1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3 * Header File for FPGA DFL User API
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>
9 * Zhang Yi <yi.z.zhang@intel.com>
10 * Wu Hao <hao.wu@intel.com>
11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
12 */
13
14 #ifndef _UAPI_LINUX_FPGA_DFL_H
15 #define _UAPI_LINUX_FPGA_DFL_H
16
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19
20 #define DFL_FPGA_API_VERSION 0
21
22 /*
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
24 * embedding the structure length (argsz) and flags into structures passed
25 * between kernel and userspace. This design referenced the VFIO IOCTL
26 * interface (include/uapi/linux/vfio.h).
27 */
28
29 #define DFL_FPGA_MAGIC 0xB6
30
31 #define DFL_FPGA_BASE 0
32 #define DFL_PORT_BASE 0x40
33 #define DFL_FME_BASE 0x80
34
35 /* Common IOCTLs for both FME and AFU file descriptor */
36
37 /**
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
39 *
40 * Report the version of the driver API.
41 * Return: Driver API Version.
42 */
43
44 #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
45
46 /**
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
48 *
49 * Check whether an extension is supported.
50 * Return: 0 if not supported, otherwise the extension is supported.
51 */
52
53 #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
54
55 /* IOCTLs for AFU file descriptor */
56
57 /**
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
59 *
60 * Reset the FPGA Port and its AFU. No parameters are supported.
61 * Userspace can do Port reset at any time, e.g. during DMA or PR. But
62 * it should never cause any system level issue, only functional failure
63 * (e.g. DMA or PR operation failure) and be recoverable from the failure.
64 * Return: 0 on success, -errno of failure
65 */
66
67 #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
68
69 /**
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
71 * struct dfl_fpga_port_info)
72 *
73 * Retrieve information about the fpga port.
74 * Driver fills the info in provided struct dfl_fpga_port_info.
75 * Return: 0 on success, -errno on failure.
76 */
77 struct dfl_fpga_port_info {
78 /* Input */
79 __u32 argsz; /* Structure length */
80 /* Output */
81 __u32 flags; /* Zero for now */
82 __u32 num_regions; /* The number of supported regions */
83 __u32 num_umsgs; /* The number of allocated umsgs */
84 };
85
86 #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)
87
88 /**
89 * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2,
90 * struct dfl_fpga_port_region_info)
91 *
92 * Retrieve information about a device memory region.
93 * Caller provides struct dfl_fpga_port_region_info with index value set.
94 * Driver returns the region info in other fields.
95 * Return: 0 on success, -errno on failure.
96 */
97 struct dfl_fpga_port_region_info {
98 /* input */
99 __u32 argsz; /* Structure length */
100 /* Output */
101 __u32 flags; /* Access permission */
102 #define DFL_PORT_REGION_READ (1 << 0) /* Region is readable */
103 #define DFL_PORT_REGION_WRITE (1 << 1) /* Region is writable */
104 #define DFL_PORT_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */
105 /* Input */
106 __u32 index; /* Region index */
107 #define DFL_PORT_REGION_INDEX_AFU 0 /* AFU */
108 #define DFL_PORT_REGION_INDEX_STP 1 /* Signal Tap */
109 __u32 padding;
110 /* Output */
111 __u64 size; /* Region size (bytes) */
112 __u64 offset; /* Region offset from start of device fd */
113 };
114
115 #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
116
117 /**
118 * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3,
119 * struct dfl_fpga_port_dma_map)
120 *
121 * Map the dma memory per user_addr and length which are provided by caller.
122 * Driver fills the iova in provided struct afu_port_dma_map.
123 * This interface only accepts page-size aligned user memory for dma mapping.
124 * Return: 0 on success, -errno on failure.
125 */
126 struct dfl_fpga_port_dma_map {
127 /* Input */
128 __u32 argsz; /* Structure length */
129 __u32 flags; /* Zero for now */
130 __u64 user_addr; /* Process virtual address */
131 __u64 length; /* Length of mapping (bytes)*/
132 /* Output */
133 __u64 iova; /* IO virtual address */
134 };
135
136 #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)
137
138 /**
139 * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4,
140 * struct dfl_fpga_port_dma_unmap)
141 *
142 * Unmap the dma memory per iova provided by caller.
143 * Return: 0 on success, -errno on failure.
144 */
145 struct dfl_fpga_port_dma_unmap {
146 /* Input */
147 __u32 argsz; /* Structure length */
148 __u32 flags; /* Zero for now */
149 __u64 iova; /* IO virtual address */
150 };
151
152 #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)
153
154 /* IOCTLs for FME file descriptor */
155
156 /**
157 * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0,
158 * struct dfl_fpga_fme_port_pr)
159 *
160 * Driver does Partial Reconfiguration based on Port ID and Buffer (Image)
161 * provided by caller.
162 * Return: 0 on success, -errno on failure.
163 * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
164 * some errors during PR, under this case, the user can fetch HW error info
165 * from the status of FME's fpga manager.
166 */
167
168 struct dfl_fpga_fme_port_pr {
169 /* Input */
170 __u32 argsz; /* Structure length */
171 __u32 flags; /* Zero for now */
172 __u32 port_id;
173 __u32 buffer_size;
174 __u64 buffer_address; /* Userspace address to the buffer for PR */
175 };
176
177 #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
178
179 /**
180 * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1,
181 * int port_id)
182 *
183 * Driver releases the port per Port ID provided by caller.
184 * Return: 0 on success, -errno on failure.
185 */
186 #define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int)
187
188 /**
189 * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2,
190 * int port_id)
191 *
192 * Driver assigns the port back per Port ID provided by caller.
193 * Return: 0 on success, -errno on failure.
194 */
195 #define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int)
196
197 #endif /* _UAPI_LINUX_FPGA_DFL_H */