root/include/uapi/sound/skl-tplg-interface.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * skl-tplg-interface.h - Intel DSP FW private data interface
   4  *
   5  * Copyright (C) 2015 Intel Corp
   6  * Author: Jeeja KP <jeeja.kp@intel.com>
   7  *          Nilofer, Samreen <samreen.nilofer@intel.com>
   8  */
   9 
  10 #ifndef __HDA_TPLG_INTERFACE_H__
  11 #define __HDA_TPLG_INTERFACE_H__
  12 
  13 #include <linux/types.h>
  14 
  15 /*
  16  * Default types range from 0~12. type can range from 0 to 0xff
  17  * SST types start at higher to avoid any overlapping in future
  18  */
  19 #define SKL_CONTROL_TYPE_BYTE_TLV       0x100
  20 #define SKL_CONTROL_TYPE_MIC_SELECT     0x102
  21 
  22 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
  23 #define MAX_IN_QUEUE 8
  24 #define MAX_OUT_QUEUE 8
  25 
  26 #define SKL_UUID_STR_SZ 40
  27 /* Event types goes here */
  28 /* Reserve event type 0 for no event handlers */
  29 enum skl_event_types {
  30         SKL_EVENT_NONE = 0,
  31         SKL_MIXER_EVENT,
  32         SKL_MUX_EVENT,
  33         SKL_VMIXER_EVENT,
  34         SKL_PGA_EVENT
  35 };
  36 
  37 /**
  38  * enum skl_ch_cfg - channel configuration
  39  *
  40  * @SKL_CH_CFG_MONO:    One channel only
  41  * @SKL_CH_CFG_STEREO:  L & R
  42  * @SKL_CH_CFG_2_1:     L, R & LFE
  43  * @SKL_CH_CFG_3_0:     L, C & R
  44  * @SKL_CH_CFG_3_1:     L, C, R & LFE
  45  * @SKL_CH_CFG_QUATRO:  L, R, Ls & Rs
  46  * @SKL_CH_CFG_4_0:     L, C, R & Cs
  47  * @SKL_CH_CFG_5_0:     L, C, R, Ls & Rs
  48  * @SKL_CH_CFG_5_1:     L, C, R, Ls, Rs & LFE
  49  * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
  50  * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
  51  * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
  52  * @SKL_CH_CFG_INVALID: Invalid
  53  */
  54 enum skl_ch_cfg {
  55         SKL_CH_CFG_MONO = 0,
  56         SKL_CH_CFG_STEREO = 1,
  57         SKL_CH_CFG_2_1 = 2,
  58         SKL_CH_CFG_3_0 = 3,
  59         SKL_CH_CFG_3_1 = 4,
  60         SKL_CH_CFG_QUATRO = 5,
  61         SKL_CH_CFG_4_0 = 6,
  62         SKL_CH_CFG_5_0 = 7,
  63         SKL_CH_CFG_5_1 = 8,
  64         SKL_CH_CFG_DUAL_MONO = 9,
  65         SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
  66         SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
  67         SKL_CH_CFG_4_CHANNEL = 12,
  68         SKL_CH_CFG_INVALID
  69 };
  70 
  71 enum skl_module_type {
  72         SKL_MODULE_TYPE_MIXER = 0,
  73         SKL_MODULE_TYPE_COPIER,
  74         SKL_MODULE_TYPE_UPDWMIX,
  75         SKL_MODULE_TYPE_SRCINT,
  76         SKL_MODULE_TYPE_ALGO,
  77         SKL_MODULE_TYPE_BASE_OUTFMT,
  78         SKL_MODULE_TYPE_KPB,
  79         SKL_MODULE_TYPE_MIC_SELECT,
  80 };
  81 
  82 enum skl_core_affinity {
  83         SKL_AFFINITY_CORE_0 = 0,
  84         SKL_AFFINITY_CORE_1,
  85         SKL_AFFINITY_CORE_MAX
  86 };
  87 
  88 enum skl_pipe_conn_type {
  89         SKL_PIPE_CONN_TYPE_NONE = 0,
  90         SKL_PIPE_CONN_TYPE_FE,
  91         SKL_PIPE_CONN_TYPE_BE
  92 };
  93 
  94 enum skl_hw_conn_type {
  95         SKL_CONN_NONE = 0,
  96         SKL_CONN_SOURCE = 1,
  97         SKL_CONN_SINK = 2
  98 };
  99 
 100 enum skl_dev_type {
 101         SKL_DEVICE_BT = 0x0,
 102         SKL_DEVICE_DMIC = 0x1,
 103         SKL_DEVICE_I2S = 0x2,
 104         SKL_DEVICE_SLIMBUS = 0x3,
 105         SKL_DEVICE_HDALINK = 0x4,
 106         SKL_DEVICE_HDAHOST = 0x5,
 107         SKL_DEVICE_NONE
 108 };
 109 
 110 /**
 111  * enum skl_interleaving - interleaving style
 112  *
 113  * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
 114  * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
 115  */
 116 enum skl_interleaving {
 117         SKL_INTERLEAVING_PER_CHANNEL = 0,
 118         SKL_INTERLEAVING_PER_SAMPLE = 1,
 119 };
 120 
 121 enum skl_sample_type {
 122         SKL_SAMPLE_TYPE_INT_MSB = 0,
 123         SKL_SAMPLE_TYPE_INT_LSB = 1,
 124         SKL_SAMPLE_TYPE_INT_SIGNED = 2,
 125         SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
 126         SKL_SAMPLE_TYPE_FLOAT = 4
 127 };
 128 
 129 enum module_pin_type {
 130         /* All pins of the module takes same PCM inputs or outputs
 131         * e.g. mixout
 132         */
 133         SKL_PIN_TYPE_HOMOGENEOUS,
 134         /* All pins of the module takes different PCM inputs or outputs
 135         * e.g mux
 136         */
 137         SKL_PIN_TYPE_HETEROGENEOUS,
 138 };
 139 
 140 enum skl_module_param_type {
 141         SKL_PARAM_DEFAULT = 0,
 142         SKL_PARAM_INIT,
 143         SKL_PARAM_SET,
 144         SKL_PARAM_BIND
 145 };
 146 
 147 struct skl_dfw_algo_data {
 148         __u32 set_params:2;
 149         __u32 rsvd:30;
 150         __u32 param_id;
 151         __u32 max;
 152         char params[0];
 153 } __packed;
 154 
 155 enum skl_tkn_dir {
 156         SKL_DIR_IN,
 157         SKL_DIR_OUT
 158 };
 159 
 160 enum skl_tuple_type {
 161         SKL_TYPE_TUPLE,
 162         SKL_TYPE_DATA
 163 };
 164 
 165 /* v4 configuration data */
 166 
 167 struct skl_dfw_v4_module_pin {
 168         __u16 module_id;
 169         __u16 instance_id;
 170 } __packed;
 171 
 172 struct skl_dfw_v4_module_fmt {
 173         __u32 channels;
 174         __u32 freq;
 175         __u32 bit_depth;
 176         __u32 valid_bit_depth;
 177         __u32 ch_cfg;
 178         __u32 interleaving_style;
 179         __u32 sample_type;
 180         __u32 ch_map;
 181 } __packed;
 182 
 183 struct skl_dfw_v4_module_caps {
 184         __u32 set_params:2;
 185         __u32 rsvd:30;
 186         __u32 param_id;
 187         __u32 caps_size;
 188         __u32 caps[HDA_SST_CFG_MAX];
 189 } __packed;
 190 
 191 struct skl_dfw_v4_pipe {
 192         __u8 pipe_id;
 193         __u8 pipe_priority;
 194         __u16 conn_type:4;
 195         __u16 rsvd:4;
 196         __u16 memory_pages:8;
 197 } __packed;
 198 
 199 struct skl_dfw_v4_module {
 200         char uuid[SKL_UUID_STR_SZ];
 201 
 202         __u16 module_id;
 203         __u16 instance_id;
 204         __u32 max_mcps;
 205         __u32 mem_pages;
 206         __u32 obs;
 207         __u32 ibs;
 208         __u32 vbus_id;
 209 
 210         __u32 max_in_queue:8;
 211         __u32 max_out_queue:8;
 212         __u32 time_slot:8;
 213         __u32 core_id:4;
 214         __u32 rsvd1:4;
 215 
 216         __u32 module_type:8;
 217         __u32 conn_type:4;
 218         __u32 dev_type:4;
 219         __u32 hw_conn_type:4;
 220         __u32 rsvd2:12;
 221 
 222         __u32 params_fixup:8;
 223         __u32 converter:8;
 224         __u32 input_pin_type:1;
 225         __u32 output_pin_type:1;
 226         __u32 is_dynamic_in_pin:1;
 227         __u32 is_dynamic_out_pin:1;
 228         __u32 is_loadable:1;
 229         __u32 rsvd3:11;
 230 
 231         struct skl_dfw_v4_pipe pipe;
 232         struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
 233         struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
 234         struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
 235         struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
 236         struct skl_dfw_v4_module_caps caps;
 237 } __packed;
 238 
 239 #endif