root/include/dt-bindings/memory/tegra114-mc.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
   3 #define DT_BINDINGS_MEMORY_TEGRA114_MC_H
   4 
   5 #define TEGRA_SWGROUP_PTC       0
   6 #define TEGRA_SWGROUP_DC        1
   7 #define TEGRA_SWGROUP_DCB       2
   8 #define TEGRA_SWGROUP_EPP       3
   9 #define TEGRA_SWGROUP_G2        4
  10 #define TEGRA_SWGROUP_AVPC      5
  11 #define TEGRA_SWGROUP_NV        6
  12 #define TEGRA_SWGROUP_HDA       7
  13 #define TEGRA_SWGROUP_HC        8
  14 #define TEGRA_SWGROUP_MSENC     9
  15 #define TEGRA_SWGROUP_PPCS      10
  16 #define TEGRA_SWGROUP_VDE       11
  17 #define TEGRA_SWGROUP_MPCORELP  12
  18 #define TEGRA_SWGROUP_MPCORE    13
  19 #define TEGRA_SWGROUP_VI        14
  20 #define TEGRA_SWGROUP_ISP       15
  21 #define TEGRA_SWGROUP_XUSB_HOST 16
  22 #define TEGRA_SWGROUP_XUSB_DEV  17
  23 #define TEGRA_SWGROUP_EMUCIF    18
  24 #define TEGRA_SWGROUP_TSEC      19
  25 
  26 #define TEGRA114_MC_RESET_AVPC          0
  27 #define TEGRA114_MC_RESET_DC            1
  28 #define TEGRA114_MC_RESET_DCB           2
  29 #define TEGRA114_MC_RESET_EPP           3
  30 #define TEGRA114_MC_RESET_2D            4
  31 #define TEGRA114_MC_RESET_HC            5
  32 #define TEGRA114_MC_RESET_HDA           6
  33 #define TEGRA114_MC_RESET_ISP           7
  34 #define TEGRA114_MC_RESET_MPCORE        8
  35 #define TEGRA114_MC_RESET_MPCORELP      9
  36 #define TEGRA114_MC_RESET_MPE           10
  37 #define TEGRA114_MC_RESET_3D            11
  38 #define TEGRA114_MC_RESET_3D2           12
  39 #define TEGRA114_MC_RESET_PPCS          13
  40 #define TEGRA114_MC_RESET_VDE           14
  41 #define TEGRA114_MC_RESET_VI            15
  42 
  43 #endif