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6 #ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
7 #define _DT_BINDINGS_CLK_LCC_MSM8960_H
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9 #define PLL4 0
10 #define MI2S_OSR_SRC 1
11 #define MI2S_OSR_CLK 2
12 #define MI2S_DIV_CLK 3
13 #define MI2S_BIT_DIV_CLK 4
14 #define MI2S_BIT_CLK 5
15 #define PCM_SRC 6
16 #define PCM_CLK_OUT 7
17 #define PCM_CLK 8
18 #define SLIMBUS_SRC 9
19 #define AUDIO_SLIMBUS_CLK 10
20 #define SPS_SLIMBUS_CLK 11
21 #define CODEC_I2S_MIC_OSR_SRC 12
22 #define CODEC_I2S_MIC_OSR_CLK 13
23 #define CODEC_I2S_MIC_DIV_CLK 14
24 #define CODEC_I2S_MIC_BIT_DIV_CLK 15
25 #define CODEC_I2S_MIC_BIT_CLK 16
26 #define SPARE_I2S_MIC_OSR_SRC 17
27 #define SPARE_I2S_MIC_OSR_CLK 18
28 #define SPARE_I2S_MIC_DIV_CLK 19
29 #define SPARE_I2S_MIC_BIT_DIV_CLK 20
30 #define SPARE_I2S_MIC_BIT_CLK 21
31 #define CODEC_I2S_SPKR_OSR_SRC 22
32 #define CODEC_I2S_SPKR_OSR_CLK 23
33 #define CODEC_I2S_SPKR_DIV_CLK 24
34 #define CODEC_I2S_SPKR_BIT_DIV_CLK 25
35 #define CODEC_I2S_SPKR_BIT_CLK 26
36 #define SPARE_I2S_SPKR_OSR_SRC 27
37 #define SPARE_I2S_SPKR_OSR_CLK 28
38 #define SPARE_I2S_SPKR_DIV_CLK 29
39 #define SPARE_I2S_SPKR_BIT_DIV_CLK 30
40 #define SPARE_I2S_SPKR_BIT_CLK 31
41
42 #endif