root/include/dt-bindings/clock/r8a7745-cpg-mssr.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  *
   3  * Copyright (C) 2016 Cogent Embedded Inc.
   4  */
   5 #ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
   6 #define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
   7 
   8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   9 
  10 /* r8a7745 CPG Core Clocks */
  11 #define R8A7745_CLK_Z2          0
  12 #define R8A7745_CLK_ZG          1
  13 #define R8A7745_CLK_ZTR         2
  14 #define R8A7745_CLK_ZTRD2       3
  15 #define R8A7745_CLK_ZT          4
  16 #define R8A7745_CLK_ZX          5
  17 #define R8A7745_CLK_ZS          6
  18 #define R8A7745_CLK_HP          7
  19 #define R8A7745_CLK_B           9
  20 #define R8A7745_CLK_LB          10
  21 #define R8A7745_CLK_P           11
  22 #define R8A7745_CLK_CL          12
  23 #define R8A7745_CLK_CP          13
  24 #define R8A7745_CLK_M2          14
  25 #define R8A7745_CLK_ZB3         16
  26 #define R8A7745_CLK_ZB3D2       17
  27 #define R8A7745_CLK_DDR         18
  28 #define R8A7745_CLK_SDH         19
  29 #define R8A7745_CLK_SD0         20
  30 #define R8A7745_CLK_SD2         21
  31 #define R8A7745_CLK_SD3         22
  32 #define R8A7745_CLK_MMC0        23
  33 #define R8A7745_CLK_MP          24
  34 #define R8A7745_CLK_QSPI        25
  35 #define R8A7745_CLK_CPEX        26
  36 #define R8A7745_CLK_RCAN        27
  37 #define R8A7745_CLK_R           28
  38 #define R8A7745_CLK_OSC         29
  39 
  40 #endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */