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8 #ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H
9 #define _DT_BINDINGS_CLK_LCC_MDM9615_H
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11 #define PLL4 0
12 #define MI2S_OSR_SRC 1
13 #define MI2S_OSR_CLK 2
14 #define MI2S_DIV_CLK 3
15 #define MI2S_BIT_DIV_CLK 4
16 #define MI2S_BIT_CLK 5
17 #define PCM_SRC 6
18 #define PCM_CLK_OUT 7
19 #define PCM_CLK 8
20 #define SLIMBUS_SRC 9
21 #define AUDIO_SLIMBUS_CLK 10
22 #define SPS_SLIMBUS_CLK 11
23 #define CODEC_I2S_MIC_OSR_SRC 12
24 #define CODEC_I2S_MIC_OSR_CLK 13
25 #define CODEC_I2S_MIC_DIV_CLK 14
26 #define CODEC_I2S_MIC_BIT_DIV_CLK 15
27 #define CODEC_I2S_MIC_BIT_CLK 16
28 #define SPARE_I2S_MIC_OSR_SRC 17
29 #define SPARE_I2S_MIC_OSR_CLK 18
30 #define SPARE_I2S_MIC_DIV_CLK 19
31 #define SPARE_I2S_MIC_BIT_DIV_CLK 20
32 #define SPARE_I2S_MIC_BIT_CLK 21
33 #define CODEC_I2S_SPKR_OSR_SRC 22
34 #define CODEC_I2S_SPKR_OSR_CLK 23
35 #define CODEC_I2S_SPKR_DIV_CLK 24
36 #define CODEC_I2S_SPKR_BIT_DIV_CLK 25
37 #define CODEC_I2S_SPKR_BIT_CLK 26
38 #define SPARE_I2S_SPKR_OSR_SRC 27
39 #define SPARE_I2S_SPKR_OSR_CLK 28
40 #define SPARE_I2S_SPKR_DIV_CLK 29
41 #define SPARE_I2S_SPKR_BIT_DIV_CLK 30
42 #define SPARE_I2S_SPKR_BIT_CLK 31
43
44 #endif