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43 #ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
44 #define _DT_BINDINGS_CLK_SUN6I_A31_H_
45
46 #define CLK_PLL_VIDEO0_2X 7
47
48 #define CLK_PLL_PERIPH 10
49
50 #define CLK_PLL_VIDEO1_2X 13
51
52 #define CLK_CPU 18
53
54 #define CLK_AHB1_MIPIDSI 23
55 #define CLK_AHB1_SS 24
56 #define CLK_AHB1_DMA 25
57 #define CLK_AHB1_MMC0 26
58 #define CLK_AHB1_MMC1 27
59 #define CLK_AHB1_MMC2 28
60 #define CLK_AHB1_MMC3 29
61 #define CLK_AHB1_NAND1 30
62 #define CLK_AHB1_NAND0 31
63 #define CLK_AHB1_SDRAM 32
64 #define CLK_AHB1_EMAC 33
65 #define CLK_AHB1_TS 34
66 #define CLK_AHB1_HSTIMER 35
67 #define CLK_AHB1_SPI0 36
68 #define CLK_AHB1_SPI1 37
69 #define CLK_AHB1_SPI2 38
70 #define CLK_AHB1_SPI3 39
71 #define CLK_AHB1_OTG 40
72 #define CLK_AHB1_EHCI0 41
73 #define CLK_AHB1_EHCI1 42
74 #define CLK_AHB1_OHCI0 43
75 #define CLK_AHB1_OHCI1 44
76 #define CLK_AHB1_OHCI2 45
77 #define CLK_AHB1_VE 46
78 #define CLK_AHB1_LCD0 47
79 #define CLK_AHB1_LCD1 48
80 #define CLK_AHB1_CSI 49
81 #define CLK_AHB1_HDMI 50
82 #define CLK_AHB1_BE0 51
83 #define CLK_AHB1_BE1 52
84 #define CLK_AHB1_FE0 53
85 #define CLK_AHB1_FE1 54
86 #define CLK_AHB1_MP 55
87 #define CLK_AHB1_GPU 56
88 #define CLK_AHB1_DEU0 57
89 #define CLK_AHB1_DEU1 58
90 #define CLK_AHB1_DRC0 59
91 #define CLK_AHB1_DRC1 60
92
93 #define CLK_APB1_CODEC 61
94 #define CLK_APB1_SPDIF 62
95 #define CLK_APB1_DIGITAL_MIC 63
96 #define CLK_APB1_PIO 64
97 #define CLK_APB1_DAUDIO0 65
98 #define CLK_APB1_DAUDIO1 66
99
100 #define CLK_APB2_I2C0 67
101 #define CLK_APB2_I2C1 68
102 #define CLK_APB2_I2C2 69
103 #define CLK_APB2_I2C3 70
104 #define CLK_APB2_UART0 71
105 #define CLK_APB2_UART1 72
106 #define CLK_APB2_UART2 73
107 #define CLK_APB2_UART3 74
108 #define CLK_APB2_UART4 75
109 #define CLK_APB2_UART5 76
110
111 #define CLK_NAND0 77
112 #define CLK_NAND1 78
113 #define CLK_MMC0 79
114 #define CLK_MMC0_SAMPLE 80
115 #define CLK_MMC0_OUTPUT 81
116 #define CLK_MMC1 82
117 #define CLK_MMC1_SAMPLE 83
118 #define CLK_MMC1_OUTPUT 84
119 #define CLK_MMC2 85
120 #define CLK_MMC2_SAMPLE 86
121 #define CLK_MMC2_OUTPUT 87
122 #define CLK_MMC3 88
123 #define CLK_MMC3_SAMPLE 89
124 #define CLK_MMC3_OUTPUT 90
125 #define CLK_TS 91
126 #define CLK_SS 92
127 #define CLK_SPI0 93
128 #define CLK_SPI1 94
129 #define CLK_SPI2 95
130 #define CLK_SPI3 96
131 #define CLK_DAUDIO0 97
132 #define CLK_DAUDIO1 98
133 #define CLK_SPDIF 99
134 #define CLK_USB_PHY0 100
135 #define CLK_USB_PHY1 101
136 #define CLK_USB_PHY2 102
137 #define CLK_USB_OHCI0 103
138 #define CLK_USB_OHCI1 104
139 #define CLK_USB_OHCI2 105
140
141 #define CLK_DRAM_VE 110
142 #define CLK_DRAM_CSI_ISP 111
143 #define CLK_DRAM_TS 112
144 #define CLK_DRAM_DRC0 113
145 #define CLK_DRAM_DRC1 114
146 #define CLK_DRAM_DEU0 115
147 #define CLK_DRAM_DEU1 116
148 #define CLK_DRAM_FE0 117
149 #define CLK_DRAM_FE1 118
150 #define CLK_DRAM_BE0 119
151 #define CLK_DRAM_BE1 120
152 #define CLK_DRAM_MP 121
153
154 #define CLK_BE0 122
155 #define CLK_BE1 123
156 #define CLK_FE0 124
157 #define CLK_FE1 125
158 #define CLK_MP 126
159 #define CLK_LCD0_CH0 127
160 #define CLK_LCD1_CH0 128
161 #define CLK_LCD0_CH1 129
162 #define CLK_LCD1_CH1 130
163 #define CLK_CSI0_SCLK 131
164 #define CLK_CSI0_MCLK 132
165 #define CLK_CSI1_MCLK 133
166 #define CLK_VE 134
167 #define CLK_CODEC 135
168 #define CLK_AVS 136
169 #define CLK_DIGITAL_MIC 137
170 #define CLK_HDMI 138
171 #define CLK_HDMI_DDC 139
172 #define CLK_PS 140
173
174 #define CLK_MIPI_DSI 143
175 #define CLK_MIPI_DSI_DPHY 144
176 #define CLK_MIPI_CSI_DPHY 145
177 #define CLK_IEP_DRC0 146
178 #define CLK_IEP_DRC1 147
179 #define CLK_IEP_DEU0 148
180 #define CLK_IEP_DEU1 149
181 #define CLK_GPU_CORE 150
182 #define CLK_GPU_MEMORY 151
183 #define CLK_GPU_HYD 152
184 #define CLK_ATS 153
185 #define CLK_TRACE 154
186
187 #define CLK_OUT_A 155
188 #define CLK_OUT_B 156
189 #define CLK_OUT_C 157
190
191 #endif