1
2
3
4
5 #ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
6 #define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
7
8
9
10
11
12
13
14 #define R8A7790_PD_CA15_CPU0 0
15 #define R8A7790_PD_CA15_CPU1 1
16 #define R8A7790_PD_CA15_CPU2 2
17 #define R8A7790_PD_CA15_CPU3 3
18 #define R8A7790_PD_CA7_CPU0 5
19 #define R8A7790_PD_CA7_CPU1 6
20 #define R8A7790_PD_CA7_CPU2 7
21 #define R8A7790_PD_CA7_CPU3 8
22 #define R8A7790_PD_CA15_SCU 12
23 #define R8A7790_PD_SH_4A 16
24 #define R8A7790_PD_RGX 20
25 #define R8A7790_PD_CA7_SCU 21
26 #define R8A7790_PD_IMP 24
27
28
29 #define R8A7790_PD_ALWAYS_ON 32
30
31 #endif