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21 #ifndef __XEN_PUBLIC_PHYSDEV_H__
22 #define __XEN_PUBLIC_PHYSDEV_H__
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34
35 #define PHYSDEVOP_eoi 12
36 struct physdev_eoi {
37
38 uint32_t irq;
39 };
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46
47
48 #define PHYSDEVOP_pirq_eoi_gmfn_v1 17
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55
56 #define PHYSDEVOP_pirq_eoi_gmfn_v2 28
57 struct physdev_pirq_eoi_gmfn {
58
59 xen_ulong_t gmfn;
60 };
61
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64
65
66 #define PHYSDEVOP_irq_status_query 5
67 struct physdev_irq_status_query {
68
69 uint32_t irq;
70
71 uint32_t flags;
72 };
73
74
75 #define _XENIRQSTAT_needs_eoi (0)
76 #define XENIRQSTAT_needs_eoi (1U<<_XENIRQSTAT_needs_eoi)
77
78
79 #define _XENIRQSTAT_shared (1)
80 #define XENIRQSTAT_shared (1U<<_XENIRQSTAT_shared)
81
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85
86 #define PHYSDEVOP_set_iopl 6
87 struct physdev_set_iopl {
88
89 uint32_t iopl;
90 };
91
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95
96 #define PHYSDEVOP_set_iobitmap 7
97 struct physdev_set_iobitmap {
98
99 uint8_t * bitmap;
100 uint32_t nr_ports;
101 };
102
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105
106
107 #define PHYSDEVOP_apic_read 8
108 #define PHYSDEVOP_apic_write 9
109 struct physdev_apic {
110
111 unsigned long apic_physbase;
112 uint32_t reg;
113
114 uint32_t value;
115 };
116
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118
119
120
121 #define PHYSDEVOP_alloc_irq_vector 10
122 #define PHYSDEVOP_free_irq_vector 11
123 struct physdev_irq {
124
125 uint32_t irq;
126
127 uint32_t vector;
128 };
129
130 #define MAP_PIRQ_TYPE_MSI 0x0
131 #define MAP_PIRQ_TYPE_GSI 0x1
132 #define MAP_PIRQ_TYPE_UNKNOWN 0x2
133 #define MAP_PIRQ_TYPE_MSI_SEG 0x3
134 #define MAP_PIRQ_TYPE_MULTI_MSI 0x4
135
136 #define PHYSDEVOP_map_pirq 13
137 struct physdev_map_pirq {
138 domid_t domid;
139
140 int type;
141
142 int index;
143
144 int pirq;
145
146 int bus;
147
148 int devfn;
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153
154
155 int entry_nr;
156
157 uint64_t table_base;
158 };
159
160 #define PHYSDEVOP_unmap_pirq 14
161 struct physdev_unmap_pirq {
162 domid_t domid;
163
164 int pirq;
165 };
166
167 #define PHYSDEVOP_manage_pci_add 15
168 #define PHYSDEVOP_manage_pci_remove 16
169 struct physdev_manage_pci {
170
171 uint8_t bus;
172 uint8_t devfn;
173 };
174
175 #define PHYSDEVOP_restore_msi 19
176 struct physdev_restore_msi {
177
178 uint8_t bus;
179 uint8_t devfn;
180 };
181
182 #define PHYSDEVOP_manage_pci_add_ext 20
183 struct physdev_manage_pci_ext {
184
185 uint8_t bus;
186 uint8_t devfn;
187 unsigned is_extfn;
188 unsigned is_virtfn;
189 struct {
190 uint8_t bus;
191 uint8_t devfn;
192 } physfn;
193 };
194
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197
198
199 struct physdev_op {
200 uint32_t cmd;
201 union {
202 struct physdev_irq_status_query irq_status_query;
203 struct physdev_set_iopl set_iopl;
204 struct physdev_set_iobitmap set_iobitmap;
205 struct physdev_apic apic_op;
206 struct physdev_irq irq_op;
207 } u;
208 };
209
210 #define PHYSDEVOP_setup_gsi 21
211 struct physdev_setup_gsi {
212 int gsi;
213
214 uint8_t triggering;
215
216 uint8_t polarity;
217
218 };
219
220 #define PHYSDEVOP_get_nr_pirqs 22
221 struct physdev_nr_pirqs {
222
223 uint32_t nr_pirqs;
224 };
225
226
227
228 #define PHYSDEVOP_get_free_pirq 23
229 struct physdev_get_free_pirq {
230
231 int type;
232
233 uint32_t pirq;
234 };
235
236 #define XEN_PCI_DEV_EXTFN 0x1
237 #define XEN_PCI_DEV_VIRTFN 0x2
238 #define XEN_PCI_DEV_PXM 0x4
239
240 #define XEN_PCI_MMCFG_RESERVED 0x1
241
242 #define PHYSDEVOP_pci_mmcfg_reserved 24
243 struct physdev_pci_mmcfg_reserved {
244 uint64_t address;
245 uint16_t segment;
246 uint8_t start_bus;
247 uint8_t end_bus;
248 uint32_t flags;
249 };
250
251 #define PHYSDEVOP_pci_device_add 25
252 struct physdev_pci_device_add {
253
254 uint16_t seg;
255 uint8_t bus;
256 uint8_t devfn;
257 uint32_t flags;
258 struct {
259 uint8_t bus;
260 uint8_t devfn;
261 } physfn;
262 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
263 uint32_t optarr[];
264 #elif defined(__GNUC__)
265 uint32_t optarr[0];
266 #endif
267 };
268
269 #define PHYSDEVOP_pci_device_remove 26
270 #define PHYSDEVOP_restore_msi_ext 27
271
272
273
274
275 #define PHYSDEVOP_prepare_msix 30
276 #define PHYSDEVOP_release_msix 31
277 struct physdev_pci_device {
278
279 uint16_t seg;
280 uint8_t bus;
281 uint8_t devfn;
282 };
283
284 #define PHYSDEVOP_DBGP_RESET_PREPARE 1
285 #define PHYSDEVOP_DBGP_RESET_DONE 2
286
287 #define PHYSDEVOP_DBGP_BUS_UNKNOWN 0
288 #define PHYSDEVOP_DBGP_BUS_PCI 1
289
290 #define PHYSDEVOP_dbgp_op 29
291 struct physdev_dbgp_op {
292
293 uint8_t op;
294 uint8_t bus;
295 union {
296 struct physdev_pci_device pci;
297 } u;
298 };
299
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303
304
305 #define PHYSDEVOP_IRQ_UNMASK_NOTIFY 4
306
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310
311 #define PHYSDEVOP_IRQ_STATUS_QUERY PHYSDEVOP_irq_status_query
312 #define PHYSDEVOP_SET_IOPL PHYSDEVOP_set_iopl
313 #define PHYSDEVOP_SET_IOBITMAP PHYSDEVOP_set_iobitmap
314 #define PHYSDEVOP_APIC_READ PHYSDEVOP_apic_read
315 #define PHYSDEVOP_APIC_WRITE PHYSDEVOP_apic_write
316 #define PHYSDEVOP_ASSIGN_VECTOR PHYSDEVOP_alloc_irq_vector
317 #define PHYSDEVOP_FREE_VECTOR PHYSDEVOP_free_irq_vector
318 #define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
319 #define PHYSDEVOP_IRQ_SHARED XENIRQSTAT_shared
320
321 #endif