root/include/linux/ssb/ssb_regs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef LINUX_SSB_REGS_H_
   3 #define LINUX_SSB_REGS_H_
   4 
   5 
   6 /* SiliconBackplane Address Map.
   7  * All regions may not exist on all chips.
   8  */
   9 #define SSB_SDRAM_BASE          0x00000000U     /* Physical SDRAM */
  10 #define SSB_PCI_MEM             0x08000000U     /* Host Mode sb2pcitranslation0 (64 MB) */
  11 #define SSB_PCI_CFG             0x0c000000U     /* Host Mode sb2pcitranslation1 (64 MB) */
  12 #define SSB_SDRAM_SWAPPED       0x10000000U     /* Byteswapped Physical SDRAM */
  13 #define SSB_ENUM_BASE           0x18000000U     /* Enumeration space base */
  14 #define SSB_ENUM_LIMIT          0x18010000U     /* Enumeration space limit */
  15 
  16 #define SSB_FLASH2              0x1c000000U     /* Flash Region 2 (region 1 shadowed here) */
  17 #define SSB_FLASH2_SZ           0x02000000U     /* Size of Flash Region 2 */
  18 
  19 #define SSB_EXTIF_BASE          0x1f000000U     /* External Interface region base address */
  20 #define SSB_FLASH1              0x1fc00000U     /* Flash Region 1 */
  21 #define SSB_FLASH1_SZ           0x00400000U     /* Size of Flash Region 1 */
  22 
  23 #define SSB_PCI_DMA             0x40000000U     /* Client Mode sb2pcitranslation2 (1 GB) */
  24 #define SSB_PCI_DMA_SZ          0x40000000U     /* Client Mode sb2pcitranslation2 size in bytes */
  25 #define SSB_PCIE_DMA_L32        0x00000000U     /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
  26 #define SSB_PCIE_DMA_H32        0x80000000U     /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
  27 #define SSB_EUART               (SSB_EXTIF_BASE + 0x00800000)
  28 #define SSB_LED                 (SSB_EXTIF_BASE + 0x00900000)
  29 
  30 
  31 /* Enumeration space constants */
  32 #define SSB_CORE_SIZE           0x1000  /* Size of a core MMIO area */
  33 #define SSB_MAX_NR_CORES        ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
  34 
  35 
  36 /* mips address */
  37 #define SSB_EJTAG               0xff200000      /* MIPS EJTAG space (2M) */
  38 
  39 
  40 /* SSB PCI config space registers. */
  41 #define SSB_PMCSR               0x44
  42 #define  SSB_PE                 0x100
  43 #define SSB_BAR0_WIN            0x80    /* Backplane address space 0 */
  44 #define SSB_BAR1_WIN            0x84    /* Backplane address space 1 */
  45 #define SSB_SPROMCTL            0x88    /* SPROM control */
  46 #define  SSB_SPROMCTL_WE        0x10    /* SPROM write enable */
  47 #define SSB_BAR1_CONTROL        0x8c    /* Address space 1 burst control */
  48 #define SSB_PCI_IRQS            0x90    /* PCI interrupts */
  49 #define SSB_PCI_IRQMASK         0x94    /* PCI IRQ control and mask (pcirev >= 6 only) */
  50 #define SSB_BACKPLANE_IRQS      0x98    /* Backplane Interrupts */
  51 #define SSB_GPIO_IN             0xB0    /* GPIO Input (pcirev >= 3 only) */
  52 #define SSB_GPIO_OUT            0xB4    /* GPIO Output (pcirev >= 3 only) */
  53 #define SSB_GPIO_OUT_ENABLE     0xB8    /* GPIO Output Enable/Disable (pcirev >= 3 only) */
  54 #define  SSB_GPIO_SCS           0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
  55 #define  SSB_GPIO_HWRAD         0x20    /* PCI config space GPIO 13 for hw radio disable */
  56 #define  SSB_GPIO_XTAL          0x40    /* PCI config space GPIO 14 for Xtal powerup */
  57 #define  SSB_GPIO_PLL           0x80    /* PCI config space GPIO 15 for PLL powerdown */
  58 
  59 
  60 #define SSB_BAR0_MAX_RETRIES    50
  61 
  62 /* Silicon backplane configuration register definitions */
  63 #define SSB_IPSFLAG             0x0F08
  64 #define  SSB_IPSFLAG_IRQ1       0x0000003F /* which sbflags get routed to mips interrupt 1 */
  65 #define  SSB_IPSFLAG_IRQ1_SHIFT 0
  66 #define  SSB_IPSFLAG_IRQ2       0x00003F00 /* which sbflags get routed to mips interrupt 2 */
  67 #define  SSB_IPSFLAG_IRQ2_SHIFT 8
  68 #define  SSB_IPSFLAG_IRQ3       0x003F0000 /* which sbflags get routed to mips interrupt 3 */
  69 #define  SSB_IPSFLAG_IRQ3_SHIFT 16
  70 #define  SSB_IPSFLAG_IRQ4       0x3F000000 /* which sbflags get routed to mips interrupt 4 */
  71 #define  SSB_IPSFLAG_IRQ4_SHIFT 24
  72 #define SSB_TPSFLAG             0x0F18
  73 #define  SSB_TPSFLAG_BPFLAG     0x0000003F /* Backplane flag # */
  74 #define  SSB_TPSFLAG_ALWAYSIRQ  0x00000040 /* IRQ is always sent on the Backplane */
  75 #define SSB_TMERRLOGA           0x0F48
  76 #define SSB_TMERRLOG            0x0F50
  77 #define SSB_ADMATCH3            0x0F60
  78 #define SSB_ADMATCH2            0x0F68
  79 #define SSB_ADMATCH1            0x0F70
  80 #define SSB_IMSTATE             0x0F90     /* SB Initiator Agent State */
  81 #define  SSB_IMSTATE_PC         0x0000000f /* Pipe Count */
  82 #define  SSB_IMSTATE_AP_MASK    0x00000030 /* Arbitration Priority */
  83 #define  SSB_IMSTATE_AP_BOTH    0x00000000 /* Use both timeslices and token */
  84 #define  SSB_IMSTATE_AP_TS      0x00000010 /* Use timeslices only */
  85 #define  SSB_IMSTATE_AP_TK      0x00000020 /* Use token only */
  86 #define  SSB_IMSTATE_AP_RSV     0x00000030 /* Reserved */
  87 #define  SSB_IMSTATE_IBE        0x00020000 /* In Band Error */
  88 #define  SSB_IMSTATE_TO         0x00040000 /* Timeout */
  89 #define  SSB_IMSTATE_BUSY       0x01800000 /* Busy (Backplane rev >= 2.3 only) */
  90 #define  SSB_IMSTATE_REJECT     0x02000000 /* Reject (Backplane rev >= 2.3 only) */
  91 #define SSB_INTVEC              0x0F94     /* SB Interrupt Mask */
  92 #define  SSB_INTVEC_PCI         0x00000001 /* Enable interrupts for PCI */
  93 #define  SSB_INTVEC_ENET0       0x00000002 /* Enable interrupts for enet 0 */
  94 #define  SSB_INTVEC_ILINE20     0x00000004 /* Enable interrupts for iline20 */
  95 #define  SSB_INTVEC_CODEC       0x00000008 /* Enable interrupts for v90 codec */
  96 #define  SSB_INTVEC_USB         0x00000010 /* Enable interrupts for usb */
  97 #define  SSB_INTVEC_EXTIF       0x00000020 /* Enable interrupts for external i/f */
  98 #define  SSB_INTVEC_ENET1       0x00000040 /* Enable interrupts for enet 1 */
  99 #define SSB_TMSLOW              0x0F98     /* SB Target State Low */
 100 #define  SSB_TMSLOW_RESET       0x00000001 /* Reset */
 101 #define  SSB_TMSLOW_REJECT      0x00000002 /* Reject (Standard Backplane) */
 102 #define  SSB_TMSLOW_REJECT_23   0x00000004 /* Reject (Backplane rev 2.3) */
 103 #define  SSB_TMSLOW_CLOCK       0x00010000 /* Clock Enable */
 104 #define  SSB_TMSLOW_FGC         0x00020000 /* Force Gated Clocks On */
 105 #define  SSB_TMSLOW_PE          0x40000000 /* Power Management Enable */
 106 #define  SSB_TMSLOW_BE          0x80000000 /* BIST Enable */
 107 #define SSB_TMSHIGH             0x0F9C     /* SB Target State High */
 108 #define  SSB_TMSHIGH_SERR       0x00000001 /* S-error */
 109 #define  SSB_TMSHIGH_INT        0x00000002 /* Interrupt */
 110 #define  SSB_TMSHIGH_BUSY       0x00000004 /* Busy */
 111 #define  SSB_TMSHIGH_TO         0x00000020 /* Timeout. Backplane rev >= 2.3 only */
 112 #define  SSB_TMSHIGH_COREFL     0x1FFF0000 /* Core specific flags */
 113 #define  SSB_TMSHIGH_COREFL_SHIFT       16
 114 #define  SSB_TMSHIGH_DMA64      0x10000000 /* 64bit DMA supported */
 115 #define  SSB_TMSHIGH_GCR        0x20000000 /* Gated Clock Request */
 116 #define  SSB_TMSHIGH_BISTF      0x40000000 /* BIST Failed */
 117 #define  SSB_TMSHIGH_BISTD      0x80000000 /* BIST Done */
 118 #define SSB_BWA0                0x0FA0
 119 #define SSB_IMCFGLO             0x0FA8
 120 #define  SSB_IMCFGLO_SERTO      0x00000007 /* Service timeout */
 121 #define  SSB_IMCFGLO_REQTO      0x00000070 /* Request timeout */
 122 #define  SSB_IMCFGLO_REQTO_SHIFT        4
 123 #define  SSB_IMCFGLO_CONNID     0x00FF0000 /* Connection ID */
 124 #define  SSB_IMCFGLO_CONNID_SHIFT       16
 125 #define SSB_IMCFGHI             0x0FAC
 126 #define SSB_ADMATCH0            0x0FB0
 127 #define SSB_TMCFGLO             0x0FB8
 128 #define SSB_TMCFGHI             0x0FBC
 129 #define SSB_BCONFIG             0x0FC0
 130 #define SSB_BSTATE              0x0FC8
 131 #define SSB_ACTCFG              0x0FD8
 132 #define SSB_FLAGST              0x0FE8
 133 #define SSB_IDLOW               0x0FF8
 134 #define  SSB_IDLOW_CFGSP        0x00000003 /* Config Space */
 135 #define  SSB_IDLOW_ADDRNGE      0x00000038 /* Address Ranges supported */
 136 #define  SSB_IDLOW_ADDRNGE_SHIFT        3
 137 #define  SSB_IDLOW_SYNC         0x00000040
 138 #define  SSB_IDLOW_INITIATOR    0x00000080
 139 #define  SSB_IDLOW_MIBL         0x00000F00 /* Minimum Backplane latency */
 140 #define  SSB_IDLOW_MIBL_SHIFT   8
 141 #define  SSB_IDLOW_MABL         0x0000F000 /* Maximum Backplane latency */
 142 #define  SSB_IDLOW_MABL_SHIFT   12
 143 #define  SSB_IDLOW_TIF          0x00010000 /* This Initiator is first */
 144 #define  SSB_IDLOW_CCW          0x000C0000 /* Cycle counter width */
 145 #define  SSB_IDLOW_CCW_SHIFT    18
 146 #define  SSB_IDLOW_TPT          0x00F00000 /* Target ports */
 147 #define  SSB_IDLOW_TPT_SHIFT    20
 148 #define  SSB_IDLOW_INITP        0x0F000000 /* Initiator ports */
 149 #define  SSB_IDLOW_INITP_SHIFT  24
 150 #define  SSB_IDLOW_SSBREV       0xF0000000 /* Sonics Backplane Revision code */
 151 #define  SSB_IDLOW_SSBREV_22    0x00000000 /* <= 2.2 */
 152 #define  SSB_IDLOW_SSBREV_23    0x10000000 /* 2.3 */
 153 #define  SSB_IDLOW_SSBREV_24    0x40000000 /* ?? Found in BCM4328 */
 154 #define  SSB_IDLOW_SSBREV_25    0x50000000 /* ?? Not Found yet */
 155 #define  SSB_IDLOW_SSBREV_26    0x60000000 /* ?? Found in some BCM4311/2 */
 156 #define  SSB_IDLOW_SSBREV_27    0x70000000 /* ?? Found in some BCM4311/2 */
 157 #define SSB_IDHIGH              0x0FFC     /* SB Identification High */
 158 #define  SSB_IDHIGH_RCLO        0x0000000F /* Revision Code (low part) */
 159 #define  SSB_IDHIGH_CC          0x00008FF0 /* Core Code */
 160 #define  SSB_IDHIGH_CC_SHIFT    4
 161 #define  SSB_IDHIGH_RCHI        0x00007000 /* Revision Code (high part) */
 162 #define  SSB_IDHIGH_RCHI_SHIFT  8          /* yes, shift 8 is right */
 163 #define  SSB_IDHIGH_VC          0xFFFF0000 /* Vendor Code */
 164 #define  SSB_IDHIGH_VC_SHIFT    16
 165 
 166 /* SPROM shadow area. If not otherwise noted, fields are
 167  * two bytes wide. Note that the SPROM can _only_ be read
 168  * in two-byte quantities.
 169  */
 170 #define SSB_SPROMSIZE_WORDS             64
 171 #define SSB_SPROMSIZE_BYTES             (SSB_SPROMSIZE_WORDS * sizeof(u16))
 172 #define SSB_SPROMSIZE_WORDS_R123        64
 173 #define SSB_SPROMSIZE_WORDS_R4          220
 174 #define SSB_SPROMSIZE_BYTES_R123        (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
 175 #define SSB_SPROMSIZE_BYTES_R4          (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
 176 #define SSB_SPROMSIZE_WORDS_R10         230
 177 #define SSB_SPROMSIZE_WORDS_R11         234
 178 #define SSB_SPROM_BASE1                 0x1000
 179 #define SSB_SPROM_BASE31                0x0800
 180 #define SSB_SPROM_REVISION              0x007E
 181 #define  SSB_SPROM_REVISION_REV         0x00FF  /* SPROM Revision number */
 182 #define  SSB_SPROM_REVISION_CRC         0xFF00  /* SPROM CRC8 value */
 183 #define  SSB_SPROM_REVISION_CRC_SHIFT   8
 184 
 185 /* SPROM Revision 1 */
 186 #define SSB_SPROM1_SPID                 0x0004  /* Subsystem Product ID for PCI */
 187 #define SSB_SPROM1_SVID                 0x0006  /* Subsystem Vendor ID for PCI */
 188 #define SSB_SPROM1_PID                  0x0008  /* Product ID for PCI */
 189 #define SSB_SPROM1_IL0MAC               0x0048  /* 6 bytes MAC address for 802.11b/g */
 190 #define SSB_SPROM1_ET0MAC               0x004E  /* 6 bytes MAC address for Ethernet */
 191 #define SSB_SPROM1_ET1MAC               0x0054  /* 6 bytes MAC address for 802.11a */
 192 #define SSB_SPROM1_ETHPHY               0x005A  /* Ethernet PHY settings */
 193 #define  SSB_SPROM1_ETHPHY_ET0A         0x001F  /* MII Address for enet0 */
 194 #define  SSB_SPROM1_ETHPHY_ET1A         0x03E0  /* MII Address for enet1 */
 195 #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT   5
 196 #define  SSB_SPROM1_ETHPHY_ET0M         (1<<14) /* MDIO for enet0 */
 197 #define  SSB_SPROM1_ETHPHY_ET1M         (1<<15) /* MDIO for enet1 */
 198 #define SSB_SPROM1_BINF                 0x005C  /* Board info */
 199 #define  SSB_SPROM1_BINF_BREV           0x00FF  /* Board Revision */
 200 #define  SSB_SPROM1_BINF_CCODE          0x0F00  /* Country Code */
 201 #define  SSB_SPROM1_BINF_CCODE_SHIFT    8
 202 #define  SSB_SPROM1_BINF_ANTBG          0x3000  /* Available B-PHY and G-PHY antennas */
 203 #define  SSB_SPROM1_BINF_ANTBG_SHIFT    12
 204 #define  SSB_SPROM1_BINF_ANTA           0xC000  /* Available A-PHY antennas */
 205 #define  SSB_SPROM1_BINF_ANTA_SHIFT     14
 206 #define SSB_SPROM1_PA0B0                0x005E
 207 #define SSB_SPROM1_PA0B1                0x0060
 208 #define SSB_SPROM1_PA0B2                0x0062
 209 #define SSB_SPROM1_GPIOA                0x0064  /* General Purpose IO pins 0 and 1 */
 210 #define  SSB_SPROM1_GPIOA_P0            0x00FF  /* Pin 0 */
 211 #define  SSB_SPROM1_GPIOA_P1            0xFF00  /* Pin 1 */
 212 #define  SSB_SPROM1_GPIOA_P1_SHIFT      8
 213 #define SSB_SPROM1_GPIOB                0x0066  /* General Purpuse IO pins 2 and 3 */
 214 #define  SSB_SPROM1_GPIOB_P2            0x00FF  /* Pin 2 */
 215 #define  SSB_SPROM1_GPIOB_P3            0xFF00  /* Pin 3 */
 216 #define  SSB_SPROM1_GPIOB_P3_SHIFT      8
 217 #define SSB_SPROM1_MAXPWR               0x0068  /* Power Amplifier Max Power */
 218 #define  SSB_SPROM1_MAXPWR_BG           0x00FF  /* B-PHY and G-PHY (in dBm Q5.2) */
 219 #define  SSB_SPROM1_MAXPWR_A            0xFF00  /* A-PHY (in dBm Q5.2) */
 220 #define  SSB_SPROM1_MAXPWR_A_SHIFT      8
 221 #define SSB_SPROM1_PA1B0                0x006A
 222 #define SSB_SPROM1_PA1B1                0x006C
 223 #define SSB_SPROM1_PA1B2                0x006E
 224 #define SSB_SPROM1_ITSSI                0x0070  /* Idle TSSI Target */
 225 #define  SSB_SPROM1_ITSSI_BG            0x00FF  /* B-PHY and G-PHY*/
 226 #define  SSB_SPROM1_ITSSI_A             0xFF00  /* A-PHY */
 227 #define  SSB_SPROM1_ITSSI_A_SHIFT       8
 228 #define SSB_SPROM1_BFLLO                0x0072  /* Boardflags (low 16 bits) */
 229 #define SSB_SPROM1_AGAIN                0x0074  /* Antenna Gain (in dBm Q5.2) */
 230 #define  SSB_SPROM1_AGAIN_BG            0x00FF  /* B-PHY and G-PHY */
 231 #define  SSB_SPROM1_AGAIN_BG_SHIFT      0
 232 #define  SSB_SPROM1_AGAIN_A             0xFF00  /* A-PHY */
 233 #define  SSB_SPROM1_AGAIN_A_SHIFT       8
 234 #define SSB_SPROM1_CCODE                0x0076
 235 
 236 /* SPROM Revision 2 (inherits from rev 1) */
 237 #define SSB_SPROM2_BFLHI                0x0038  /* Boardflags (high 16 bits) */
 238 #define SSB_SPROM2_MAXP_A               0x003A  /* A-PHY Max Power */
 239 #define  SSB_SPROM2_MAXP_A_HI           0x00FF  /* Max Power High */
 240 #define  SSB_SPROM2_MAXP_A_LO           0xFF00  /* Max Power Low */
 241 #define  SSB_SPROM2_MAXP_A_LO_SHIFT     8
 242 #define SSB_SPROM2_PA1LOB0              0x003C  /* A-PHY PowerAmplifier Low Settings */
 243 #define SSB_SPROM2_PA1LOB1              0x003E  /* A-PHY PowerAmplifier Low Settings */
 244 #define SSB_SPROM2_PA1LOB2              0x0040  /* A-PHY PowerAmplifier Low Settings */
 245 #define SSB_SPROM2_PA1HIB0              0x0042  /* A-PHY PowerAmplifier High Settings */
 246 #define SSB_SPROM2_PA1HIB1              0x0044  /* A-PHY PowerAmplifier High Settings */
 247 #define SSB_SPROM2_PA1HIB2              0x0046  /* A-PHY PowerAmplifier High Settings */
 248 #define SSB_SPROM2_OPO                  0x0078  /* OFDM Power Offset from CCK Level */
 249 #define  SSB_SPROM2_OPO_VALUE           0x00FF
 250 #define  SSB_SPROM2_OPO_UNUSED          0xFF00
 251 #define SSB_SPROM2_CCODE                0x007C  /* Two char Country Code */
 252 
 253 /* SPROM Revision 3 (inherits most data from rev 2) */
 254 #define SSB_SPROM3_OFDMAPO              0x002C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
 255 #define SSB_SPROM3_OFDMALPO             0x0030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
 256 #define SSB_SPROM3_OFDMAHPO             0x0034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
 257 #define SSB_SPROM3_GPIOLDC              0x0042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
 258 #define  SSB_SPROM3_GPIOLDC_OFF         0x0000FF00      /* Off Count */
 259 #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT   8
 260 #define  SSB_SPROM3_GPIOLDC_ON          0x00FF0000      /* On Count */
 261 #define  SSB_SPROM3_GPIOLDC_ON_SHIFT    16
 262 #define SSB_SPROM3_IL0MAC               0x004A  /* 6 bytes MAC address for 802.11b/g */
 263 #define SSB_SPROM3_CCKPO                0x0078  /* CCK Power Offset */
 264 #define  SSB_SPROM3_CCKPO_1M            0x000F  /* 1M Rate PO */
 265 #define  SSB_SPROM3_CCKPO_2M            0x00F0  /* 2M Rate PO */
 266 #define  SSB_SPROM3_CCKPO_2M_SHIFT      4
 267 #define  SSB_SPROM3_CCKPO_55M           0x0F00  /* 5.5M Rate PO */
 268 #define  SSB_SPROM3_CCKPO_55M_SHIFT     8
 269 #define  SSB_SPROM3_CCKPO_11M           0xF000  /* 11M Rate PO */
 270 #define  SSB_SPROM3_CCKPO_11M_SHIFT     12
 271 #define  SSB_SPROM3_OFDMGPO             0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
 272 
 273 /* SPROM Revision 4 */
 274 #define SSB_SPROM4_BOARDREV             0x0042  /* Board revision */
 275 #define SSB_SPROM4_BFLLO                0x0044  /* Boardflags (low 16 bits) */
 276 #define SSB_SPROM4_BFLHI                0x0046  /* Board Flags Hi */
 277 #define SSB_SPROM4_BFL2LO               0x0048  /* Board flags 2 (low 16 bits) */
 278 #define SSB_SPROM4_BFL2HI               0x004A  /* Board flags 2 Hi */
 279 #define SSB_SPROM4_IL0MAC               0x004C  /* 6 byte MAC address for a/b/g/n */
 280 #define SSB_SPROM4_CCODE                0x0052  /* Country Code (2 bytes) */
 281 #define SSB_SPROM4_GPIOA                0x0056  /* Gen. Purpose IO # 0 and 1 */
 282 #define  SSB_SPROM4_GPIOA_P0            0x00FF  /* Pin 0 */
 283 #define  SSB_SPROM4_GPIOA_P1            0xFF00  /* Pin 1 */
 284 #define  SSB_SPROM4_GPIOA_P1_SHIFT      8
 285 #define SSB_SPROM4_GPIOB                0x0058  /* Gen. Purpose IO # 2 and 3 */
 286 #define  SSB_SPROM4_GPIOB_P2            0x00FF  /* Pin 2 */
 287 #define  SSB_SPROM4_GPIOB_P3            0xFF00  /* Pin 3 */
 288 #define  SSB_SPROM4_GPIOB_P3_SHIFT      8
 289 #define SSB_SPROM4_ETHPHY               0x005A  /* Ethernet PHY settings ?? */
 290 #define  SSB_SPROM4_ETHPHY_ET0A         0x001F  /* MII Address for enet0 */
 291 #define  SSB_SPROM4_ETHPHY_ET1A         0x03E0  /* MII Address for enet1 */
 292 #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT   5
 293 #define  SSB_SPROM4_ETHPHY_ET0M         (1<<14) /* MDIO for enet0 */
 294 #define  SSB_SPROM4_ETHPHY_ET1M         (1<<15) /* MDIO for enet1 */
 295 #define SSB_SPROM4_ANTAVAIL             0x005C  /* Antenna available bitfields */
 296 #define  SSB_SPROM4_ANTAVAIL_BG         0x00FF  /* B-PHY and G-PHY bitfield */
 297 #define  SSB_SPROM4_ANTAVAIL_BG_SHIFT   0
 298 #define  SSB_SPROM4_ANTAVAIL_A          0xFF00  /* A-PHY bitfield */
 299 #define  SSB_SPROM4_ANTAVAIL_A_SHIFT    8
 300 #define SSB_SPROM4_AGAIN01              0x005E  /* Antenna Gain (in dBm Q5.2) */
 301 #define  SSB_SPROM4_AGAIN0              0x00FF  /* Antenna 0 */
 302 #define  SSB_SPROM4_AGAIN0_SHIFT        0
 303 #define  SSB_SPROM4_AGAIN1              0xFF00  /* Antenna 1 */
 304 #define  SSB_SPROM4_AGAIN1_SHIFT        8
 305 #define SSB_SPROM4_AGAIN23              0x0060
 306 #define  SSB_SPROM4_AGAIN2              0x00FF  /* Antenna 2 */
 307 #define  SSB_SPROM4_AGAIN2_SHIFT        0
 308 #define  SSB_SPROM4_AGAIN3              0xFF00  /* Antenna 3 */
 309 #define  SSB_SPROM4_AGAIN3_SHIFT        8
 310 #define SSB_SPROM4_TXPID2G01            0x0062  /* TX Power Index 2GHz */
 311 #define  SSB_SPROM4_TXPID2G0            0x00FF
 312 #define  SSB_SPROM4_TXPID2G0_SHIFT      0
 313 #define  SSB_SPROM4_TXPID2G1            0xFF00
 314 #define  SSB_SPROM4_TXPID2G1_SHIFT      8
 315 #define SSB_SPROM4_TXPID2G23            0x0064  /* TX Power Index 2GHz */
 316 #define  SSB_SPROM4_TXPID2G2            0x00FF
 317 #define  SSB_SPROM4_TXPID2G2_SHIFT      0
 318 #define  SSB_SPROM4_TXPID2G3            0xFF00
 319 #define  SSB_SPROM4_TXPID2G3_SHIFT      8
 320 #define SSB_SPROM4_TXPID5G01            0x0066  /* TX Power Index 5GHz middle subband */
 321 #define  SSB_SPROM4_TXPID5G0            0x00FF
 322 #define  SSB_SPROM4_TXPID5G0_SHIFT      0
 323 #define  SSB_SPROM4_TXPID5G1            0xFF00
 324 #define  SSB_SPROM4_TXPID5G1_SHIFT      8
 325 #define SSB_SPROM4_TXPID5G23            0x0068  /* TX Power Index 5GHz middle subband */
 326 #define  SSB_SPROM4_TXPID5G2            0x00FF
 327 #define  SSB_SPROM4_TXPID5G2_SHIFT      0
 328 #define  SSB_SPROM4_TXPID5G3            0xFF00
 329 #define  SSB_SPROM4_TXPID5G3_SHIFT      8
 330 #define SSB_SPROM4_TXPID5GL01           0x006A  /* TX Power Index 5GHz low subband */
 331 #define  SSB_SPROM4_TXPID5GL0           0x00FF
 332 #define  SSB_SPROM4_TXPID5GL0_SHIFT     0
 333 #define  SSB_SPROM4_TXPID5GL1           0xFF00
 334 #define  SSB_SPROM4_TXPID5GL1_SHIFT     8
 335 #define SSB_SPROM4_TXPID5GL23           0x006C  /* TX Power Index 5GHz low subband */
 336 #define  SSB_SPROM4_TXPID5GL2           0x00FF
 337 #define  SSB_SPROM4_TXPID5GL2_SHIFT     0
 338 #define  SSB_SPROM4_TXPID5GL3           0xFF00
 339 #define  SSB_SPROM4_TXPID5GL3_SHIFT     8
 340 #define SSB_SPROM4_TXPID5GH01           0x006E  /* TX Power Index 5GHz high subband */
 341 #define  SSB_SPROM4_TXPID5GH0           0x00FF
 342 #define  SSB_SPROM4_TXPID5GH0_SHIFT     0
 343 #define  SSB_SPROM4_TXPID5GH1           0xFF00
 344 #define  SSB_SPROM4_TXPID5GH1_SHIFT     8
 345 #define SSB_SPROM4_TXPID5GH23           0x0070  /* TX Power Index 5GHz high subband */
 346 #define  SSB_SPROM4_TXPID5GH2           0x00FF
 347 #define  SSB_SPROM4_TXPID5GH2_SHIFT     0
 348 #define  SSB_SPROM4_TXPID5GH3           0xFF00
 349 #define  SSB_SPROM4_TXPID5GH3_SHIFT     8
 350 
 351 /* There are 4 blocks with power info sharing the same layout */
 352 #define SSB_SPROM4_PWR_INFO_CORE0       0x0080
 353 #define SSB_SPROM4_PWR_INFO_CORE1       0x00AE
 354 #define SSB_SPROM4_PWR_INFO_CORE2       0x00DC
 355 #define SSB_SPROM4_PWR_INFO_CORE3       0x010A
 356 
 357 #define SSB_SPROM4_2G_MAXP_ITSSI        0x00    /* 2 GHz ITSSI and 2 GHz Max Power */
 358 #define  SSB_SPROM4_2G_MAXP             0x00FF
 359 #define  SSB_SPROM4_2G_ITSSI            0xFF00
 360 #define  SSB_SPROM4_2G_ITSSI_SHIFT      8
 361 #define SSB_SPROM4_2G_PA_0              0x02    /* 2 GHz power amp */
 362 #define SSB_SPROM4_2G_PA_1              0x04
 363 #define SSB_SPROM4_2G_PA_2              0x06
 364 #define SSB_SPROM4_2G_PA_3              0x08
 365 #define SSB_SPROM4_5G_MAXP_ITSSI        0x0A    /* 5 GHz ITSSI and 5.3 GHz Max Power */
 366 #define  SSB_SPROM4_5G_MAXP             0x00FF
 367 #define  SSB_SPROM4_5G_ITSSI            0xFF00
 368 #define  SSB_SPROM4_5G_ITSSI_SHIFT      8
 369 #define SSB_SPROM4_5GHL_MAXP            0x0C    /* 5.2 GHz and 5.8 GHz Max Power */
 370 #define  SSB_SPROM4_5GH_MAXP            0x00FF
 371 #define  SSB_SPROM4_5GL_MAXP            0xFF00
 372 #define  SSB_SPROM4_5GL_MAXP_SHIFT      8
 373 #define SSB_SPROM4_5G_PA_0              0x0E    /* 5.3 GHz power amp */
 374 #define SSB_SPROM4_5G_PA_1              0x10
 375 #define SSB_SPROM4_5G_PA_2              0x12
 376 #define SSB_SPROM4_5G_PA_3              0x14
 377 #define SSB_SPROM4_5GL_PA_0             0x16    /* 5.2 GHz power amp */
 378 #define SSB_SPROM4_5GL_PA_1             0x18
 379 #define SSB_SPROM4_5GL_PA_2             0x1A
 380 #define SSB_SPROM4_5GL_PA_3             0x1C
 381 #define SSB_SPROM4_5GH_PA_0             0x1E    /* 5.8 GHz power amp */
 382 #define SSB_SPROM4_5GH_PA_1             0x20
 383 #define SSB_SPROM4_5GH_PA_2             0x22
 384 #define SSB_SPROM4_5GH_PA_3             0x24
 385 
 386 /* TODO: Make it deprecated */
 387 #define SSB_SPROM4_MAXP_BG              0x0080  /* Max Power BG in path 1 */
 388 #define  SSB_SPROM4_MAXP_BG_MASK        0x00FF  /* Mask for Max Power BG */
 389 #define  SSB_SPROM4_ITSSI_BG            0xFF00  /* Mask for path 1 itssi_bg */
 390 #define  SSB_SPROM4_ITSSI_BG_SHIFT      8
 391 #define SSB_SPROM4_MAXP_A               0x008A  /* Max Power A in path 1 */
 392 #define  SSB_SPROM4_MAXP_A_MASK         0x00FF  /* Mask for Max Power A */
 393 #define  SSB_SPROM4_ITSSI_A             0xFF00  /* Mask for path 1 itssi_a */
 394 #define  SSB_SPROM4_ITSSI_A_SHIFT       8
 395 #define SSB_SPROM4_PA0B0                0x0082  /* The paXbY locations are */
 396 #define SSB_SPROM4_PA0B1                0x0084  /*   only guesses */
 397 #define SSB_SPROM4_PA0B2                0x0086
 398 #define SSB_SPROM4_PA1B0                0x008E
 399 #define SSB_SPROM4_PA1B1                0x0090
 400 #define SSB_SPROM4_PA1B2                0x0092
 401 
 402 /* SPROM Revision 5 (inherits most data from rev 4) */
 403 #define SSB_SPROM5_CCODE                0x0044  /* Country Code (2 bytes) */
 404 #define SSB_SPROM5_BFLLO                0x004A  /* Boardflags (low 16 bits) */
 405 #define SSB_SPROM5_BFLHI                0x004C  /* Board Flags Hi */
 406 #define SSB_SPROM5_BFL2LO               0x004E  /* Board flags 2 (low 16 bits) */
 407 #define SSB_SPROM5_BFL2HI               0x0050  /* Board flags 2 Hi */
 408 #define SSB_SPROM5_IL0MAC               0x0052  /* 6 byte MAC address for a/b/g/n */
 409 #define SSB_SPROM5_GPIOA                0x0076  /* Gen. Purpose IO # 0 and 1 */
 410 #define  SSB_SPROM5_GPIOA_P0            0x00FF  /* Pin 0 */
 411 #define  SSB_SPROM5_GPIOA_P1            0xFF00  /* Pin 1 */
 412 #define  SSB_SPROM5_GPIOA_P1_SHIFT      8
 413 #define SSB_SPROM5_GPIOB                0x0078  /* Gen. Purpose IO # 2 and 3 */
 414 #define  SSB_SPROM5_GPIOB_P2            0x00FF  /* Pin 2 */
 415 #define  SSB_SPROM5_GPIOB_P3            0xFF00  /* Pin 3 */
 416 #define  SSB_SPROM5_GPIOB_P3_SHIFT      8
 417 
 418 /* SPROM Revision 8 */
 419 #define SSB_SPROM8_BOARDREV             0x0082  /* Board revision */
 420 #define SSB_SPROM8_BFLLO                0x0084  /* Board flags (bits 0-15) */
 421 #define SSB_SPROM8_BFLHI                0x0086  /* Board flags (bits 16-31) */
 422 #define SSB_SPROM8_BFL2LO               0x0088  /* Board flags (bits 32-47) */
 423 #define SSB_SPROM8_BFL2HI               0x008A  /* Board flags (bits 48-63) */
 424 #define SSB_SPROM8_IL0MAC               0x008C  /* 6 byte MAC address */
 425 #define SSB_SPROM8_CCODE                0x0092  /* 2 byte country code */
 426 #define SSB_SPROM8_GPIOA                0x0096  /*Gen. Purpose IO # 0 and 1 */
 427 #define  SSB_SPROM8_GPIOA_P0            0x00FF  /* Pin 0 */
 428 #define  SSB_SPROM8_GPIOA_P1            0xFF00  /* Pin 1 */
 429 #define  SSB_SPROM8_GPIOA_P1_SHIFT      8
 430 #define SSB_SPROM8_GPIOB                0x0098  /* Gen. Purpose IO # 2 and 3 */
 431 #define  SSB_SPROM8_GPIOB_P2            0x00FF  /* Pin 2 */
 432 #define  SSB_SPROM8_GPIOB_P3            0xFF00  /* Pin 3 */
 433 #define  SSB_SPROM8_GPIOB_P3_SHIFT      8
 434 #define SSB_SPROM8_LEDDC                0x009A
 435 #define  SSB_SPROM8_LEDDC_ON            0xFF00  /* oncount */
 436 #define  SSB_SPROM8_LEDDC_ON_SHIFT      8
 437 #define  SSB_SPROM8_LEDDC_OFF           0x00FF  /* offcount */
 438 #define  SSB_SPROM8_LEDDC_OFF_SHIFT     0
 439 #define SSB_SPROM8_ANTAVAIL             0x009C  /* Antenna available bitfields*/
 440 #define  SSB_SPROM8_ANTAVAIL_A          0xFF00  /* A-PHY bitfield */
 441 #define  SSB_SPROM8_ANTAVAIL_A_SHIFT    8
 442 #define  SSB_SPROM8_ANTAVAIL_BG         0x00FF  /* B-PHY and G-PHY bitfield */
 443 #define  SSB_SPROM8_ANTAVAIL_BG_SHIFT   0
 444 #define SSB_SPROM8_AGAIN01              0x009E  /* Antenna Gain (in dBm Q5.2) */
 445 #define  SSB_SPROM8_AGAIN0              0x00FF  /* Antenna 0 */
 446 #define  SSB_SPROM8_AGAIN0_SHIFT        0
 447 #define  SSB_SPROM8_AGAIN1              0xFF00  /* Antenna 1 */
 448 #define  SSB_SPROM8_AGAIN1_SHIFT        8
 449 #define SSB_SPROM8_AGAIN23              0x00A0
 450 #define  SSB_SPROM8_AGAIN2              0x00FF  /* Antenna 2 */
 451 #define  SSB_SPROM8_AGAIN2_SHIFT        0
 452 #define  SSB_SPROM8_AGAIN3              0xFF00  /* Antenna 3 */
 453 #define  SSB_SPROM8_AGAIN3_SHIFT        8
 454 #define SSB_SPROM8_TXRXC                0x00A2
 455 #define  SSB_SPROM8_TXRXC_TXCHAIN       0x000f
 456 #define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
 457 #define  SSB_SPROM8_TXRXC_RXCHAIN       0x00f0
 458 #define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
 459 #define  SSB_SPROM8_TXRXC_SWITCH        0xff00
 460 #define  SSB_SPROM8_TXRXC_SWITCH_SHIFT  8
 461 #define SSB_SPROM8_RSSIPARM2G           0x00A4  /* RSSI params for 2GHz */
 462 #define  SSB_SPROM8_RSSISMF2G           0x000F
 463 #define  SSB_SPROM8_RSSISMC2G           0x00F0
 464 #define  SSB_SPROM8_RSSISMC2G_SHIFT     4
 465 #define  SSB_SPROM8_RSSISAV2G           0x0700
 466 #define  SSB_SPROM8_RSSISAV2G_SHIFT     8
 467 #define  SSB_SPROM8_BXA2G               0x1800
 468 #define  SSB_SPROM8_BXA2G_SHIFT         11
 469 #define SSB_SPROM8_RSSIPARM5G           0x00A6  /* RSSI params for 5GHz */
 470 #define  SSB_SPROM8_RSSISMF5G           0x000F
 471 #define  SSB_SPROM8_RSSISMC5G           0x00F0
 472 #define  SSB_SPROM8_RSSISMC5G_SHIFT     4
 473 #define  SSB_SPROM8_RSSISAV5G           0x0700
 474 #define  SSB_SPROM8_RSSISAV5G_SHIFT     8
 475 #define  SSB_SPROM8_BXA5G               0x1800
 476 #define  SSB_SPROM8_BXA5G_SHIFT         11
 477 #define SSB_SPROM8_TRI25G               0x00A8  /* TX isolation 2.4&5.3GHz */
 478 #define  SSB_SPROM8_TRI2G               0x00FF  /* TX isolation 2.4GHz */
 479 #define  SSB_SPROM8_TRI5G               0xFF00  /* TX isolation 5.3GHz */
 480 #define  SSB_SPROM8_TRI5G_SHIFT         8
 481 #define SSB_SPROM8_TRI5GHL              0x00AA  /* TX isolation 5.2/5.8GHz */
 482 #define  SSB_SPROM8_TRI5GL              0x00FF  /* TX isolation 5.2GHz */
 483 #define  SSB_SPROM8_TRI5GH              0xFF00  /* TX isolation 5.8GHz */
 484 #define  SSB_SPROM8_TRI5GH_SHIFT        8
 485 #define SSB_SPROM8_RXPO                 0x00AC  /* RX power offsets */
 486 #define  SSB_SPROM8_RXPO2G              0x00FF  /* 2GHz RX power offset */
 487 #define  SSB_SPROM8_RXPO2G_SHIFT        0
 488 #define  SSB_SPROM8_RXPO5G              0xFF00  /* 5GHz RX power offset */
 489 #define  SSB_SPROM8_RXPO5G_SHIFT        8
 490 #define SSB_SPROM8_FEM2G                0x00AE
 491 #define SSB_SPROM8_FEM5G                0x00B0
 492 #define  SSB_SROM8_FEM_TSSIPOS          0x0001
 493 #define  SSB_SROM8_FEM_TSSIPOS_SHIFT    0
 494 #define  SSB_SROM8_FEM_EXTPA_GAIN       0x0006
 495 #define  SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
 496 #define  SSB_SROM8_FEM_PDET_RANGE       0x00F8
 497 #define  SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
 498 #define  SSB_SROM8_FEM_TR_ISO           0x0700
 499 #define  SSB_SROM8_FEM_TR_ISO_SHIFT     8
 500 #define  SSB_SROM8_FEM_ANTSWLUT         0xF800
 501 #define  SSB_SROM8_FEM_ANTSWLUT_SHIFT   11
 502 #define SSB_SPROM8_THERMAL              0x00B2
 503 #define  SSB_SPROM8_THERMAL_OFFSET      0x00ff
 504 #define  SSB_SPROM8_THERMAL_OFFSET_SHIFT        0
 505 #define  SSB_SPROM8_THERMAL_TRESH       0xff00
 506 #define  SSB_SPROM8_THERMAL_TRESH_SHIFT 8
 507 /* Temp sense related entries */
 508 #define SSB_SPROM8_RAWTS                0x00B4
 509 #define  SSB_SPROM8_RAWTS_RAWTEMP       0x01ff
 510 #define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
 511 #define  SSB_SPROM8_RAWTS_MEASPOWER     0xfe00
 512 #define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT       9
 513 #define SSB_SPROM8_OPT_CORRX            0x00B6
 514 #define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE        0x00ff
 515 #define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT  0
 516 #define  SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
 517 #define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT   10
 518 #define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION       0x0300
 519 #define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
 520 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
 521 #define SSB_SPROM8_HWIQ_IQSWP           0x00B8
 522 #define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR        0x000f
 523 #define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT  0
 524 #define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP        0x0010
 525 #define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT  4
 526 #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
 527 #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT   5
 528 #define SSB_SPROM8_TEMPDELTA            0x00BC
 529 #define  SSB_SPROM8_TEMPDELTA_PHYCAL    0x00ff
 530 #define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT      0
 531 #define  SSB_SPROM8_TEMPDELTA_PERIOD    0x0f00
 532 #define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT      8
 533 #define  SSB_SPROM8_TEMPDELTA_HYSTERESIS        0xf000
 534 #define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT  12
 535 
 536 /* There are 4 blocks with power info sharing the same layout */
 537 #define SSB_SROM8_PWR_INFO_CORE0        0x00C0
 538 #define SSB_SROM8_PWR_INFO_CORE1        0x00E0
 539 #define SSB_SROM8_PWR_INFO_CORE2        0x0100
 540 #define SSB_SROM8_PWR_INFO_CORE3        0x0120
 541 
 542 #define SSB_SROM8_2G_MAXP_ITSSI         0x00
 543 #define  SSB_SPROM8_2G_MAXP             0x00FF
 544 #define  SSB_SPROM8_2G_ITSSI            0xFF00
 545 #define  SSB_SPROM8_2G_ITSSI_SHIFT      8
 546 #define SSB_SROM8_2G_PA_0               0x02    /* 2GHz power amp settings */
 547 #define SSB_SROM8_2G_PA_1               0x04
 548 #define SSB_SROM8_2G_PA_2               0x06
 549 #define SSB_SROM8_5G_MAXP_ITSSI         0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
 550 #define  SSB_SPROM8_5G_MAXP             0x00FF
 551 #define  SSB_SPROM8_5G_ITSSI            0xFF00
 552 #define  SSB_SPROM8_5G_ITSSI_SHIFT      8
 553 #define SSB_SPROM8_5GHL_MAXP            0x0A    /* 5.2GHz and 5.8GHz Max Power */
 554 #define  SSB_SPROM8_5GH_MAXP            0x00FF
 555 #define  SSB_SPROM8_5GL_MAXP            0xFF00
 556 #define  SSB_SPROM8_5GL_MAXP_SHIFT      8
 557 #define SSB_SROM8_5G_PA_0               0x0C    /* 5.3GHz power amp settings */
 558 #define SSB_SROM8_5G_PA_1               0x0E
 559 #define SSB_SROM8_5G_PA_2               0x10
 560 #define SSB_SROM8_5GL_PA_0              0x12    /* 5.2GHz power amp settings */
 561 #define SSB_SROM8_5GL_PA_1              0x14
 562 #define SSB_SROM8_5GL_PA_2              0x16
 563 #define SSB_SROM8_5GH_PA_0              0x18    /* 5.8GHz power amp settings */
 564 #define SSB_SROM8_5GH_PA_1              0x1A
 565 #define SSB_SROM8_5GH_PA_2              0x1C
 566 
 567 /* TODO: Make it deprecated */
 568 #define SSB_SPROM8_MAXP_BG              0x00C0  /* Max Power 2GHz in path 1 */
 569 #define  SSB_SPROM8_MAXP_BG_MASK        0x00FF  /* Mask for Max Power 2GHz */
 570 #define  SSB_SPROM8_ITSSI_BG            0xFF00  /* Mask for path 1 itssi_bg */
 571 #define  SSB_SPROM8_ITSSI_BG_SHIFT      8
 572 #define SSB_SPROM8_PA0B0                0x00C2  /* 2GHz power amp settings */
 573 #define SSB_SPROM8_PA0B1                0x00C4
 574 #define SSB_SPROM8_PA0B2                0x00C6
 575 #define SSB_SPROM8_MAXP_A               0x00C8  /* Max Power 5.3GHz */
 576 #define  SSB_SPROM8_MAXP_A_MASK         0x00FF  /* Mask for Max Power 5.3GHz */
 577 #define  SSB_SPROM8_ITSSI_A             0xFF00  /* Mask for path 1 itssi_a */
 578 #define  SSB_SPROM8_ITSSI_A_SHIFT       8
 579 #define SSB_SPROM8_MAXP_AHL             0x00CA  /* Max Power 5.2/5.8GHz */
 580 #define  SSB_SPROM8_MAXP_AH_MASK        0x00FF  /* Mask for Max Power 5.8GHz */
 581 #define  SSB_SPROM8_MAXP_AL_MASK        0xFF00  /* Mask for Max Power 5.2GHz */
 582 #define  SSB_SPROM8_MAXP_AL_SHIFT       8
 583 #define SSB_SPROM8_PA1B0                0x00CC  /* 5.3GHz power amp settings */
 584 #define SSB_SPROM8_PA1B1                0x00CE
 585 #define SSB_SPROM8_PA1B2                0x00D0
 586 #define SSB_SPROM8_PA1LOB0              0x00D2  /* 5.2GHz power amp settings */
 587 #define SSB_SPROM8_PA1LOB1              0x00D4
 588 #define SSB_SPROM8_PA1LOB2              0x00D6
 589 #define SSB_SPROM8_PA1HIB0              0x00D8  /* 5.8GHz power amp settings */
 590 #define SSB_SPROM8_PA1HIB1              0x00DA
 591 #define SSB_SPROM8_PA1HIB2              0x00DC
 592 
 593 #define SSB_SPROM8_CCK2GPO              0x0140  /* CCK power offset */
 594 #define SSB_SPROM8_OFDM2GPO             0x0142  /* 2.4GHz OFDM power offset */
 595 #define SSB_SPROM8_OFDM5GPO             0x0146  /* 5.3GHz OFDM power offset */
 596 #define SSB_SPROM8_OFDM5GLPO            0x014A  /* 5.2GHz OFDM power offset */
 597 #define SSB_SPROM8_OFDM5GHPO            0x014E  /* 5.8GHz OFDM power offset */
 598 
 599 #define SSB_SPROM8_2G_MCSPO             0x0152
 600 #define SSB_SPROM8_5G_MCSPO             0x0162
 601 #define SSB_SPROM8_5GL_MCSPO            0x0172
 602 #define SSB_SPROM8_5GH_MCSPO            0x0182
 603 
 604 #define SSB_SPROM8_CDDPO                0x0192
 605 #define SSB_SPROM8_STBCPO               0x0194
 606 #define SSB_SPROM8_BW40PO               0x0196
 607 #define SSB_SPROM8_BWDUPPO              0x0198
 608 
 609 /* Values for boardflags_lo read from SPROM */
 610 #define SSB_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
 611 #define SSB_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */
 612 #define SSB_BFL_AIRLINEMODE             0x0004  /* implements GPIO 13 radio disable indication */
 613 #define SSB_BFL_RSSI                    0x0008  /* software calculates nrssi slope. */
 614 #define SSB_BFL_ENETSPI                 0x0010  /* has ephy roboswitch spi */
 615 #define SSB_BFL_XTAL_NOSLOW             0x0020  /* no slow clock available */
 616 #define SSB_BFL_CCKHIPWR                0x0040  /* can do high power CCK transmission */
 617 #define SSB_BFL_ENETADM                 0x0080  /* has ADMtek switch */
 618 #define SSB_BFL_ENETVLAN                0x0100  /* can do vlan */
 619 #define SSB_BFL_AFTERBURNER             0x0200  /* supports Afterburner mode */
 620 #define SSB_BFL_NOPCI                   0x0400  /* board leaves PCI floating */
 621 #define SSB_BFL_FEM                     0x0800  /* supports the Front End Module */
 622 #define SSB_BFL_EXTLNA                  0x1000  /* has an external LNA */
 623 #define SSB_BFL_HGPA                    0x2000  /* had high gain PA */
 624 #define SSB_BFL_BTCMOD                  0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 625 #define SSB_BFL_ALTIQ                   0x8000  /* alternate I/Q settings */
 626 
 627 /* Values for boardflags_hi read from SPROM */
 628 #define SSB_BFH_NOPA                    0x0001  /* has no PA */
 629 #define SSB_BFH_RSSIINV                 0x0002  /* RSSI uses positive slope (not TSSI) */
 630 #define SSB_BFH_PAREF                   0x0004  /* uses the PARef LDO */
 631 #define SSB_BFH_3TSWITCH                0x0008  /* uses a triple throw switch shared with bluetooth */
 632 #define SSB_BFH_PHASESHIFT              0x0010  /* can support phase shifter */
 633 #define SSB_BFH_BUCKBOOST               0x0020  /* has buck/booster */
 634 #define SSB_BFH_FEM_BT                  0x0040  /* has FEM and switch to share antenna with bluetooth */
 635 
 636 /* Values for boardflags2_lo read from SPROM */
 637 #define SSB_BFL2_RXBB_INT_REG_DIS       0x0001  /* external RX BB regulator present */
 638 #define SSB_BFL2_APLL_WAR               0x0002  /* alternative A-band PLL settings implemented */
 639 #define SSB_BFL2_TXPWRCTRL_EN           0x0004  /* permits enabling TX Power Control */
 640 #define SSB_BFL2_2X4_DIV                0x0008  /* 2x4 diversity switch */
 641 #define SSB_BFL2_5G_PWRGAIN             0x0010  /* supports 5G band power gain */
 642 #define SSB_BFL2_PCIEWAR_OVR            0x0020  /* overrides ASPM and Clkreq settings */
 643 #define SSB_BFL2_CAESERS_BRD            0x0040  /* is Caesers board (unused) */
 644 #define SSB_BFL2_BTC3WIRE               0x0080  /* used 3-wire bluetooth coexist */
 645 #define SSB_BFL2_SKWRKFEM_BRD           0x0100  /* 4321mcm93 uses Skyworks FEM */
 646 #define SSB_BFL2_SPUR_WAR               0x0200  /* has a workaround for clock-harmonic spurs */
 647 #define SSB_BFL2_GPLL_WAR               0x0400  /* altenative G-band PLL settings implemented */
 648 
 649 /* Values for SSB_SPROM1_BINF_CCODE */
 650 enum {
 651         SSB_SPROM1CCODE_WORLD = 0,
 652         SSB_SPROM1CCODE_THAILAND,
 653         SSB_SPROM1CCODE_ISRAEL,
 654         SSB_SPROM1CCODE_JORDAN,
 655         SSB_SPROM1CCODE_CHINA,
 656         SSB_SPROM1CCODE_JAPAN,
 657         SSB_SPROM1CCODE_USA_CANADA_ANZ,
 658         SSB_SPROM1CCODE_EUROPE,
 659         SSB_SPROM1CCODE_USA_LOW,
 660         SSB_SPROM1CCODE_JAPAN_HIGH,
 661         SSB_SPROM1CCODE_ALL,
 662         SSB_SPROM1CCODE_NONE,
 663 };
 664 
 665 /* Address-Match values and masks (SSB_ADMATCHxxx) */
 666 #define SSB_ADM_TYPE                    0x00000003      /* Address type */
 667 #define  SSB_ADM_TYPE0                  0
 668 #define  SSB_ADM_TYPE1                  1
 669 #define  SSB_ADM_TYPE2                  2
 670 #define SSB_ADM_AD64                    0x00000004
 671 #define SSB_ADM_SZ0                     0x000000F8      /* Type0 size */
 672 #define SSB_ADM_SZ0_SHIFT               3
 673 #define SSB_ADM_SZ1                     0x000001F8      /* Type1 size */
 674 #define SSB_ADM_SZ1_SHIFT               3
 675 #define SSB_ADM_SZ2                     0x000001F8      /* Type2 size */
 676 #define SSB_ADM_SZ2_SHIFT               3
 677 #define SSB_ADM_EN                      0x00000400      /* Enable */
 678 #define SSB_ADM_NEG                     0x00000800      /* Negative decode */
 679 #define SSB_ADM_BASE0                   0xFFFFFF00      /* Type0 base address */
 680 #define SSB_ADM_BASE0_SHIFT             8
 681 #define SSB_ADM_BASE1                   0xFFFFF000      /* Type1 base address for the core */
 682 #define SSB_ADM_BASE1_SHIFT             12
 683 #define SSB_ADM_BASE2                   0xFFFF0000      /* Type2 base address for the core */
 684 #define SSB_ADM_BASE2_SHIFT             16
 685 
 686 
 687 #endif /* LINUX_SSB_REGS_H_ */