1
2
3
4
5
6
7
8
9 #ifndef LINUX_RIO_REGS_H
10 #define LINUX_RIO_REGS_H
11
12
13
14
15
16
17 #define RIO_MAINT_SPACE_SZ 0x1000000
18
19 #define RIO_DEV_ID_CAR 0x00
20 #define RIO_DEV_INFO_CAR 0x04
21 #define RIO_ASM_ID_CAR 0x08
22 #define RIO_ASM_ID_MASK 0xffff0000
23 #define RIO_ASM_VEN_ID_MASK 0x0000ffff
24
25 #define RIO_ASM_INFO_CAR 0x0c
26 #define RIO_ASM_REV_MASK 0xffff0000
27 #define RIO_EXT_FTR_PTR_MASK 0x0000ffff
28
29 #define RIO_PEF_CAR 0x10
30 #define RIO_PEF_BRIDGE 0x80000000
31 #define RIO_PEF_MEMORY 0x40000000
32 #define RIO_PEF_PROCESSOR 0x20000000
33 #define RIO_PEF_SWITCH 0x10000000
34 #define RIO_PEF_MULTIPORT 0x08000000
35 #define RIO_PEF_INB_MBOX 0x00f00000
36 #define RIO_PEF_INB_MBOX0 0x00800000
37 #define RIO_PEF_INB_MBOX1 0x00400000
38 #define RIO_PEF_INB_MBOX2 0x00200000
39 #define RIO_PEF_INB_MBOX3 0x00100000
40 #define RIO_PEF_INB_DOORBELL 0x00080000
41 #define RIO_PEF_DEV32 0x00001000
42 #define RIO_PEF_EXT_RT 0x00000200
43 #define RIO_PEF_STD_RT 0x00000100
44 #define RIO_PEF_CTLS 0x00000010
45 #define RIO_PEF_DEV16 0x00000010
46 #define RIO_PEF_EXT_FEATURES 0x00000008
47 #define RIO_PEF_ADDR_66 0x00000004
48 #define RIO_PEF_ADDR_50 0x00000002
49 #define RIO_PEF_ADDR_34 0x00000001
50
51 #define RIO_SWP_INFO_CAR 0x14
52 #define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00
53 #define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff
54 #define RIO_GET_TOTAL_PORTS(x) ((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8)
55 #define RIO_GET_PORT_NUM(x) (x & RIO_SWP_INFO_PORT_NUM_MASK)
56
57 #define RIO_SRC_OPS_CAR 0x18
58 #define RIO_SRC_OPS_READ 0x00008000
59 #define RIO_SRC_OPS_WRITE 0x00004000
60 #define RIO_SRC_OPS_STREAM_WRITE 0x00002000
61 #define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000
62 #define RIO_SRC_OPS_DATA_MSG 0x00000800
63 #define RIO_SRC_OPS_DOORBELL 0x00000400
64 #define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100
65 #define RIO_SRC_OPS_ATOMIC_INC 0x00000080
66 #define RIO_SRC_OPS_ATOMIC_DEC 0x00000040
67 #define RIO_SRC_OPS_ATOMIC_SET 0x00000020
68 #define RIO_SRC_OPS_ATOMIC_CLR 0x00000010
69 #define RIO_SRC_OPS_PORT_WRITE 0x00000004
70
71 #define RIO_DST_OPS_CAR 0x1c
72 #define RIO_DST_OPS_READ 0x00008000
73 #define RIO_DST_OPS_WRITE 0x00004000
74 #define RIO_DST_OPS_STREAM_WRITE 0x00002000
75 #define RIO_DST_OPS_WRITE_RESPONSE 0x00001000
76 #define RIO_DST_OPS_DATA_MSG 0x00000800
77 #define RIO_DST_OPS_DOORBELL 0x00000400
78 #define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100
79 #define RIO_DST_OPS_ATOMIC_INC 0x00000080
80 #define RIO_DST_OPS_ATOMIC_DEC 0x00000040
81 #define RIO_DST_OPS_ATOMIC_SET 0x00000020
82 #define RIO_DST_OPS_ATOMIC_CLR 0x00000010
83 #define RIO_DST_OPS_PORT_WRITE 0x00000004
84
85 #define RIO_OPS_READ 0x00008000
86 #define RIO_OPS_WRITE 0x00004000
87 #define RIO_OPS_STREAM_WRITE 0x00002000
88 #define RIO_OPS_WRITE_RESPONSE 0x00001000
89 #define RIO_OPS_DATA_MSG 0x00000800
90 #define RIO_OPS_DOORBELL 0x00000400
91 #define RIO_OPS_ATOMIC_TST_SWP 0x00000100
92 #define RIO_OPS_ATOMIC_INC 0x00000080
93 #define RIO_OPS_ATOMIC_DEC 0x00000040
94 #define RIO_OPS_ATOMIC_SET 0x00000020
95 #define RIO_OPS_ATOMIC_CLR 0x00000010
96 #define RIO_OPS_PORT_WRITE 0x00000004
97
98
99
100 #define RIO_SWITCH_RT_LIMIT 0x34
101 #define RIO_RT_MAX_DESTID 0x0000ffff
102
103 #define RIO_MBOX_CSR 0x40
104 #define RIO_MBOX0_AVAIL 0x80000000
105 #define RIO_MBOX0_FULL 0x40000000
106 #define RIO_MBOX0_EMPTY 0x20000000
107 #define RIO_MBOX0_BUSY 0x10000000
108 #define RIO_MBOX0_FAIL 0x08000000
109 #define RIO_MBOX0_ERROR 0x04000000
110 #define RIO_MBOX1_AVAIL 0x00800000
111 #define RIO_MBOX1_FULL 0x00200000
112 #define RIO_MBOX1_EMPTY 0x00200000
113 #define RIO_MBOX1_BUSY 0x00100000
114 #define RIO_MBOX1_FAIL 0x00080000
115 #define RIO_MBOX1_ERROR 0x00040000
116 #define RIO_MBOX2_AVAIL 0x00008000
117 #define RIO_MBOX2_FULL 0x00004000
118 #define RIO_MBOX2_EMPTY 0x00002000
119 #define RIO_MBOX2_BUSY 0x00001000
120 #define RIO_MBOX2_FAIL 0x00000800
121 #define RIO_MBOX2_ERROR 0x00000400
122 #define RIO_MBOX3_AVAIL 0x00000080
123 #define RIO_MBOX3_FULL 0x00000040
124 #define RIO_MBOX3_EMPTY 0x00000020
125 #define RIO_MBOX3_BUSY 0x00000010
126 #define RIO_MBOX3_FAIL 0x00000008
127 #define RIO_MBOX3_ERROR 0x00000004
128
129 #define RIO_WRITE_PORT_CSR 0x44
130 #define RIO_DOORBELL_CSR 0x44
131 #define RIO_DOORBELL_AVAIL 0x80000000
132 #define RIO_DOORBELL_FULL 0x40000000
133 #define RIO_DOORBELL_EMPTY 0x20000000
134 #define RIO_DOORBELL_BUSY 0x10000000
135 #define RIO_DOORBELL_FAILED 0x08000000
136 #define RIO_DOORBELL_ERROR 0x04000000
137 #define RIO_WRITE_PORT_AVAILABLE 0x00000080
138 #define RIO_WRITE_PORT_FULL 0x00000040
139 #define RIO_WRITE_PORT_EMPTY 0x00000020
140 #define RIO_WRITE_PORT_BUSY 0x00000010
141 #define RIO_WRITE_PORT_FAILED 0x00000008
142 #define RIO_WRITE_PORT_ERROR 0x00000004
143
144
145
146 #define RIO_PELL_CTRL_CSR 0x4c
147 #define RIO_PELL_ADDR_66 0x00000004
148 #define RIO_PELL_ADDR_50 0x00000002
149 #define RIO_PELL_ADDR_34 0x00000001
150
151
152
153 #define RIO_LCSH_BA 0x58
154 #define RIO_LCSL_BA 0x5c
155
156 #define RIO_DID_CSR 0x60
157
158
159
160 #define RIO_HOST_DID_LOCK_CSR 0x68
161 #define RIO_COMPONENT_TAG_CSR 0x6c
162
163 #define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70
164 #define RIO_STD_RTE_CONF_EXTCFGEN 0x80000000
165 #define RIO_STD_RTE_CONF_PORT_SEL_CSR 0x74
166 #define RIO_STD_RTE_DEFAULT_PORT 0x78
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189 #define RIO_EFB_PTR_MASK 0xffff0000
190 #define RIO_EFB_ID_MASK 0x0000ffff
191 #define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16)
192 #define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK)
193
194
195 #define RIO_EFB_SER_EP_M1_ID 0x0001
196 #define RIO_EFB_SER_EP_SW_M1_ID 0x0002
197 #define RIO_EFB_SER_EPF_M1_ID 0x0003
198 #define RIO_EFB_SER_EP_ID 0x0004
199 #define RIO_EFB_SER_EP_REC_ID 0x0005
200 #define RIO_EFB_SER_EP_FREE_ID 0x0006
201 #define RIO_EFB_ERR_MGMNT 0x0007
202 #define RIO_EFB_SER_EPF_SW_M1_ID 0x0009
203 #define RIO_EFB_SW_ROUTING_TBL 0x000E
204 #define RIO_EFB_SER_EP_M2_ID 0x0011
205 #define RIO_EFB_SER_EP_SW_M2_ID 0x0012
206 #define RIO_EFB_SER_EPF_M2_ID 0x0013
207 #define RIO_EFB_ERR_MGMNT_HS 0x0017
208 #define RIO_EFB_SER_EPF_SW_M2_ID 0x0019
209
210
211
212
213
214
215 #define RIO_PORT_MNT_HEADER 0x0000
216 #define RIO_PORT_REQ_CTL_CSR 0x0020
217 #define RIO_PORT_RSP_CTL_CSR 0x0024
218 #define RIO_PORT_LINKTO_CTL_CSR 0x0020
219 #define RIO_PORT_RSPTO_CTL_CSR 0x0024
220 #define RIO_PORT_GEN_CTL_CSR 0x003c
221 #define RIO_PORT_GEN_HOST 0x80000000
222 #define RIO_PORT_GEN_MASTER 0x40000000
223 #define RIO_PORT_GEN_DISCOVERED 0x20000000
224 #define RIO_PORT_N_MNT_REQ_CSR(n, m) (0x40 + (n) * (0x20 * (m)))
225 #define RIO_MNT_REQ_CMD_RD 0x03
226 #define RIO_MNT_REQ_CMD_IS 0x04
227 #define RIO_PORT_N_MNT_RSP_CSR(n, m) (0x44 + (n) * (0x20 * (m)))
228 #define RIO_PORT_N_MNT_RSP_RVAL 0x80000000
229 #define RIO_PORT_N_MNT_RSP_ASTAT 0x000007e0
230 #define RIO_PORT_N_MNT_RSP_LSTAT 0x0000001f
231 #define RIO_PORT_N_ACK_STS_CSR(n) (0x48 + (n) * 0x20)
232 #define RIO_PORT_N_ACK_CLEAR 0x80000000
233 #define RIO_PORT_N_ACK_INBOUND 0x3f000000
234 #define RIO_PORT_N_ACK_OUTSTAND 0x00003f00
235 #define RIO_PORT_N_ACK_OUTBOUND 0x0000003f
236 #define RIO_PORT_N_CTL2_CSR(n, m) (0x54 + (n) * (0x20 * (m)))
237 #define RIO_PORT_N_CTL2_SEL_BAUD 0xf0000000
238 #define RIO_PORT_N_ERR_STS_CSR(n, m) (0x58 + (n) * (0x20 * (m)))
239 #define RIO_PORT_N_ERR_STS_OUT_ES 0x00010000
240 #define RIO_PORT_N_ERR_STS_INP_ES 0x00000100
241 #define RIO_PORT_N_ERR_STS_PW_PEND 0x00000010
242 #define RIO_PORT_N_ERR_STS_PORT_UA 0x00000008
243 #define RIO_PORT_N_ERR_STS_PORT_ERR 0x00000004
244 #define RIO_PORT_N_ERR_STS_PORT_OK 0x00000002
245 #define RIO_PORT_N_ERR_STS_PORT_UNINIT 0x00000001
246 #define RIO_PORT_N_CTL_CSR(n, m) (0x5c + (n) * (0x20 * (m)))
247 #define RIO_PORT_N_CTL_PWIDTH 0xc0000000
248 #define RIO_PORT_N_CTL_PWIDTH_1 0x00000000
249 #define RIO_PORT_N_CTL_PWIDTH_4 0x40000000
250 #define RIO_PORT_N_CTL_IPW 0x38000000
251 #define RIO_PORT_N_CTL_P_TYP_SER 0x00000001
252 #define RIO_PORT_N_CTL_LOCKOUT 0x00000002
253 #define RIO_PORT_N_CTL_EN_RX 0x00200000
254 #define RIO_PORT_N_CTL_EN_TX 0x00400000
255 #define RIO_PORT_N_OB_ACK_CSR(n) (0x60 + (n) * 0x40)
256 #define RIO_PORT_N_OB_ACK_CLEAR 0x80000000
257 #define RIO_PORT_N_OB_ACK_OUTSTD 0x00fff000
258 #define RIO_PORT_N_OB_ACK_OUTBND 0x00000fff
259 #define RIO_PORT_N_IB_ACK_CSR(n) (0x64 + (n) * 0x40)
260 #define RIO_PORT_N_IB_ACK_INBND 0x00000fff
261
262
263
264
265
266
267 #define RIO_DEV_PORT_N_MNT_REQ_CSR(d, n) \
268 (d->phys_efptr + RIO_PORT_N_MNT_REQ_CSR(n, d->phys_rmap))
269
270 #define RIO_DEV_PORT_N_MNT_RSP_CSR(d, n) \
271 (d->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(n, d->phys_rmap))
272
273 #define RIO_DEV_PORT_N_ACK_STS_CSR(d, n) \
274 (d->phys_efptr + RIO_PORT_N_ACK_STS_CSR(n))
275
276 #define RIO_DEV_PORT_N_CTL2_CSR(d, n) \
277 (d->phys_efptr + RIO_PORT_N_CTL2_CSR(n, d->phys_rmap))
278
279 #define RIO_DEV_PORT_N_ERR_STS_CSR(d, n) \
280 (d->phys_efptr + RIO_PORT_N_ERR_STS_CSR(n, d->phys_rmap))
281
282 #define RIO_DEV_PORT_N_CTL_CSR(d, n) \
283 (d->phys_efptr + RIO_PORT_N_CTL_CSR(n, d->phys_rmap))
284
285 #define RIO_DEV_PORT_N_OB_ACK_CSR(d, n) \
286 (d->phys_efptr + RIO_PORT_N_OB_ACK_CSR(n))
287
288 #define RIO_DEV_PORT_N_IB_ACK_CSR(d, n) \
289 (d->phys_efptr + RIO_PORT_N_IB_ACK_CSR(n))
290
291
292
293
294
295
296
297
298
299 #define RIO_EM_EFB_HEADER 0x000
300 #define RIO_EM_EMHS_CAR 0x004
301 #define RIO_EM_LTL_ERR_DETECT 0x008
302 #define RIO_EM_LTL_ERR_EN 0x00c
303 #define REM_LTL_ERR_ILLTRAN 0x08000000
304 #define REM_LTL_ERR_UNSOLR 0x00800000
305 #define REM_LTL_ERR_UNSUPTR 0x00400000
306 #define REM_LTL_ERR_IMPSPEC 0x000000ff
307 #define RIO_EM_LTL_HIADDR_CAP 0x010
308 #define RIO_EM_LTL_ADDR_CAP 0x014
309 #define RIO_EM_LTL_DEVID_CAP 0x018
310 #define RIO_EM_LTL_CTRL_CAP 0x01c
311 #define RIO_EM_LTL_DID32_CAP 0x020
312 #define RIO_EM_LTL_SID32_CAP 0x024
313 #define RIO_EM_PW_TGT_DEVID 0x028
314 #define RIO_EM_PW_TGT_DEVID_D16M 0xff000000
315 #define RIO_EM_PW_TGT_DEVID_D8 0x00ff0000
316 #define RIO_EM_PW_TGT_DEVID_DEV16 0x00008000
317 #define RIO_EM_PW_TGT_DEVID_DEV32 0x00004000
318 #define RIO_EM_PKT_TTL 0x02c
319 #define RIO_EM_PKT_TTL_VAL 0xffff0000
320 #define RIO_EM_PW_TGT32_DEVID 0x030
321 #define RIO_EM_PW_TX_CTRL 0x034
322 #define RIO_EM_PW_TX_CTRL_PW_DIS 0x00000001
323
324
325
326 #define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40)
327 #define REM_PED_IMPL_SPEC 0x80000000
328 #define REM_PED_LINK_OK2U 0x40000000
329 #define REM_PED_LINK_UPDA 0x20000000
330 #define REM_PED_LINK_U2OK 0x10000000
331 #define REM_PED_LINK_TO 0x00000001
332
333 #define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40)
334 #define RIO_EM_PN_ERRRATE_EN_OK2U 0x40000000
335 #define RIO_EM_PN_ERRRATE_EN_UPDA 0x20000000
336 #define RIO_EM_PN_ERRRATE_EN_U2OK 0x10000000
337
338 #define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40)
339 #define RIO_EM_PN_PKT_CAP_0(x) (0x04c + x*0x40)
340 #define RIO_EM_PN_PKT_CAP_1(x) (0x050 + x*0x40)
341 #define RIO_EM_PN_PKT_CAP_2(x) (0x054 + x*0x40)
342 #define RIO_EM_PN_PKT_CAP_3(x) (0x058 + x*0x40)
343 #define RIO_EM_PN_ERRRATE(x) (0x068 + x*0x40)
344 #define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40)
345 #define RIO_EM_PN_LINK_UDT(x) (0x070 + x*0x40)
346 #define RIO_EM_PN_LINK_UDT_TO 0xffffff00
347
348
349
350
351
352
353
354 #define RIO_BC_RT_CTL_CSR 0x020
355 #define RIO_RT_CTL_THREE_LVL 0x80000000
356 #define RIO_RT_CTL_DEV32_RT_CTRL 0x40000000
357 #define RIO_RT_CTL_MC_MASK_SZ 0x03000000
358
359
360 #define RIO_BC_RT_LVL0_INFO_CSR 0x030
361 #define RIO_RT_L0I_NUM_GR 0xff000000
362 #define RIO_RT_L0I_GR_PTR 0x00fffc00
363
364
365 #define RIO_BC_RT_LVL1_INFO_CSR 0x034
366 #define RIO_RT_L1I_NUM_GR 0xff000000
367 #define RIO_RT_L1I_GR_PTR 0x00fffc00
368
369
370 #define RIO_BC_RT_LVL2_INFO_CSR 0x038
371 #define RIO_RT_L2I_NUM_GR 0xff000000
372 #define RIO_RT_L2I_GR_PTR 0x00fffc00
373
374
375
376
377
378 #define RIO_SPx_RT_CTL_CSR(x) (0x040 + (0x20 * x))
379 #define RIO_SPx_RT_LVL0_INFO_CSR(x) (0x50 + (0x20 * x))
380 #define RIO_SPx_RT_LVL1_INFO_CSR(x) (0x54 + (0x20 * x))
381 #define RIO_SPx_RT_LVL2_INFO_CSR(x) (0x58 + (0x20 * x))
382
383
384
385
386
387 #define RIO_RT_Ln_ENTRY_IMPL_DEF 0xf0000000
388 #define RIO_RT_Ln_ENTRY_RTE_VAL 0x000003ff
389 #define RIO_RT_ENTRY_DROP_PKT 0x300
390
391 #endif