root/include/linux/mfd/sta2x11-mfd.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. sta2x11_apbreg_mask
  2. sta2x11_sctl_mask
  3. sta2x11_apb_soc_regs_mask
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2009-2011 Wind River Systems, Inc.
   4  * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini)
   5  *
   6  * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated
   7  * functions in one PCI endpoint functions. This driver simply
   8  * registers the platform devices in this iomemregion and exports a few
   9  * functions to access common registers
  10  */
  11 
  12 #ifndef __STA2X11_MFD_H
  13 #define __STA2X11_MFD_H
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 
  17 enum sta2x11_mfd_plat_dev {
  18         sta2x11_sctl = 0,
  19         sta2x11_gpio,
  20         sta2x11_scr,
  21         sta2x11_time,
  22         sta2x11_apbreg,
  23         sta2x11_apb_soc_regs,
  24         sta2x11_vic,
  25         sta2x11_n_mfd_plat_devs,
  26 };
  27 
  28 #define STA2X11_MFD_SCTL_NAME          "sta2x11-sctl"
  29 #define STA2X11_MFD_GPIO_NAME          "sta2x11-gpio"
  30 #define STA2X11_MFD_SCR_NAME           "sta2x11-scr"
  31 #define STA2X11_MFD_TIME_NAME          "sta2x11-time"
  32 #define STA2X11_MFD_APBREG_NAME        "sta2x11-apbreg"
  33 #define STA2X11_MFD_APB_SOC_REGS_NAME  "sta2x11-apb-soc-regs"
  34 #define STA2X11_MFD_VIC_NAME           "sta2x11-vic"
  35 
  36 extern u32
  37 __sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev);
  38 
  39 /*
  40  * The MFD PCI block includes the GPIO peripherals and other register blocks.
  41  * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
  42  */
  43 #define GSTA_GPIO_PER_BLOCK     32
  44 #define GSTA_NR_BLOCKS          4
  45 #define GSTA_NR_GPIO            (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS)
  46 
  47 /* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */
  48 struct sta2x11_gpio_pdata {
  49         unsigned pinconfig[GSTA_NR_GPIO];
  50 };
  51 
  52 /* Macros below lifted from sh_pfc.h, with minor differences */
  53 #define PINMUX_TYPE_NONE                0
  54 #define PINMUX_TYPE_FUNCTION            1
  55 #define PINMUX_TYPE_OUTPUT_LOW          2
  56 #define PINMUX_TYPE_OUTPUT_HIGH         3
  57 #define PINMUX_TYPE_INPUT               4
  58 #define PINMUX_TYPE_INPUT_PULLUP        5
  59 #define PINMUX_TYPE_INPUT_PULLDOWN      6
  60 
  61 /* Give names to GPIO pins, like PXA does, taken from the manual */
  62 #define STA2X11_GPIO0                   0
  63 #define STA2X11_GPIO1                   1
  64 #define STA2X11_GPIO2                   2
  65 #define STA2X11_GPIO3                   3
  66 #define STA2X11_GPIO4                   4
  67 #define STA2X11_GPIO5                   5
  68 #define STA2X11_GPIO6                   6
  69 #define STA2X11_GPIO7                   7
  70 #define STA2X11_GPIO8_RGBOUT_RED7       8
  71 #define STA2X11_GPIO9_RGBOUT_RED6       9
  72 #define STA2X11_GPIO10_RGBOUT_RED5      10
  73 #define STA2X11_GPIO11_RGBOUT_RED4      11
  74 #define STA2X11_GPIO12_RGBOUT_RED3      12
  75 #define STA2X11_GPIO13_RGBOUT_RED2      13
  76 #define STA2X11_GPIO14_RGBOUT_RED1      14
  77 #define STA2X11_GPIO15_RGBOUT_RED0      15
  78 #define STA2X11_GPIO16_RGBOUT_GREEN7    16
  79 #define STA2X11_GPIO17_RGBOUT_GREEN6    17
  80 #define STA2X11_GPIO18_RGBOUT_GREEN5    18
  81 #define STA2X11_GPIO19_RGBOUT_GREEN4    19
  82 #define STA2X11_GPIO20_RGBOUT_GREEN3    20
  83 #define STA2X11_GPIO21_RGBOUT_GREEN2    21
  84 #define STA2X11_GPIO22_RGBOUT_GREEN1    22
  85 #define STA2X11_GPIO23_RGBOUT_GREEN0    23
  86 #define STA2X11_GPIO24_RGBOUT_BLUE7     24
  87 #define STA2X11_GPIO25_RGBOUT_BLUE6     25
  88 #define STA2X11_GPIO26_RGBOUT_BLUE5     26
  89 #define STA2X11_GPIO27_RGBOUT_BLUE4     27
  90 #define STA2X11_GPIO28_RGBOUT_BLUE3     28
  91 #define STA2X11_GPIO29_RGBOUT_BLUE2     29
  92 #define STA2X11_GPIO30_RGBOUT_BLUE1     30
  93 #define STA2X11_GPIO31_RGBOUT_BLUE0     31
  94 #define STA2X11_GPIO32_RGBOUT_VSYNCH    32
  95 #define STA2X11_GPIO33_RGBOUT_HSYNCH    33
  96 #define STA2X11_GPIO34_RGBOUT_DEN       34
  97 #define STA2X11_GPIO35_ETH_CRS_DV       35
  98 #define STA2X11_GPIO36_ETH_TXD1         36
  99 #define STA2X11_GPIO37_ETH_TXD0         37
 100 #define STA2X11_GPIO38_ETH_TX_EN        38
 101 #define STA2X11_GPIO39_MDIO             39
 102 #define STA2X11_GPIO40_ETH_REF_CLK      40
 103 #define STA2X11_GPIO41_ETH_RXD1         41
 104 #define STA2X11_GPIO42_ETH_RXD0         42
 105 #define STA2X11_GPIO43_MDC              43
 106 #define STA2X11_GPIO44_CAN_TX           44
 107 #define STA2X11_GPIO45_CAN_RX           45
 108 #define STA2X11_GPIO46_MLB_DAT          46
 109 #define STA2X11_GPIO47_MLB_SIG          47
 110 #define STA2X11_GPIO48_SPI0_CLK         48
 111 #define STA2X11_GPIO49_SPI0_TXD         49
 112 #define STA2X11_GPIO50_SPI0_RXD         50
 113 #define STA2X11_GPIO51_SPI0_FRM         51
 114 #define STA2X11_GPIO52_SPI1_CLK         52
 115 #define STA2X11_GPIO53_SPI1_TXD         53
 116 #define STA2X11_GPIO54_SPI1_RXD         54
 117 #define STA2X11_GPIO55_SPI1_FRM         55
 118 #define STA2X11_GPIO56_SPI2_CLK         56
 119 #define STA2X11_GPIO57_SPI2_TXD         57
 120 #define STA2X11_GPIO58_SPI2_RXD         58
 121 #define STA2X11_GPIO59_SPI2_FRM         59
 122 #define STA2X11_GPIO60_I2C0_SCL         60
 123 #define STA2X11_GPIO61_I2C0_SDA         61
 124 #define STA2X11_GPIO62_I2C1_SCL         62
 125 #define STA2X11_GPIO63_I2C1_SDA         63
 126 #define STA2X11_GPIO64_I2C2_SCL         64
 127 #define STA2X11_GPIO65_I2C2_SDA         65
 128 #define STA2X11_GPIO66_I2C3_SCL         66
 129 #define STA2X11_GPIO67_I2C3_SDA         67
 130 #define STA2X11_GPIO68_MSP0_RCK         68
 131 #define STA2X11_GPIO69_MSP0_RXD         69
 132 #define STA2X11_GPIO70_MSP0_RFS         70
 133 #define STA2X11_GPIO71_MSP0_TCK         71
 134 #define STA2X11_GPIO72_MSP0_TXD         72
 135 #define STA2X11_GPIO73_MSP0_TFS         73
 136 #define STA2X11_GPIO74_MSP0_SCK         74
 137 #define STA2X11_GPIO75_MSP1_CK          75
 138 #define STA2X11_GPIO76_MSP1_RXD         76
 139 #define STA2X11_GPIO77_MSP1_FS          77
 140 #define STA2X11_GPIO78_MSP1_TXD         78
 141 #define STA2X11_GPIO79_MSP2_CK          79
 142 #define STA2X11_GPIO80_MSP2_RXD         80
 143 #define STA2X11_GPIO81_MSP2_FS          81
 144 #define STA2X11_GPIO82_MSP2_TXD         82
 145 #define STA2X11_GPIO83_MSP3_CK          83
 146 #define STA2X11_GPIO84_MSP3_RXD         84
 147 #define STA2X11_GPIO85_MSP3_FS          85
 148 #define STA2X11_GPIO86_MSP3_TXD         86
 149 #define STA2X11_GPIO87_MSP4_CK          87
 150 #define STA2X11_GPIO88_MSP4_RXD         88
 151 #define STA2X11_GPIO89_MSP4_FS          89
 152 #define STA2X11_GPIO90_MSP4_TXD         90
 153 #define STA2X11_GPIO91_MSP5_CK          91
 154 #define STA2X11_GPIO92_MSP5_RXD         92
 155 #define STA2X11_GPIO93_MSP5_FS          93
 156 #define STA2X11_GPIO94_MSP5_TXD         94
 157 #define STA2X11_GPIO95_SDIO3_DAT3       95
 158 #define STA2X11_GPIO96_SDIO3_DAT2       96
 159 #define STA2X11_GPIO97_SDIO3_DAT1       97
 160 #define STA2X11_GPIO98_SDIO3_DAT0       98
 161 #define STA2X11_GPIO99_SDIO3_CLK        99
 162 #define STA2X11_GPIO100_SDIO3_CMD       100
 163 #define STA2X11_GPIO101                 101
 164 #define STA2X11_GPIO102                 102
 165 #define STA2X11_GPIO103                 103
 166 #define STA2X11_GPIO104                 104
 167 #define STA2X11_GPIO105_SDIO2_DAT3      105
 168 #define STA2X11_GPIO106_SDIO2_DAT2      106
 169 #define STA2X11_GPIO107_SDIO2_DAT1      107
 170 #define STA2X11_GPIO108_SDIO2_DAT0      108
 171 #define STA2X11_GPIO109_SDIO2_CLK       109
 172 #define STA2X11_GPIO110_SDIO2_CMD       110
 173 #define STA2X11_GPIO111                 111
 174 #define STA2X11_GPIO112                 112
 175 #define STA2X11_GPIO113                 113
 176 #define STA2X11_GPIO114                 114
 177 #define STA2X11_GPIO115_SDIO1_DAT3      115
 178 #define STA2X11_GPIO116_SDIO1_DAT2      116
 179 #define STA2X11_GPIO117_SDIO1_DAT1      117
 180 #define STA2X11_GPIO118_SDIO1_DAT0      118
 181 #define STA2X11_GPIO119_SDIO1_CLK       119
 182 #define STA2X11_GPIO120_SDIO1_CMD       120
 183 #define STA2X11_GPIO121                 121
 184 #define STA2X11_GPIO122                 122
 185 #define STA2X11_GPIO123                 123
 186 #define STA2X11_GPIO124                 124
 187 #define STA2X11_GPIO125_UART2_TXD       125
 188 #define STA2X11_GPIO126_UART2_RXD       126
 189 #define STA2X11_GPIO127_UART3_TXD       127
 190 
 191 /*
 192  * The APB bridge has its own registers, needed by our users as well.
 193  * They are accessed with the following read/mask/write function.
 194  */
 195 static inline u32
 196 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
 197 {
 198         return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg);
 199 }
 200 
 201 /* CAN and MLB */
 202 #define APBREG_BSR      0x00    /* Bridge Status Reg */
 203 #define APBREG_PAER     0x08    /* Peripherals Address Error Reg */
 204 #define APBREG_PWAC     0x20    /* Peripheral Write Access Control reg */
 205 #define APBREG_PRAC     0x40    /* Peripheral Read Access Control reg */
 206 #define APBREG_PCG      0x60    /* Peripheral Clock Gating Reg */
 207 #define APBREG_PUR      0x80    /* Peripheral Under Reset Reg */
 208 #define APBREG_EMU_PCG  0xA0    /* Emulator Peripheral Clock Gating Reg */
 209 
 210 #define APBREG_CAN      (1 << 1)
 211 #define APBREG_MLB      (1 << 3)
 212 
 213 /* SARAC */
 214 #define APBREG_BSR_SARAC     0x100 /* Bridge Status Reg */
 215 #define APBREG_PAER_SARAC    0x108 /* Peripherals Address Error Reg */
 216 #define APBREG_PWAC_SARAC    0x120 /* Peripheral Write Access Control reg */
 217 #define APBREG_PRAC_SARAC    0x140 /* Peripheral Read Access Control reg */
 218 #define APBREG_PCG_SARAC     0x160 /* Peripheral Clock Gating Reg */
 219 #define APBREG_PUR_SARAC     0x180 /* Peripheral Under Reset Reg */
 220 #define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
 221 
 222 #define APBREG_SARAC    (1 << 2)
 223 
 224 /*
 225  * The system controller has its own registers. Some of these are accessed
 226  * by out users as well, using the following read/mask/write/function
 227  */
 228 static inline
 229 u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
 230 {
 231         return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl);
 232 }
 233 
 234 #define SCTL_SCCTL              0x00    /* System controller control register */
 235 #define SCTL_ARMCFG             0x04    /* ARM configuration register */
 236 #define SCTL_SCPLLCTL           0x08    /* PLL control status register */
 237 
 238 #define SCTL_SCPLLCTL_AUDIO_PLL_PD           BIT(1)
 239 #define SCTL_SCPLLCTL_FRAC_CONTROL           BIT(3)
 240 #define SCTL_SCPLLCTL_STRB_BYPASS            BIT(6)
 241 #define SCTL_SCPLLCTL_STRB_INPUT             BIT(8)
 242 
 243 #define SCTL_SCPLLFCTRL         0x0c    /* PLL frequency control register */
 244 
 245 #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK     0xff
 246 #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT      10
 247 #define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK         7
 248 #define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT       21
 249 #define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK         7
 250 #define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT       18
 251 #define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK     0x03
 252 #define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT       4
 253 
 254 
 255 #define SCTL_SCRESFRACT         0x10    /* PLL fractional input register */
 256 
 257 #define SCTL_SCRESFRACT_MASK    0x0000ffff
 258 
 259 
 260 #define SCTL_SCRESCTRL1         0x14    /* Peripheral reset control 1 */
 261 #define SCTL_SCRESXTRL2         0x18    /* Peripheral reset control 2 */
 262 #define SCTL_SCPEREN0           0x1c    /* Peripheral clock enable register 0 */
 263 #define SCTL_SCPEREN1           0x20    /* Peripheral clock enable register 1 */
 264 #define SCTL_SCPEREN2           0x24    /* Peripheral clock enable register 2 */
 265 #define SCTL_SCGRST             0x28    /* Peripheral global reset */
 266 #define SCTL_SCPCIECSBRST       0x2c    /* PCIe PAB CSB reset status register */
 267 #define SCTL_SCPCIPMCR1         0x30    /* PCI power management control 1 */
 268 #define SCTL_SCPCIPMCR2         0x34    /* PCI power management control 2 */
 269 #define SCTL_SCPCIPMSR1         0x38    /* PCI power management status 1 */
 270 #define SCTL_SCPCIPMSR2         0x3c    /* PCI power management status 2 */
 271 #define SCTL_SCPCIPMSR3         0x40    /* PCI power management status 3 */
 272 #define SCTL_SCINTREN           0x44    /* Interrupt enable */
 273 #define SCTL_SCRISR             0x48    /* RAW interrupt status */
 274 #define SCTL_SCCLKSTAT0         0x4c    /* Peripheral clocks status 0 */
 275 #define SCTL_SCCLKSTAT1         0x50    /* Peripheral clocks status 1 */
 276 #define SCTL_SCCLKSTAT2         0x54    /* Peripheral clocks status 2 */
 277 #define SCTL_SCRSTSTA           0x58    /* Reset status register */
 278 
 279 #define SCTL_SCRESCTRL1_USB_PHY_POR     (1 << 0)
 280 #define SCTL_SCRESCTRL1_USB_OTG (1 << 1)
 281 #define SCTL_SCRESCTRL1_USB_HRST        (1 << 2)
 282 #define SCTL_SCRESCTRL1_USB_PHY_HOST    (1 << 3)
 283 #define SCTL_SCRESCTRL1_SATAII  (1 << 4)
 284 #define SCTL_SCRESCTRL1_VIP             (1 << 5)
 285 #define SCTL_SCRESCTRL1_PER_MMC0        (1 << 6)
 286 #define SCTL_SCRESCTRL1_PER_MMC1        (1 << 7)
 287 #define SCTL_SCRESCTRL1_PER_GPIO0       (1 << 8)
 288 #define SCTL_SCRESCTRL1_PER_GPIO1       (1 << 9)
 289 #define SCTL_SCRESCTRL1_PER_GPIO2       (1 << 10)
 290 #define SCTL_SCRESCTRL1_PER_GPIO3       (1 << 11)
 291 #define SCTL_SCRESCTRL1_PER_MTU0        (1 << 12)
 292 #define SCTL_SCRESCTRL1_KER_SPI0        (1 << 13)
 293 #define SCTL_SCRESCTRL1_KER_SPI1        (1 << 14)
 294 #define SCTL_SCRESCTRL1_KER_SPI2        (1 << 15)
 295 #define SCTL_SCRESCTRL1_KER_MCI0        (1 << 16)
 296 #define SCTL_SCRESCTRL1_KER_MCI1        (1 << 17)
 297 #define SCTL_SCRESCTRL1_PRE_HSI2C0      (1 << 18)
 298 #define SCTL_SCRESCTRL1_PER_HSI2C1      (1 << 19)
 299 #define SCTL_SCRESCTRL1_PER_HSI2C2      (1 << 20)
 300 #define SCTL_SCRESCTRL1_PER_HSI2C3      (1 << 21)
 301 #define SCTL_SCRESCTRL1_PER_MSP0        (1 << 22)
 302 #define SCTL_SCRESCTRL1_PER_MSP1        (1 << 23)
 303 #define SCTL_SCRESCTRL1_PER_MSP2        (1 << 24)
 304 #define SCTL_SCRESCTRL1_PER_MSP3        (1 << 25)
 305 #define SCTL_SCRESCTRL1_PER_MSP4        (1 << 26)
 306 #define SCTL_SCRESCTRL1_PER_MSP5        (1 << 27)
 307 #define SCTL_SCRESCTRL1_PER_MMC (1 << 28)
 308 #define SCTL_SCRESCTRL1_KER_MSP0        (1 << 29)
 309 #define SCTL_SCRESCTRL1_KER_MSP1        (1 << 30)
 310 #define SCTL_SCRESCTRL1_KER_MSP2        (1 << 31)
 311 
 312 #define SCTL_SCPEREN0_UART0             (1 << 0)
 313 #define SCTL_SCPEREN0_UART1             (1 << 1)
 314 #define SCTL_SCPEREN0_UART2             (1 << 2)
 315 #define SCTL_SCPEREN0_UART3             (1 << 3)
 316 #define SCTL_SCPEREN0_MSP0              (1 << 4)
 317 #define SCTL_SCPEREN0_MSP1              (1 << 5)
 318 #define SCTL_SCPEREN0_MSP2              (1 << 6)
 319 #define SCTL_SCPEREN0_MSP3              (1 << 7)
 320 #define SCTL_SCPEREN0_MSP4              (1 << 8)
 321 #define SCTL_SCPEREN0_MSP5              (1 << 9)
 322 #define SCTL_SCPEREN0_SPI0              (1 << 10)
 323 #define SCTL_SCPEREN0_SPI1              (1 << 11)
 324 #define SCTL_SCPEREN0_SPI2              (1 << 12)
 325 #define SCTL_SCPEREN0_I2C0              (1 << 13)
 326 #define SCTL_SCPEREN0_I2C1              (1 << 14)
 327 #define SCTL_SCPEREN0_I2C2              (1 << 15)
 328 #define SCTL_SCPEREN0_I2C3              (1 << 16)
 329 #define SCTL_SCPEREN0_SVDO_LVDS         (1 << 17)
 330 #define SCTL_SCPEREN0_USB_HOST          (1 << 18)
 331 #define SCTL_SCPEREN0_USB_OTG           (1 << 19)
 332 #define SCTL_SCPEREN0_MCI0              (1 << 20)
 333 #define SCTL_SCPEREN0_MCI1              (1 << 21)
 334 #define SCTL_SCPEREN0_MCI2              (1 << 22)
 335 #define SCTL_SCPEREN0_MCI3              (1 << 23)
 336 #define SCTL_SCPEREN0_SATA              (1 << 24)
 337 #define SCTL_SCPEREN0_ETHERNET          (1 << 25)
 338 #define SCTL_SCPEREN0_VIC               (1 << 26)
 339 #define SCTL_SCPEREN0_DMA_AUDIO         (1 << 27)
 340 #define SCTL_SCPEREN0_DMA_SOC           (1 << 28)
 341 #define SCTL_SCPEREN0_RAM               (1 << 29)
 342 #define SCTL_SCPEREN0_VIP               (1 << 30)
 343 #define SCTL_SCPEREN0_ARM               (1 << 31)
 344 
 345 #define SCTL_SCPEREN1_UART0             (1 << 0)
 346 #define SCTL_SCPEREN1_UART1             (1 << 1)
 347 #define SCTL_SCPEREN1_UART2             (1 << 2)
 348 #define SCTL_SCPEREN1_UART3             (1 << 3)
 349 #define SCTL_SCPEREN1_MSP0              (1 << 4)
 350 #define SCTL_SCPEREN1_MSP1              (1 << 5)
 351 #define SCTL_SCPEREN1_MSP2              (1 << 6)
 352 #define SCTL_SCPEREN1_MSP3              (1 << 7)
 353 #define SCTL_SCPEREN1_MSP4              (1 << 8)
 354 #define SCTL_SCPEREN1_MSP5              (1 << 9)
 355 #define SCTL_SCPEREN1_SPI0              (1 << 10)
 356 #define SCTL_SCPEREN1_SPI1              (1 << 11)
 357 #define SCTL_SCPEREN1_SPI2              (1 << 12)
 358 #define SCTL_SCPEREN1_I2C0              (1 << 13)
 359 #define SCTL_SCPEREN1_I2C1              (1 << 14)
 360 #define SCTL_SCPEREN1_I2C2              (1 << 15)
 361 #define SCTL_SCPEREN1_I2C3              (1 << 16)
 362 #define SCTL_SCPEREN1_USB_PHY           (1 << 17)
 363 
 364 /*
 365  * APB-SOC registers
 366  */
 367 static inline
 368 u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
 369 {
 370         return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs);
 371 }
 372 
 373 #define PCIE_EP1_FUNC3_0_INTR_REG       0x000
 374 #define PCIE_EP1_FUNC7_4_INTR_REG       0x004
 375 #define PCIE_EP2_FUNC3_0_INTR_REG       0x008
 376 #define PCIE_EP2_FUNC7_4_INTR_REG       0x00c
 377 #define PCIE_EP3_FUNC3_0_INTR_REG       0x010
 378 #define PCIE_EP3_FUNC7_4_INTR_REG       0x014
 379 #define PCIE_EP4_FUNC3_0_INTR_REG       0x018
 380 #define PCIE_EP4_FUNC7_4_INTR_REG       0x01c
 381 #define PCIE_INTR_ENABLE0_REG           0x020
 382 #define PCIE_INTR_ENABLE1_REG           0x024
 383 #define PCIE_EP1_FUNC_TC_REG            0x028
 384 #define PCIE_EP2_FUNC_TC_REG            0x02c
 385 #define PCIE_EP3_FUNC_TC_REG            0x030
 386 #define PCIE_EP4_FUNC_TC_REG            0x034
 387 #define PCIE_EP1_FUNC_F_REG             0x038
 388 #define PCIE_EP2_FUNC_F_REG             0x03c
 389 #define PCIE_EP3_FUNC_F_REG             0x040
 390 #define PCIE_EP4_FUNC_F_REG             0x044
 391 #define PCIE_PAB_AMBA_SW_RST_REG        0x048
 392 #define PCIE_PM_STATUS_0_PORT_0_4       0x04c
 393 #define PCIE_PM_STATUS_7_0_EP1          0x050
 394 #define PCIE_PM_STATUS_7_0_EP2          0x054
 395 #define PCIE_PM_STATUS_7_0_EP3          0x058
 396 #define PCIE_PM_STATUS_7_0_EP4          0x05c
 397 #define PCIE_DEV_ID_0_EP1_REG           0x060
 398 #define PCIE_CC_REV_ID_0_EP1_REG        0x064
 399 #define PCIE_DEV_ID_1_EP1_REG           0x068
 400 #define PCIE_CC_REV_ID_1_EP1_REG        0x06c
 401 #define PCIE_DEV_ID_2_EP1_REG           0x070
 402 #define PCIE_CC_REV_ID_2_EP1_REG        0x074
 403 #define PCIE_DEV_ID_3_EP1_REG           0x078
 404 #define PCIE_CC_REV_ID_3_EP1_REG        0x07c
 405 #define PCIE_DEV_ID_4_EP1_REG           0x080
 406 #define PCIE_CC_REV_ID_4_EP1_REG        0x084
 407 #define PCIE_DEV_ID_5_EP1_REG           0x088
 408 #define PCIE_CC_REV_ID_5_EP1_REG        0x08c
 409 #define PCIE_DEV_ID_6_EP1_REG           0x090
 410 #define PCIE_CC_REV_ID_6_EP1_REG        0x094
 411 #define PCIE_DEV_ID_7_EP1_REG           0x098
 412 #define PCIE_CC_REV_ID_7_EP1_REG        0x09c
 413 #define PCIE_DEV_ID_0_EP2_REG           0x0a0
 414 #define PCIE_CC_REV_ID_0_EP2_REG        0x0a4
 415 #define PCIE_DEV_ID_1_EP2_REG           0x0a8
 416 #define PCIE_CC_REV_ID_1_EP2_REG        0x0ac
 417 #define PCIE_DEV_ID_2_EP2_REG           0x0b0
 418 #define PCIE_CC_REV_ID_2_EP2_REG        0x0b4
 419 #define PCIE_DEV_ID_3_EP2_REG           0x0b8
 420 #define PCIE_CC_REV_ID_3_EP2_REG        0x0bc
 421 #define PCIE_DEV_ID_4_EP2_REG           0x0c0
 422 #define PCIE_CC_REV_ID_4_EP2_REG        0x0c4
 423 #define PCIE_DEV_ID_5_EP2_REG           0x0c8
 424 #define PCIE_CC_REV_ID_5_EP2_REG        0x0cc
 425 #define PCIE_DEV_ID_6_EP2_REG           0x0d0
 426 #define PCIE_CC_REV_ID_6_EP2_REG        0x0d4
 427 #define PCIE_DEV_ID_7_EP2_REG           0x0d8
 428 #define PCIE_CC_REV_ID_7_EP2_REG        0x0dC
 429 #define PCIE_DEV_ID_0_EP3_REG           0x0e0
 430 #define PCIE_CC_REV_ID_0_EP3_REG        0x0e4
 431 #define PCIE_DEV_ID_1_EP3_REG           0x0e8
 432 #define PCIE_CC_REV_ID_1_EP3_REG        0x0ec
 433 #define PCIE_DEV_ID_2_EP3_REG           0x0f0
 434 #define PCIE_CC_REV_ID_2_EP3_REG        0x0f4
 435 #define PCIE_DEV_ID_3_EP3_REG           0x0f8
 436 #define PCIE_CC_REV_ID_3_EP3_REG        0x0fc
 437 #define PCIE_DEV_ID_4_EP3_REG           0x100
 438 #define PCIE_CC_REV_ID_4_EP3_REG        0x104
 439 #define PCIE_DEV_ID_5_EP3_REG           0x108
 440 #define PCIE_CC_REV_ID_5_EP3_REG        0x10c
 441 #define PCIE_DEV_ID_6_EP3_REG           0x110
 442 #define PCIE_CC_REV_ID_6_EP3_REG        0x114
 443 #define PCIE_DEV_ID_7_EP3_REG           0x118
 444 #define PCIE_CC_REV_ID_7_EP3_REG        0x11c
 445 #define PCIE_DEV_ID_0_EP4_REG           0x120
 446 #define PCIE_CC_REV_ID_0_EP4_REG        0x124
 447 #define PCIE_DEV_ID_1_EP4_REG           0x128
 448 #define PCIE_CC_REV_ID_1_EP4_REG        0x12c
 449 #define PCIE_DEV_ID_2_EP4_REG           0x130
 450 #define PCIE_CC_REV_ID_2_EP4_REG        0x134
 451 #define PCIE_DEV_ID_3_EP4_REG           0x138
 452 #define PCIE_CC_REV_ID_3_EP4_REG        0x13c
 453 #define PCIE_DEV_ID_4_EP4_REG           0x140
 454 #define PCIE_CC_REV_ID_4_EP4_REG        0x144
 455 #define PCIE_DEV_ID_5_EP4_REG           0x148
 456 #define PCIE_CC_REV_ID_5_EP4_REG        0x14c
 457 #define PCIE_DEV_ID_6_EP4_REG           0x150
 458 #define PCIE_CC_REV_ID_6_EP4_REG        0x154
 459 #define PCIE_DEV_ID_7_EP4_REG           0x158
 460 #define PCIE_CC_REV_ID_7_EP4_REG        0x15c
 461 #define PCIE_SUBSYS_VEN_ID_REG          0x160
 462 #define PCIE_COMMON_CLOCK_CONFIG_0_4_0  0x164
 463 #define PCIE_MIPHYP_SSC_EN_REG          0x168
 464 #define PCIE_MIPHYP_ADDR_REG            0x16c
 465 #define PCIE_L1_ASPM_READY_REG          0x170
 466 #define PCIE_EXT_CFG_RDY_REG            0x174
 467 #define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
 468 #define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
 469 #define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
 470 #define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
 471 #define DMA_IP_CTRL_REG                 0x324
 472 #define DISP_BRIDGE_PU_PD_CTRL_REG      0x328
 473 #define VIP_PU_PD_CTRL_REG              0x32c
 474 #define USB_MLB_PU_PD_CTRL_REG          0x330
 475 #define SDIO_PU_PD_MISCFUNC_CTRL_REG1   0x334
 476 #define SDIO_PU_PD_MISCFUNC_CTRL_REG2   0x338
 477 #define UART_PU_PD_CTRL_REG             0x33c
 478 #define ARM_Lock                        0x340
 479 #define SYS_IO_CHAR_REG1                0x344
 480 #define SYS_IO_CHAR_REG2                0x348
 481 #define SATA_CORE_ID_REG                0x34c
 482 #define SATA_CTRL_REG                   0x350
 483 #define I2C_HSFIX_MISC_REG              0x354
 484 #define SPARE2_RESERVED                 0x358
 485 #define SPARE3_RESERVED                 0x35c
 486 #define MASTER_LOCK_REG                 0x368
 487 #define SYSTEM_CONFIG_STATUS_REG        0x36c
 488 #define MSP_CLK_CTRL_REG                0x39c
 489 #define COMPENSATION_REG1               0x3c4
 490 #define COMPENSATION_REG2               0x3c8
 491 #define COMPENSATION_REG3               0x3cc
 492 #define TEST_CTL_REG                    0x3d0
 493 
 494 /*
 495  * SECR (OTP) registers
 496  */
 497 #define STA2X11_SECR_CR                 0x00
 498 #define STA2X11_SECR_FVR0               0x10
 499 #define STA2X11_SECR_FVR1               0x14
 500 
 501 extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev,
 502                                      enum sta2x11_mfd_plat_dev index,
 503                                      void __iomem **regs,
 504                                      spinlock_t **lock);
 505 
 506 #endif /* __STA2X11_MFD_H */
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