This source file includes following definitions.
- db8500_prcmu_early_init
- prcmu_set_rc_a2p
- prcmu_get_rc_p2a
- prcmu_get_xp70_current_state
- prcmu_has_arm_maxopp
- prcmu_get_fw_version
- db8500_prcmu_set_ape_opp
- db8500_prcmu_get_ape_opp
- db8500_prcmu_request_ape_opp_100_voltage
- prcmu_release_usb_wakeup_state
- db8500_prcmu_get_ddr_opp
- prcmu_configure_auto_pm
- prcmu_is_auto_pm_enabled
- prcmu_config_clkout
- prcmu_set_clock_divider
- db8500_prcmu_config_hotdog
- db8500_prcmu_config_hotmon
- db8500_prcmu_start_temp_sense
- db8500_prcmu_stop_temp_sense
- prcmu_abb_read
- prcmu_abb_write
- prcmu_ac_wake_req
- prcmu_ac_sleep_req
- db8500_prcmu_modem_reset
- db8500_prcmu_system_reset
- db8500_prcmu_set_power_state
- db8500_prcmu_get_power_state_result
- db8500_prcmu_enable_wakeups
- db8500_prcmu_set_epod
- db8500_prcmu_request_clock
- db8500_prcmu_set_display_clocks
- db8500_prcmu_disable_dsipll
- db8500_prcmu_enable_dsipll
- db8500_prcmu_config_esram0_deep_sleep
- db8500_prcmu_config_abb_event_readout
- db8500_prcmu_get_abb_event_buffer
- db8500_prcmu_get_reset_code
- db8500_prcmu_config_a9wdog
- db8500_prcmu_enable_a9wdog
- db8500_prcmu_disable_a9wdog
- db8500_prcmu_kick_a9wdog
- db8500_prcmu_load_a9wdog
- db8500_prcmu_is_ac_wake_requested
- db8500_prcmu_set_arm_opp
- db8500_prcmu_get_arm_opp
- db8500_prcmu_read
- db8500_prcmu_write
- db8500_prcmu_write_masked
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10 #ifndef __MFD_DB8500_PRCMU_H
11 #define __MFD_DB8500_PRCMU_H
12
13 #include <linux/interrupt.h>
14 #include <linux/bitops.h>
15
16
17
18
19 #define DB8500_PRCM_LINE_VALUE 0x170
20 #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
21
22 #define DB8500_PRCM_DSI_SW_RESET 0x324
23 #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
24 #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
25 #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
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34
35 enum state {
36 OFF = 0x0,
37 ON = 0x1,
38 };
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44 enum ret_state {
45 OFFST = 0,
46 ONST = 1,
47 RETST = 2
48 };
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58 enum clk_arm {
59 A9_OFF,
60 A9_BOOT,
61 A9_OPPT1,
62 A9_OPPT2,
63 A9_EXTCLK
64 };
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72 enum clk_gen {
73 GEN_OFF,
74 GEN_BOOT,
75 GEN_OPPT1,
76 };
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86 enum romcode_write {
87 RDY_2_DS = 0x09,
88 RDY_2_XP70_RST = 0x10
89 };
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106 enum romcode_read {
107 INIT = 0x00,
108 FS_2_DS = 0x0A,
109 END_DS = 0x0B,
110 DS_TO_FS = 0x0C,
111 END_FS = 0x0D,
112 SWR = 0x0E,
113 END_SWR = 0x0F
114 };
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126 enum ap_pwrst {
127 NO_PWRST = 0x00,
128 AP_BOOT = 0x01,
129 AP_EXECUTE = 0x02,
130 AP_DEEP_SLEEP = 0x03,
131 AP_SLEEP = 0x04,
132 AP_IDLE = 0x05,
133 AP_RESET = 0x06
134 };
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146 enum ap_pwrst_trans {
147 PRCMU_AP_NO_CHANGE = 0x00,
148 APEXECUTE_TO_APSLEEP = 0x01,
149 APIDLE_TO_APSLEEP = 0x02,
150 PRCMU_AP_SLEEP = 0x01,
151 APBOOT_TO_APEXECUTE = 0x03,
152 APEXECUTE_TO_APDEEPSLEEP = 0x04,
153 PRCMU_AP_DEEP_SLEEP = 0x04,
154 APEXECUTE_TO_APIDLE = 0x05,
155 PRCMU_AP_IDLE = 0x05,
156 PRCMU_AP_DEEP_IDLE = 0x07,
157 };
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170 enum hw_acc_state {
171 HW_NO_CHANGE = 0x00,
172 HW_OFF = 0x01,
173 HW_OFF_RAMRET = 0x02,
174 HW_ON = 0x04
175 };
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204 enum ap_pwrsttr_status {
205 BOOT_TO_EXECUTEOK = 0xFF,
206 DEEPSLEEPOK = 0xFE,
207 SLEEPOK = 0xFD,
208 IDLEOK = 0xFC,
209 SOFTRESETOK = 0xFB,
210 SOFTRESETGO = 0xFA,
211 BOOT_TO_EXECUTE = 0xF9,
212 EXECUTE_TO_DEEPSLEEP = 0xF8,
213 DEEPSLEEP_TO_EXECUTE = 0xF7,
214 DEEPSLEEP_TO_EXECUTEOK = 0xF6,
215 EXECUTE_TO_SLEEP = 0xF5,
216 SLEEP_TO_EXECUTE = 0xF4,
217 SLEEP_TO_EXECUTEOK = 0xF3,
218 EXECUTE_TO_IDLE = 0xF2,
219 IDLE_TO_EXECUTE = 0xF1,
220 IDLE_TO_EXECUTEOK = 0xF0,
221 RDYTODS_RETURNTOEXE = 0xEF,
222 NORDYTODS_RETURNTOEXE = 0xEE,
223 EXETOSLEEP_RETURNTOEXE = 0xED,
224 EXETOIDLE_RETURNTOEXE = 0xEC,
225 INIT_STATUS = 0xEB,
226
227
228 INITERROR = 0x00,
229 PLLARMLOCKP_ER = 0x01,
230 PLLDDRLOCKP_ER = 0x02,
231 PLLSOCLOCKP_ER = 0x03,
232 PLLSOCK1LOCKP_ER = 0x04,
233 ARMWFI_ER = 0x05,
234 SYSCLKOK_ER = 0x06,
235 I2C_NACK_DATA_ER = 0x07,
236 BOOT_ER = 0x08,
237 I2C_STATUS_ALWAYS_1 = 0x0A,
238 I2C_NACK_REG_ADDR_ER = 0x0B,
239 I2C_NACK_DATA0123_ER = 0x1B,
240 I2C_NACK_ADDR_ER = 0x1F,
241 CURAPPWRSTISNOT_BOOT = 0x20,
242 CURAPPWRSTISNOT_EXECUTE = 0x21,
243 CURAPPWRSTISNOT_SLEEPMODE = 0x22,
244 CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
245 FIFO4500WUISNOT_WUPEVENT = 0x24,
246 PLL32KLOCKP_ER = 0x29,
247 DDRDEEPSLEEPOK_ER = 0x2A,
248 ROMCODEREADY_ER = 0x50,
249 WUPBEFOREDS = 0x51,
250 DDRCONFIG_ER = 0x52,
251 WUPBEFORESLEEP = 0x53,
252 WUPBEFOREIDLE = 0x54
253 };
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265 enum dvfs_stat {
266 DVFS_GO = 0xFF,
267 DVFS_ARM100OPPOK = 0xFE,
268 DVFS_ARM50OPPOK = 0xFD,
269 DVFS_ARMEXTCLKOK = 0xFC,
270 DVFS_NOCHGTCLKOK = 0xFB,
271 DVFS_INITSTATUS = 0x00
272 };
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279 enum sva_mmdsp_stat {
280 SVA_MMDSP_GO = 0xFF,
281 SVA_MMDSP_INIT = 0x00
282 };
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289 enum sia_mmdsp_stat {
290 SIA_MMDSP_GO = 0xFF,
291 SIA_MMDSP_INIT = 0x00
292 };
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351 enum mbox_to_arm_err {
352 INIT_ERR = 0x00,
353 PLLARMLOCKP_ERR = 0x01,
354 PLLDDRLOCKP_ERR = 0x02,
355 PLLSOC0LOCKP_ERR = 0x03,
356 PLLSOC1LOCKP_ERR = 0x04,
357 ARMWFI_ERR = 0x05,
358 SYSCLKOK_ERR = 0x06,
359 BOOT_ERR = 0x07,
360 ROMCODESAVECONTEXT = 0x08,
361 VARMHIGHSPEEDVALTO_ERR = 0x10,
362 VARMHIGHSPEEDACCESS_ERR = 0x11,
363 VARMLOWSPEEDVALTO_ERR = 0x12,
364 VARMLOWSPEEDACCESS_ERR = 0x13,
365 VARMRETENTIONVALTO_ERR = 0x14,
366 VARMRETENTIONACCESS_ERR = 0x15,
367 VAPEHIGHSPEEDVALTO_ERR = 0x16,
368 VSAFEHPVALTO_ERR = 0x17,
369 VMODSEL1VALTO_ERR = 0x18,
370 VMODSEL2VALTO_ERR = 0x19,
371 VARMOFFACCESS_ERR = 0x1A,
372 VAPEOFFACCESS_ERR = 0x1B,
373 VARMRETACCES_ERR = 0x1C,
374 CURAPPWRSTISNOTBOOT = 0x20,
375 CURAPPWRSTISNOTEXECUTE = 0x21,
376 CURAPPWRSTISNOTSLEEPMODE = 0x22,
377 CURAPPWRSTISNOTCORRECTDBG = 0x23,
378 ARMREGU1VALTO_ERR = 0x24,
379 ARMREGU2VALTO_ERR = 0x25,
380 VAPEREGUVALTO_ERR = 0x26,
381 VSMPS3REGUVALTO_ERR = 0x27,
382 VMODREGUVALTO_ERR = 0x28
383 };
384
385 enum hw_acc {
386 SVAMMDSP = 0,
387 SVAPIPE = 1,
388 SIAMMDSP = 2,
389 SIAPIPE = 3,
390 SGA = 4,
391 B2R2MCDE = 5,
392 ESRAM12 = 6,
393 ESRAM34 = 7,
394 };
395
396 enum cs_pwrmgt {
397 PWRDNCS0 = 0,
398 WKUPCS0 = 1,
399 PWRDNCS1 = 2,
400 WKUPCS1 = 3
401 };
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414 enum sia_sva_pwr_policy {
415 NO_CHGT = 0x0,
416 DSPOFF_HWPOFF = 0x1,
417 DSPOFFRAMRET_HWPOFF = 0x2,
418 DSPCLKOFF_HWPOFF = 0x3,
419 DSPCLKOFF_HWPCLKOFF = 0x4,
420 };
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428 enum auto_enable {
429 AUTO_OFF = 0x0,
430 AUTO_ON = 0x1,
431 };
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445 enum prcmu_power_status {
446 PRCMU_SLEEP_OK = 0xf3,
447 PRCMU_DEEP_SLEEP_OK = 0xf6,
448 PRCMU_IDLE_OK = 0xf0,
449 PRCMU_DEEPIDLE_OK = 0xe3,
450 PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
451 PRCMU_ARMPENDINGIT_ER = 0x93,
452 };
453
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457
458 #define PRCMU_AUTO_PM_OFF 0
459 #define PRCMU_AUTO_PM_ON 1
460
461 #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
462 #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
463
464 enum prcmu_auto_pm_policy {
465 PRCMU_AUTO_PM_POLICY_NO_CHANGE,
466 PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
467 PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
468 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
469 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
470 };
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481 struct prcmu_auto_pm_config {
482 u8 sia_auto_pm_enable;
483 u8 sia_power_on;
484 u8 sia_policy;
485 u8 sva_auto_pm_enable;
486 u8 sva_power_on;
487 u8 sva_policy;
488 };
489
490 #ifdef CONFIG_MFD_DB8500_PRCMU
491
492 void db8500_prcmu_early_init(u32 phy_base, u32 size);
493 int prcmu_set_rc_a2p(enum romcode_write);
494 enum romcode_read prcmu_get_rc_p2a(void);
495 enum ap_pwrst prcmu_get_xp70_current_state(void);
496 bool prcmu_has_arm_maxopp(void);
497 struct prcmu_fw_version *prcmu_get_fw_version(void);
498 int prcmu_release_usb_wakeup_state(void);
499 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
500 struct prcmu_auto_pm_config *idle);
501 bool prcmu_is_auto_pm_enabled(void);
502
503 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
504 int prcmu_set_clock_divider(u8 clock, u8 divider);
505 int db8500_prcmu_config_hotdog(u8 threshold);
506 int db8500_prcmu_config_hotmon(u8 low, u8 high);
507 int db8500_prcmu_start_temp_sense(u16 cycles32k);
508 int db8500_prcmu_stop_temp_sense(void);
509 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
510 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
511
512 int prcmu_ac_wake_req(void);
513 void prcmu_ac_sleep_req(void);
514 void db8500_prcmu_modem_reset(void);
515
516 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
517 int db8500_prcmu_enable_a9wdog(u8 id);
518 int db8500_prcmu_disable_a9wdog(u8 id);
519 int db8500_prcmu_kick_a9wdog(u8 id);
520 int db8500_prcmu_load_a9wdog(u8 id, u32 val);
521
522 void db8500_prcmu_system_reset(u16 reset_code);
523 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
524 u8 db8500_prcmu_get_power_state_result(void);
525 void db8500_prcmu_enable_wakeups(u32 wakeups);
526 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
527 int db8500_prcmu_request_clock(u8 clock, bool enable);
528 int db8500_prcmu_set_display_clocks(void);
529 int db8500_prcmu_disable_dsipll(void);
530 int db8500_prcmu_enable_dsipll(void);
531 void db8500_prcmu_config_abb_event_readout(u32 abb_events);
532 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
533 int db8500_prcmu_config_esram0_deep_sleep(u8 state);
534 u16 db8500_prcmu_get_reset_code(void);
535 bool db8500_prcmu_is_ac_wake_requested(void);
536 int db8500_prcmu_set_arm_opp(u8 opp);
537 int db8500_prcmu_get_arm_opp(void);
538 int db8500_prcmu_set_ape_opp(u8 opp);
539 int db8500_prcmu_get_ape_opp(void);
540 int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
541 int db8500_prcmu_get_ddr_opp(void);
542
543 u32 db8500_prcmu_read(unsigned int reg);
544 void db8500_prcmu_write(unsigned int reg, u32 value);
545 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
546
547 #else
548
549 static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {}
550
551 static inline int prcmu_set_rc_a2p(enum romcode_write code)
552 {
553 return 0;
554 }
555
556 static inline enum romcode_read prcmu_get_rc_p2a(void)
557 {
558 return INIT;
559 }
560
561 static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
562 {
563 return AP_EXECUTE;
564 }
565
566 static inline bool prcmu_has_arm_maxopp(void)
567 {
568 return false;
569 }
570
571 static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
572 {
573 return NULL;
574 }
575
576 static inline int db8500_prcmu_set_ape_opp(u8 opp)
577 {
578 return 0;
579 }
580
581 static inline int db8500_prcmu_get_ape_opp(void)
582 {
583 return APE_100_OPP;
584 }
585
586 static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
587 {
588 return 0;
589 }
590
591 static inline int prcmu_release_usb_wakeup_state(void)
592 {
593 return 0;
594 }
595
596 static inline int db8500_prcmu_get_ddr_opp(void)
597 {
598 return DDR_100_OPP;
599 }
600
601 static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
602 struct prcmu_auto_pm_config *idle)
603 {
604 }
605
606 static inline bool prcmu_is_auto_pm_enabled(void)
607 {
608 return false;
609 }
610
611 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
612 {
613 return 0;
614 }
615
616 static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
617 {
618 return 0;
619 }
620
621 static inline int db8500_prcmu_config_hotdog(u8 threshold)
622 {
623 return 0;
624 }
625
626 static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
627 {
628 return 0;
629 }
630
631 static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
632 {
633 return 0;
634 }
635
636 static inline int db8500_prcmu_stop_temp_sense(void)
637 {
638 return 0;
639 }
640
641 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
642 {
643 return -ENOSYS;
644 }
645
646 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
647 {
648 return -ENOSYS;
649 }
650
651 static inline int prcmu_ac_wake_req(void)
652 {
653 return 0;
654 }
655
656 static inline void prcmu_ac_sleep_req(void) {}
657
658 static inline void db8500_prcmu_modem_reset(void) {}
659
660 static inline void db8500_prcmu_system_reset(u16 reset_code) {}
661
662 static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
663 bool keep_ap_pll)
664 {
665 return 0;
666 }
667
668 static inline u8 db8500_prcmu_get_power_state_result(void)
669 {
670 return 0;
671 }
672
673 static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
674
675 static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
676 {
677 return 0;
678 }
679
680 static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
681 {
682 return 0;
683 }
684
685 static inline int db8500_prcmu_set_display_clocks(void)
686 {
687 return 0;
688 }
689
690 static inline int db8500_prcmu_disable_dsipll(void)
691 {
692 return 0;
693 }
694
695 static inline int db8500_prcmu_enable_dsipll(void)
696 {
697 return 0;
698 }
699
700 static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
701 {
702 return 0;
703 }
704
705 static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
706
707 static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
708
709 static inline u16 db8500_prcmu_get_reset_code(void)
710 {
711 return 0;
712 }
713
714 static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
715 {
716 return 0;
717 }
718
719 static inline int db8500_prcmu_enable_a9wdog(u8 id)
720 {
721 return 0;
722 }
723
724 static inline int db8500_prcmu_disable_a9wdog(u8 id)
725 {
726 return 0;
727 }
728
729 static inline int db8500_prcmu_kick_a9wdog(u8 id)
730 {
731 return 0;
732 }
733
734 static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
735 {
736 return 0;
737 }
738
739 static inline bool db8500_prcmu_is_ac_wake_requested(void)
740 {
741 return 0;
742 }
743
744 static inline int db8500_prcmu_set_arm_opp(u8 opp)
745 {
746 return 0;
747 }
748
749 static inline int db8500_prcmu_get_arm_opp(void)
750 {
751 return 0;
752 }
753
754 static inline u32 db8500_prcmu_read(unsigned int reg)
755 {
756 return 0;
757 }
758
759 static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
760
761 static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
762 u32 value) {}
763
764 #endif
765
766 #endif