root/include/linux/mfd/lp87565.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Functions to access LP87565 power management chip.
   4  *
   5  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 
   8 #ifndef __LINUX_MFD_LP87565_H
   9 #define __LINUX_MFD_LP87565_H
  10 
  11 #include <linux/i2c.h>
  12 #include <linux/regulator/driver.h>
  13 #include <linux/regulator/machine.h>
  14 
  15 enum lp87565_device_type {
  16         LP87565_DEVICE_TYPE_UNKNOWN     = 0,
  17         LP87565_DEVICE_TYPE_LP87561_Q1,
  18         LP87565_DEVICE_TYPE_LP87565_Q1,
  19 };
  20 
  21 /* All register addresses */
  22 #define LP87565_REG_DEV_REV             0X00
  23 #define LP87565_REG_OTP_REV             0X01
  24 #define LP87565_REG_BUCK0_CTRL_1                0X02
  25 #define LP87565_REG_BUCK0_CTRL_2                0X03
  26 
  27 #define LP87565_REG_BUCK1_CTRL_1                0X04
  28 #define LP87565_REG_BUCK1_CTRL_2                0X05
  29 
  30 #define LP87565_REG_BUCK2_CTRL_1                0X06
  31 #define LP87565_REG_BUCK2_CTRL_2                0X07
  32 
  33 #define LP87565_REG_BUCK3_CTRL_1                0X08
  34 #define LP87565_REG_BUCK3_CTRL_2                0X09
  35 
  36 #define LP87565_REG_BUCK0_VOUT                  0X0A
  37 #define LP87565_REG_BUCK0_FLOOR_VOUT            0X0B
  38 
  39 #define LP87565_REG_BUCK1_VOUT                  0X0C
  40 #define LP87565_REG_BUCK1_FLOOR_VOUT            0X0D
  41 
  42 #define LP87565_REG_BUCK2_VOUT                  0X0E
  43 #define LP87565_REG_BUCK2_FLOOR_VOUT            0X0F
  44 
  45 #define LP87565_REG_BUCK3_VOUT                  0X10
  46 #define LP87565_REG_BUCK3_FLOOR_VOUT            0X11
  47 
  48 #define LP87565_REG_BUCK0_DELAY                 0X12
  49 #define LP87565_REG_BUCK1_DELAY                 0X13
  50 
  51 #define LP87565_REG_BUCK2_DELAY                 0X14
  52 #define LP87565_REG_BUCK3_DELAY                 0X15
  53 
  54 #define LP87565_REG_GPO2_DELAY                  0X16
  55 #define LP87565_REG_GPO3_DELAY                  0X17
  56 #define LP87565_REG_RESET                       0X18
  57 #define LP87565_REG_CONFIG                      0X19
  58 
  59 #define LP87565_REG_INT_TOP_1                   0X1A
  60 #define LP87565_REG_INT_TOP_2                   0X1B
  61 
  62 #define LP87565_REG_INT_BUCK_0_1                0X1C
  63 #define LP87565_REG_INT_BUCK_2_3                0X1D
  64 #define LP87565_REG_TOP_STAT                    0X1E
  65 #define LP87565_REG_BUCK_0_1_STAT               0X1F
  66 #define LP87565_REG_BUCK_2_3_STAT               0x20
  67 
  68 #define LP87565_REG_TOP_MASK_1                  0x21
  69 #define LP87565_REG_TOP_MASK_2                  0x22
  70 
  71 #define LP87565_REG_BUCK_0_1_MASK               0x23
  72 #define LP87565_REG_BUCK_2_3_MASK               0x24
  73 #define LP87565_REG_SEL_I_LOAD                  0x25
  74 
  75 #define LP87565_REG_I_LOAD_2                    0x26
  76 #define LP87565_REG_I_LOAD_1                    0x27
  77 
  78 #define LP87565_REG_PGOOD_CTRL1                 0x28
  79 #define LP87565_REG_PGOOD_CTRL2                 0x29
  80 #define LP87565_REG_PGOOD_FLT                   0x2A
  81 #define LP87565_REG_PLL_CTRL                    0x2B
  82 #define LP87565_REG_PIN_FUNCTION                0x2C
  83 #define LP87565_REG_GPIO_CONFIG                 0x2D
  84 #define LP87565_REG_GPIO_IN                     0x2E
  85 #define LP87565_REG_GPIO_OUT                    0x2F
  86 
  87 #define LP87565_REG_MAX                 LP87565_REG_GPIO_OUT
  88 
  89 /* Register field definitions */
  90 #define LP87565_DEV_REV_DEV_ID                  0xC0
  91 #define LP87565_DEV_REV_ALL_LAYER               0x30
  92 #define LP87565_DEV_REV_METAL_LAYER             0x0F
  93 
  94 #define LP87565_OTP_REV_OTP_ID                  0xFF
  95 
  96 #define LP87565_BUCK_CTRL_1_EN                  BIT(7)
  97 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL         BIT(6)
  98 #define LP87565_BUCK_CTRL_1_PIN_SELECT_EN       0x30
  99 
 100 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN       BIT(3)
 101 #define LP87565_BUCK_CTRL_1_RDIS_EN             BIT(2)
 102 #define LP87565_BUCK_CTRL_1_FPWM                BIT(1)
 103 /* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */
 104 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2         BIT(0)
 105 
 106 #define LP87565_BUCK_CTRL_2_ILIM                0x38
 107 #define LP87565_BUCK_CTRL_2_SLEW_RATE           0x07
 108 
 109 #define LP87565_BUCK_VSET                       0xFF
 110 #define LP87565_BUCK_FLOOR_VSET                 0xFF
 111 
 112 #define LP87565_BUCK_SHUTDOWN_DELAY             0xF0
 113 #define LP87565_BUCK_STARTUP_DELAY              0x0F
 114 
 115 #define LP87565_GPIO_SHUTDOWN_DELAY             0xF0
 116 #define LP87565_GPIO_STARTUP_DELAY              0x0F
 117 
 118 #define LP87565_RESET_SW_RESET                  BIT(0)
 119 
 120 #define LP87565_CONFIG_DOUBLE_DELAY             BIT(7)
 121 #define LP87565_CONFIG_CLKIN_PD                 BIT(6)
 122 #define LP87565_CONFIG_EN4_PD                   BIT(5)
 123 #define LP87565_CONFIG_EN3_PD                   BIT(4)
 124 #define LP87565_CONFIG_TDIE_WARN_LEVEL          BIT(3)
 125 #define LP87565_CONFIG_EN2_PD                   BIT(2)
 126 #define LP87565_CONFIG_EN1_PD                   BIT(1)
 127 
 128 #define LP87565_INT_GPIO                        BIT(7)
 129 #define LP87565_INT_BUCK23                      BIT(6)
 130 #define LP87565_INT_BUCK01                      BIT(5)
 131 #define LP87565_NO_SYNC_CLK                     BIT(4)
 132 #define LP87565_TDIE_SD                         BIT(3)
 133 #define LP87565_TDIE_WARN                       BIT(2)
 134 #define LP87565_INT_OVP                         BIT(1)
 135 #define LP87565_I_LOAD_READY                    BIT(0)
 136 
 137 #define LP87565_INT_TOP2_RESET_REG              BIT(0)
 138 
 139 #define LP87565_BUCK1_PG_INT                    BIT(6)
 140 #define LP87565_BUCK1_SC_INT                    BIT(5)
 141 #define LP87565_BUCK1_ILIM_INT                  BIT(4)
 142 #define LP87565_BUCK0_PG_INT                    BIT(2)
 143 #define LP87565_BUCK0_SC_INT                    BIT(1)
 144 #define LP87565_BUCK0_ILIM_INT                  BIT(0)
 145 
 146 #define LP87565_BUCK3_PG_INT                    BIT(6)
 147 #define LP87565_BUCK3_SC_INT                    BIT(5)
 148 #define LP87565_BUCK3_ILIM_INT                  BIT(4)
 149 #define LP87565_BUCK2_PG_INT                    BIT(2)
 150 #define LP87565_BUCK2_SC_INT                    BIT(1)
 151 #define LP87565_BUCK2_ILIM_INT                  BIT(0)
 152 
 153 #define LP87565_SYNC_CLK_STAT                   BIT(4)
 154 #define LP87565_TDIE_SD_STAT                    BIT(3)
 155 #define LP87565_TDIE_WARN_STAT                  BIT(2)
 156 #define LP87565_OVP_STAT                        BIT(1)
 157 
 158 #define LP87565_BUCK1_STAT                      BIT(7)
 159 #define LP87565_BUCK1_PG_STAT                   BIT(6)
 160 #define LP87565_BUCK1_ILIM_STAT                 BIT(4)
 161 #define LP87565_BUCK0_STAT                      BIT(3)
 162 #define LP87565_BUCK0_PG_STAT                   BIT(2)
 163 #define LP87565_BUCK0_ILIM_STAT                 BIT(0)
 164 
 165 #define LP87565_BUCK3_STAT                      BIT(7)
 166 #define LP87565_BUCK3_PG_STAT                   BIT(6)
 167 #define LP87565_BUCK3_ILIM_STAT                 BIT(4)
 168 #define LP87565_BUCK2_STAT                      BIT(3)
 169 #define LP87565_BUCK2_PG_STAT                   BIT(2)
 170 #define LP87565_BUCK2_ILIM_STAT                 BIT(0)
 171 
 172 #define LPL87565_GPIO_MASK                      BIT(7)
 173 #define LPL87565_SYNC_CLK_MASK                  BIT(4)
 174 #define LPL87565_TDIE_WARN_MASK                 BIT(2)
 175 #define LPL87565_I_LOAD_READY_MASK              BIT(0)
 176 
 177 #define LPL87565_RESET_REG_MASK                 BIT(0)
 178 
 179 #define LPL87565_BUCK1_PG_MASK                  BIT(6)
 180 #define LPL87565_BUCK1_ILIM_MASK                BIT(4)
 181 #define LPL87565_BUCK0_PG_MASK                  BIT(2)
 182 #define LPL87565_BUCK0_ILIM_MASK                BIT(0)
 183 
 184 #define LPL87565_BUCK3_PG_MASK                  BIT(6)
 185 #define LPL87565_BUCK3_ILIM_MASK                BIT(4)
 186 #define LPL87565_BUCK2_PG_MASK                  BIT(2)
 187 #define LPL87565_BUCK2_ILIM_MASK                BIT(0)
 188 
 189 #define LP87565_LOAD_CURRENT_BUCK_SELECT        0x3
 190 
 191 #define LP87565_I_LOAD2_BUCK_LOAD_CURRENT       0x3
 192 #define LP87565_I_LOAD1_BUCK_LOAD_CURRENT       0xFF
 193 
 194 #define LP87565_PG3_SEL                         0xC0
 195 #define LP87565_PG2_SEL                         0x30
 196 #define LP87565_PG1_SEL                         0x0C
 197 #define LP87565_PG0_SEL                         0x03
 198 
 199 #define LP87565_HALF_DAY                        BIT(7)
 200 #define LP87565_EN_PG0_NINT                     BIT(6)
 201 #define LP87565_PGOOD_SET_DELAY                 BIT(5)
 202 #define LP87565_EN_PGFLT_STAT                   BIT(4)
 203 #define LP87565_PGOOD_WINDOW                    BIT(2)
 204 #define LP87565_PGOOD_OD                        BIT(1)
 205 #define LP87565_PGOOD_POL                       BIT(0)
 206 
 207 #define LP87565_PG3_FLT                         BIT(3)
 208 #define LP87565_PG2_FLT                         BIT(2)
 209 #define LP87565_PG1_FLT                         BIT(1)
 210 #define LP87565_PG0_FLT                         BIT(0)
 211 
 212 #define LP87565_PLL_MODE                        0xC0
 213 #define LP87565_EXT_CLK_FREQ                    0x1F
 214 
 215 #define LP87565_EN_SPREAD_SPEC                  BIT(7)
 216 #define LP87565_EN_PIN_CTRL_GPIO3               BIT(6)
 217 #define LP87565_EN_PIN_SELECT_GPIO3             BIT(5)
 218 #define LP87565_EN_PIN_CTRL_GPIO2               BIT(4)
 219 #define LP87565_EN_PIN_SELECT_GPIO2             BIT(3)
 220 #define LP87565_GPIO3_SEL                       BIT(2)
 221 #define LP87565_GPIO2_SEL                       BIT(1)
 222 #define LP87565_GPIO1_SEL                       BIT(0)
 223 
 224 #define LP87565_GOIO3_OD                        BIT(6)
 225 #define LP87565_GOIO2_OD                        BIT(5)
 226 #define LP87565_GOIO1_OD                        BIT(4)
 227 #define LP87565_GOIO3_DIR                       BIT(2)
 228 #define LP87565_GOIO2_DIR                       BIT(1)
 229 #define LP87565_GOIO1_DIR                       BIT(0)
 230 
 231 #define LP87565_GOIO3_IN                        BIT(2)
 232 #define LP87565_GOIO2_IN                        BIT(1)
 233 #define LP87565_GOIO1_IN                        BIT(0)
 234 
 235 #define LP87565_GOIO3_OUT                       BIT(2)
 236 #define LP87565_GOIO2_OUT                       BIT(1)
 237 #define LP87565_GOIO1_OUT                       BIT(0)
 238 
 239 /* Number of step-down converters available */
 240 #define LP87565_NUM_BUCK                6
 241 
 242 enum LP87565_regulator_id {
 243         /* BUCK's */
 244         LP87565_BUCK_0,
 245         LP87565_BUCK_1,
 246         LP87565_BUCK_2,
 247         LP87565_BUCK_3,
 248         LP87565_BUCK_10,
 249         LP87565_BUCK_23,
 250         LP87565_BUCK_3210,
 251 };
 252 
 253 /**
 254  * struct LP87565 - state holder for the LP87565 driver
 255  * @dev: struct device pointer for MFD device
 256  * @rev: revision of the LP87565
 257  * @dev_type: The device type for example lp87565-q1
 258  * @lock: lock guarding the data structure
 259  * @regmap: register map of the LP87565 PMIC
 260  *
 261  * Device data may be used to access the LP87565 chip
 262  */
 263 struct lp87565 {
 264         struct device *dev;
 265         u8 rev;
 266         u8 dev_type;
 267         struct regmap *regmap;
 268 };
 269 #endif /* __LINUX_MFD_LP87565_H */