root/include/linux/mfd/samsung/s5m8767.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd
   4  *              http://www.samsung.com
   5  */
   6 
   7 #ifndef __LINUX_MFD_S5M8767_H
   8 #define __LINUX_MFD_S5M8767_H
   9 
  10 /* S5M8767 registers */
  11 enum s5m8767_reg {
  12         S5M8767_REG_ID,
  13         S5M8767_REG_INT1,
  14         S5M8767_REG_INT2,
  15         S5M8767_REG_INT3,
  16         S5M8767_REG_INT1M,
  17         S5M8767_REG_INT2M,
  18         S5M8767_REG_INT3M,
  19         S5M8767_REG_STATUS1,
  20         S5M8767_REG_STATUS2,
  21         S5M8767_REG_STATUS3,
  22         S5M8767_REG_CTRL1,
  23         S5M8767_REG_CTRL2,
  24         S5M8767_REG_LOWBAT1,
  25         S5M8767_REG_LOWBAT2,
  26         S5M8767_REG_BUCHG,
  27         S5M8767_REG_DVSRAMP,
  28         S5M8767_REG_DVSTIMER2 = 0x10,
  29         S5M8767_REG_DVSTIMER3,
  30         S5M8767_REG_DVSTIMER4,
  31         S5M8767_REG_LDO1,
  32         S5M8767_REG_LDO2,
  33         S5M8767_REG_LDO3,
  34         S5M8767_REG_LDO4,
  35         S5M8767_REG_LDO5,
  36         S5M8767_REG_LDO6,
  37         S5M8767_REG_LDO7,
  38         S5M8767_REG_LDO8,
  39         S5M8767_REG_LDO9,
  40         S5M8767_REG_LDO10,
  41         S5M8767_REG_LDO11,
  42         S5M8767_REG_LDO12,
  43         S5M8767_REG_LDO13,
  44         S5M8767_REG_LDO14 = 0x20,
  45         S5M8767_REG_LDO15,
  46         S5M8767_REG_LDO16,
  47         S5M8767_REG_LDO17,
  48         S5M8767_REG_LDO18,
  49         S5M8767_REG_LDO19,
  50         S5M8767_REG_LDO20,
  51         S5M8767_REG_LDO21,
  52         S5M8767_REG_LDO22,
  53         S5M8767_REG_LDO23,
  54         S5M8767_REG_LDO24,
  55         S5M8767_REG_LDO25,
  56         S5M8767_REG_LDO26,
  57         S5M8767_REG_LDO27,
  58         S5M8767_REG_LDO28,
  59         S5M8767_REG_UVLO = 0x31,
  60         S5M8767_REG_BUCK1CTRL1,
  61         S5M8767_REG_BUCK1CTRL2,
  62         S5M8767_REG_BUCK2CTRL,
  63         S5M8767_REG_BUCK2DVS1,
  64         S5M8767_REG_BUCK2DVS2,
  65         S5M8767_REG_BUCK2DVS3,
  66         S5M8767_REG_BUCK2DVS4,
  67         S5M8767_REG_BUCK2DVS5,
  68         S5M8767_REG_BUCK2DVS6,
  69         S5M8767_REG_BUCK2DVS7,
  70         S5M8767_REG_BUCK2DVS8,
  71         S5M8767_REG_BUCK3CTRL,
  72         S5M8767_REG_BUCK3DVS1,
  73         S5M8767_REG_BUCK3DVS2,
  74         S5M8767_REG_BUCK3DVS3,
  75         S5M8767_REG_BUCK3DVS4,
  76         S5M8767_REG_BUCK3DVS5,
  77         S5M8767_REG_BUCK3DVS6,
  78         S5M8767_REG_BUCK3DVS7,
  79         S5M8767_REG_BUCK3DVS8,
  80         S5M8767_REG_BUCK4CTRL,
  81         S5M8767_REG_BUCK4DVS1,
  82         S5M8767_REG_BUCK4DVS2,
  83         S5M8767_REG_BUCK4DVS3,
  84         S5M8767_REG_BUCK4DVS4,
  85         S5M8767_REG_BUCK4DVS5,
  86         S5M8767_REG_BUCK4DVS6,
  87         S5M8767_REG_BUCK4DVS7,
  88         S5M8767_REG_BUCK4DVS8,
  89         S5M8767_REG_BUCK5CTRL1,
  90         S5M8767_REG_BUCK5CTRL2,
  91         S5M8767_REG_BUCK5CTRL3,
  92         S5M8767_REG_BUCK5CTRL4,
  93         S5M8767_REG_BUCK5CTRL5,
  94         S5M8767_REG_BUCK6CTRL1,
  95         S5M8767_REG_BUCK6CTRL2,
  96         S5M8767_REG_BUCK7CTRL1,
  97         S5M8767_REG_BUCK7CTRL2,
  98         S5M8767_REG_BUCK8CTRL1,
  99         S5M8767_REG_BUCK8CTRL2,
 100         S5M8767_REG_BUCK9CTRL1,
 101         S5M8767_REG_BUCK9CTRL2,
 102         S5M8767_REG_LDO1CTRL,
 103         S5M8767_REG_LDO2_1CTRL,
 104         S5M8767_REG_LDO2_2CTRL,
 105         S5M8767_REG_LDO2_3CTRL,
 106         S5M8767_REG_LDO2_4CTRL,
 107         S5M8767_REG_LDO3CTRL,
 108         S5M8767_REG_LDO4CTRL,
 109         S5M8767_REG_LDO5CTRL,
 110         S5M8767_REG_LDO6CTRL,
 111         S5M8767_REG_LDO7CTRL,
 112         S5M8767_REG_LDO8CTRL,
 113         S5M8767_REG_LDO9CTRL,
 114         S5M8767_REG_LDO10CTRL,
 115         S5M8767_REG_LDO11CTRL,
 116         S5M8767_REG_LDO12CTRL,
 117         S5M8767_REG_LDO13CTRL,
 118         S5M8767_REG_LDO14CTRL,
 119         S5M8767_REG_LDO15CTRL,
 120         S5M8767_REG_LDO16CTRL,
 121         S5M8767_REG_LDO17CTRL,
 122         S5M8767_REG_LDO18CTRL,
 123         S5M8767_REG_LDO19CTRL,
 124         S5M8767_REG_LDO20CTRL,
 125         S5M8767_REG_LDO21CTRL,
 126         S5M8767_REG_LDO22CTRL,
 127         S5M8767_REG_LDO23CTRL,
 128         S5M8767_REG_LDO24CTRL,
 129         S5M8767_REG_LDO25CTRL,
 130         S5M8767_REG_LDO26CTRL,
 131         S5M8767_REG_LDO27CTRL,
 132         S5M8767_REG_LDO28CTRL,
 133 };
 134 
 135 /* S5M8767 regulator ids */
 136 enum s5m8767_regulators {
 137         S5M8767_LDO1,
 138         S5M8767_LDO2,
 139         S5M8767_LDO3,
 140         S5M8767_LDO4,
 141         S5M8767_LDO5,
 142         S5M8767_LDO6,
 143         S5M8767_LDO7,
 144         S5M8767_LDO8,
 145         S5M8767_LDO9,
 146         S5M8767_LDO10,
 147         S5M8767_LDO11,
 148         S5M8767_LDO12,
 149         S5M8767_LDO13,
 150         S5M8767_LDO14,
 151         S5M8767_LDO15,
 152         S5M8767_LDO16,
 153         S5M8767_LDO17,
 154         S5M8767_LDO18,
 155         S5M8767_LDO19,
 156         S5M8767_LDO20,
 157         S5M8767_LDO21,
 158         S5M8767_LDO22,
 159         S5M8767_LDO23,
 160         S5M8767_LDO24,
 161         S5M8767_LDO25,
 162         S5M8767_LDO26,
 163         S5M8767_LDO27,
 164         S5M8767_LDO28,
 165         S5M8767_BUCK1,
 166         S5M8767_BUCK2,
 167         S5M8767_BUCK3,
 168         S5M8767_BUCK4,
 169         S5M8767_BUCK5,
 170         S5M8767_BUCK6,
 171         S5M8767_BUCK7,
 172         S5M8767_BUCK8,
 173         S5M8767_BUCK9,
 174         S5M8767_AP_EN32KHZ,
 175         S5M8767_CP_EN32KHZ,
 176 
 177         S5M8767_REG_MAX,
 178 };
 179 
 180 /* LDO_EN/BUCK_EN field in registers */
 181 #define S5M8767_ENCTRL_SHIFT            6
 182 #define S5M8767_ENCTRL_MASK             (0x3 << S5M8767_ENCTRL_SHIFT)
 183 
 184 /*
 185  * LDO_EN/BUCK_EN register value for controlling this Buck or LDO
 186  * by GPIO (PWREN, BUCKEN).
 187  */
 188 #define S5M8767_ENCTRL_USE_GPIO         0x1
 189 
 190 /*
 191  * Values for BUCK_RAMP field in DVS_RAMP register, matching raw values
 192  * in mV/us.
 193  */
 194 enum s5m8767_dvs_buck_ramp_values {
 195         S5M8767_DVS_BUCK_RAMP_5         = 0x4,
 196         S5M8767_DVS_BUCK_RAMP_10        = 0x9,
 197         S5M8767_DVS_BUCK_RAMP_12_5      = 0xb,
 198         S5M8767_DVS_BUCK_RAMP_25        = 0xd,
 199         S5M8767_DVS_BUCK_RAMP_50        = 0xe,
 200         S5M8767_DVS_BUCK_RAMP_100       = 0xf,
 201 };
 202 #define S5M8767_DVS_BUCK_RAMP_SHIFT     4
 203 #define S5M8767_DVS_BUCK_RAMP_MASK      (0xf << S5M8767_DVS_BUCK_RAMP_SHIFT)
 204 
 205 #endif /* __LINUX_MFD_S5M8767_H */