root/include/linux/mfd/wm831x/irq.h

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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
   4  *
   5  * Copyright 2009 Wolfson Microelectronics PLC.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  */
   9 
  10 #ifndef __MFD_WM831X_IRQ_H__
  11 #define __MFD_WM831X_IRQ_H__
  12 
  13 /* Interrupt number assignments within Linux */
  14 #define WM831X_IRQ_TEMP_THW 0
  15 #define WM831X_IRQ_GPIO_1   1
  16 #define WM831X_IRQ_GPIO_2   2
  17 #define WM831X_IRQ_GPIO_3   3
  18 #define WM831X_IRQ_GPIO_4   4
  19 #define WM831X_IRQ_GPIO_5   5
  20 #define WM831X_IRQ_GPIO_6   6
  21 #define WM831X_IRQ_GPIO_7   7
  22 #define WM831X_IRQ_GPIO_8   8
  23 #define WM831X_IRQ_GPIO_9   9
  24 #define WM831X_IRQ_GPIO_10  10
  25 #define WM831X_IRQ_GPIO_11  11
  26 #define WM831X_IRQ_GPIO_12  12
  27 #define WM831X_IRQ_GPIO_13  13
  28 #define WM831X_IRQ_GPIO_14  14
  29 #define WM831X_IRQ_GPIO_15  15
  30 #define WM831X_IRQ_GPIO_16  16
  31 #define WM831X_IRQ_ON           17
  32 #define WM831X_IRQ_PPM_SYSLO    18
  33 #define WM831X_IRQ_PPM_PWR_SRC  19
  34 #define WM831X_IRQ_PPM_USB_CURR 20
  35 #define WM831X_IRQ_WDOG_TO      21
  36 #define WM831X_IRQ_RTC_PER      22
  37 #define WM831X_IRQ_RTC_ALM      23
  38 #define WM831X_IRQ_CHG_BATT_HOT  24
  39 #define WM831X_IRQ_CHG_BATT_COLD 25
  40 #define WM831X_IRQ_CHG_BATT_FAIL 26
  41 #define WM831X_IRQ_CHG_OV        27
  42 #define WM831X_IRQ_CHG_END       29
  43 #define WM831X_IRQ_CHG_TO        30
  44 #define WM831X_IRQ_CHG_MODE      31
  45 #define WM831X_IRQ_CHG_START     32
  46 #define WM831X_IRQ_TCHDATA       33
  47 #define WM831X_IRQ_TCHPD         34
  48 #define WM831X_IRQ_AUXADC_DATA   35
  49 #define WM831X_IRQ_AUXADC_DCOMP1 36
  50 #define WM831X_IRQ_AUXADC_DCOMP2 37
  51 #define WM831X_IRQ_AUXADC_DCOMP3 38
  52 #define WM831X_IRQ_AUXADC_DCOMP4 39
  53 #define WM831X_IRQ_CS1           40
  54 #define WM831X_IRQ_CS2           41
  55 #define WM831X_IRQ_HC_DC1        42
  56 #define WM831X_IRQ_HC_DC2        43
  57 #define WM831X_IRQ_UV_LDO1       44
  58 #define WM831X_IRQ_UV_LDO2       45
  59 #define WM831X_IRQ_UV_LDO3       46
  60 #define WM831X_IRQ_UV_LDO4       47
  61 #define WM831X_IRQ_UV_LDO5       48
  62 #define WM831X_IRQ_UV_LDO6       49
  63 #define WM831X_IRQ_UV_LDO7       50
  64 #define WM831X_IRQ_UV_LDO8       51
  65 #define WM831X_IRQ_UV_LDO9       52
  66 #define WM831X_IRQ_UV_LDO10      53
  67 #define WM831X_IRQ_UV_DC1        54
  68 #define WM831X_IRQ_UV_DC2        55
  69 #define WM831X_IRQ_UV_DC3        56
  70 #define WM831X_IRQ_UV_DC4        57
  71 
  72 #define WM831X_NUM_IRQS     58
  73 
  74 /*
  75  * R16400 (0x4010) - System Interrupts
  76  */
  77 #define WM831X_PS_INT                           0x8000  /* PS_INT */
  78 #define WM831X_PS_INT_MASK                      0x8000  /* PS_INT */
  79 #define WM831X_PS_INT_SHIFT                         15  /* PS_INT */
  80 #define WM831X_PS_INT_WIDTH                          1  /* PS_INT */
  81 #define WM831X_TEMP_INT                         0x4000  /* TEMP_INT */
  82 #define WM831X_TEMP_INT_MASK                    0x4000  /* TEMP_INT */
  83 #define WM831X_TEMP_INT_SHIFT                       14  /* TEMP_INT */
  84 #define WM831X_TEMP_INT_WIDTH                        1  /* TEMP_INT */
  85 #define WM831X_GP_INT                           0x2000  /* GP_INT */
  86 #define WM831X_GP_INT_MASK                      0x2000  /* GP_INT */
  87 #define WM831X_GP_INT_SHIFT                         13  /* GP_INT */
  88 #define WM831X_GP_INT_WIDTH                          1  /* GP_INT */
  89 #define WM831X_ON_PIN_INT                       0x1000  /* ON_PIN_INT */
  90 #define WM831X_ON_PIN_INT_MASK                  0x1000  /* ON_PIN_INT */
  91 #define WM831X_ON_PIN_INT_SHIFT                     12  /* ON_PIN_INT */
  92 #define WM831X_ON_PIN_INT_WIDTH                      1  /* ON_PIN_INT */
  93 #define WM831X_WDOG_INT                         0x0800  /* WDOG_INT */
  94 #define WM831X_WDOG_INT_MASK                    0x0800  /* WDOG_INT */
  95 #define WM831X_WDOG_INT_SHIFT                       11  /* WDOG_INT */
  96 #define WM831X_WDOG_INT_WIDTH                        1  /* WDOG_INT */
  97 #define WM831X_TCHDATA_INT                      0x0400  /* TCHDATA_INT */
  98 #define WM831X_TCHDATA_INT_MASK                 0x0400  /* TCHDATA_INT */
  99 #define WM831X_TCHDATA_INT_SHIFT                    10  /* TCHDATA_INT */
 100 #define WM831X_TCHDATA_INT_WIDTH                     1  /* TCHDATA_INT */
 101 #define WM831X_TCHPD_INT                        0x0200  /* TCHPD_INT */
 102 #define WM831X_TCHPD_INT_MASK                   0x0200  /* TCHPD_INT */
 103 #define WM831X_TCHPD_INT_SHIFT                       9  /* TCHPD_INT */
 104 #define WM831X_TCHPD_INT_WIDTH                       1  /* TCHPD_INT */
 105 #define WM831X_AUXADC_INT                       0x0100  /* AUXADC_INT */
 106 #define WM831X_AUXADC_INT_MASK                  0x0100  /* AUXADC_INT */
 107 #define WM831X_AUXADC_INT_SHIFT                      8  /* AUXADC_INT */
 108 #define WM831X_AUXADC_INT_WIDTH                      1  /* AUXADC_INT */
 109 #define WM831X_PPM_INT                          0x0080  /* PPM_INT */
 110 #define WM831X_PPM_INT_MASK                     0x0080  /* PPM_INT */
 111 #define WM831X_PPM_INT_SHIFT                         7  /* PPM_INT */
 112 #define WM831X_PPM_INT_WIDTH                         1  /* PPM_INT */
 113 #define WM831X_CS_INT                           0x0040  /* CS_INT */
 114 #define WM831X_CS_INT_MASK                      0x0040  /* CS_INT */
 115 #define WM831X_CS_INT_SHIFT                          6  /* CS_INT */
 116 #define WM831X_CS_INT_WIDTH                          1  /* CS_INT */
 117 #define WM831X_RTC_INT                          0x0020  /* RTC_INT */
 118 #define WM831X_RTC_INT_MASK                     0x0020  /* RTC_INT */
 119 #define WM831X_RTC_INT_SHIFT                         5  /* RTC_INT */
 120 #define WM831X_RTC_INT_WIDTH                         1  /* RTC_INT */
 121 #define WM831X_OTP_INT                          0x0010  /* OTP_INT */
 122 #define WM831X_OTP_INT_MASK                     0x0010  /* OTP_INT */
 123 #define WM831X_OTP_INT_SHIFT                         4  /* OTP_INT */
 124 #define WM831X_OTP_INT_WIDTH                         1  /* OTP_INT */
 125 #define WM831X_CHILD_INT                        0x0008  /* CHILD_INT */
 126 #define WM831X_CHILD_INT_MASK                   0x0008  /* CHILD_INT */
 127 #define WM831X_CHILD_INT_SHIFT                       3  /* CHILD_INT */
 128 #define WM831X_CHILD_INT_WIDTH                       1  /* CHILD_INT */
 129 #define WM831X_CHG_INT                          0x0004  /* CHG_INT */
 130 #define WM831X_CHG_INT_MASK                     0x0004  /* CHG_INT */
 131 #define WM831X_CHG_INT_SHIFT                         2  /* CHG_INT */
 132 #define WM831X_CHG_INT_WIDTH                         1  /* CHG_INT */
 133 #define WM831X_HC_INT                           0x0002  /* HC_INT */
 134 #define WM831X_HC_INT_MASK                      0x0002  /* HC_INT */
 135 #define WM831X_HC_INT_SHIFT                          1  /* HC_INT */
 136 #define WM831X_HC_INT_WIDTH                          1  /* HC_INT */
 137 #define WM831X_UV_INT                           0x0001  /* UV_INT */
 138 #define WM831X_UV_INT_MASK                      0x0001  /* UV_INT */
 139 #define WM831X_UV_INT_SHIFT                          0  /* UV_INT */
 140 #define WM831X_UV_INT_WIDTH                          1  /* UV_INT */
 141 
 142 /*
 143  * R16401 (0x4011) - Interrupt Status 1
 144  */
 145 #define WM831X_PPM_SYSLO_EINT                   0x8000  /* PPM_SYSLO_EINT */
 146 #define WM831X_PPM_SYSLO_EINT_MASK              0x8000  /* PPM_SYSLO_EINT */
 147 #define WM831X_PPM_SYSLO_EINT_SHIFT                 15  /* PPM_SYSLO_EINT */
 148 #define WM831X_PPM_SYSLO_EINT_WIDTH                  1  /* PPM_SYSLO_EINT */
 149 #define WM831X_PPM_PWR_SRC_EINT                 0x4000  /* PPM_PWR_SRC_EINT */
 150 #define WM831X_PPM_PWR_SRC_EINT_MASK            0x4000  /* PPM_PWR_SRC_EINT */
 151 #define WM831X_PPM_PWR_SRC_EINT_SHIFT               14  /* PPM_PWR_SRC_EINT */
 152 #define WM831X_PPM_PWR_SRC_EINT_WIDTH                1  /* PPM_PWR_SRC_EINT */
 153 #define WM831X_PPM_USB_CURR_EINT                0x2000  /* PPM_USB_CURR_EINT */
 154 #define WM831X_PPM_USB_CURR_EINT_MASK           0x2000  /* PPM_USB_CURR_EINT */
 155 #define WM831X_PPM_USB_CURR_EINT_SHIFT              13  /* PPM_USB_CURR_EINT */
 156 #define WM831X_PPM_USB_CURR_EINT_WIDTH               1  /* PPM_USB_CURR_EINT */
 157 #define WM831X_ON_PIN_EINT                      0x1000  /* ON_PIN_EINT */
 158 #define WM831X_ON_PIN_EINT_MASK                 0x1000  /* ON_PIN_EINT */
 159 #define WM831X_ON_PIN_EINT_SHIFT                    12  /* ON_PIN_EINT */
 160 #define WM831X_ON_PIN_EINT_WIDTH                     1  /* ON_PIN_EINT */
 161 #define WM831X_WDOG_TO_EINT                     0x0800  /* WDOG_TO_EINT */
 162 #define WM831X_WDOG_TO_EINT_MASK                0x0800  /* WDOG_TO_EINT */
 163 #define WM831X_WDOG_TO_EINT_SHIFT                   11  /* WDOG_TO_EINT */
 164 #define WM831X_WDOG_TO_EINT_WIDTH                    1  /* WDOG_TO_EINT */
 165 #define WM831X_TCHDATA_EINT                     0x0400  /* TCHDATA_EINT */
 166 #define WM831X_TCHDATA_EINT_MASK                0x0400  /* TCHDATA_EINT */
 167 #define WM831X_TCHDATA_EINT_SHIFT                   10  /* TCHDATA_EINT */
 168 #define WM831X_TCHDATA_EINT_WIDTH                    1  /* TCHDATA_EINT */
 169 #define WM831X_TCHPD_EINT                       0x0200  /* TCHPD_EINT */
 170 #define WM831X_TCHPD_EINT_MASK                  0x0200  /* TCHPD_EINT */
 171 #define WM831X_TCHPD_EINT_SHIFT                      9  /* TCHPD_EINT */
 172 #define WM831X_TCHPD_EINT_WIDTH                      1  /* TCHPD_EINT */
 173 #define WM831X_AUXADC_DATA_EINT                 0x0100  /* AUXADC_DATA_EINT */
 174 #define WM831X_AUXADC_DATA_EINT_MASK            0x0100  /* AUXADC_DATA_EINT */
 175 #define WM831X_AUXADC_DATA_EINT_SHIFT                8  /* AUXADC_DATA_EINT */
 176 #define WM831X_AUXADC_DATA_EINT_WIDTH                1  /* AUXADC_DATA_EINT */
 177 #define WM831X_AUXADC_DCOMP4_EINT               0x0080  /* AUXADC_DCOMP4_EINT */
 178 #define WM831X_AUXADC_DCOMP4_EINT_MASK          0x0080  /* AUXADC_DCOMP4_EINT */
 179 #define WM831X_AUXADC_DCOMP4_EINT_SHIFT              7  /* AUXADC_DCOMP4_EINT */
 180 #define WM831X_AUXADC_DCOMP4_EINT_WIDTH              1  /* AUXADC_DCOMP4_EINT */
 181 #define WM831X_AUXADC_DCOMP3_EINT               0x0040  /* AUXADC_DCOMP3_EINT */
 182 #define WM831X_AUXADC_DCOMP3_EINT_MASK          0x0040  /* AUXADC_DCOMP3_EINT */
 183 #define WM831X_AUXADC_DCOMP3_EINT_SHIFT              6  /* AUXADC_DCOMP3_EINT */
 184 #define WM831X_AUXADC_DCOMP3_EINT_WIDTH              1  /* AUXADC_DCOMP3_EINT */
 185 #define WM831X_AUXADC_DCOMP2_EINT               0x0020  /* AUXADC_DCOMP2_EINT */
 186 #define WM831X_AUXADC_DCOMP2_EINT_MASK          0x0020  /* AUXADC_DCOMP2_EINT */
 187 #define WM831X_AUXADC_DCOMP2_EINT_SHIFT              5  /* AUXADC_DCOMP2_EINT */
 188 #define WM831X_AUXADC_DCOMP2_EINT_WIDTH              1  /* AUXADC_DCOMP2_EINT */
 189 #define WM831X_AUXADC_DCOMP1_EINT               0x0010  /* AUXADC_DCOMP1_EINT */
 190 #define WM831X_AUXADC_DCOMP1_EINT_MASK          0x0010  /* AUXADC_DCOMP1_EINT */
 191 #define WM831X_AUXADC_DCOMP1_EINT_SHIFT              4  /* AUXADC_DCOMP1_EINT */
 192 #define WM831X_AUXADC_DCOMP1_EINT_WIDTH              1  /* AUXADC_DCOMP1_EINT */
 193 #define WM831X_RTC_PER_EINT                     0x0008  /* RTC_PER_EINT */
 194 #define WM831X_RTC_PER_EINT_MASK                0x0008  /* RTC_PER_EINT */
 195 #define WM831X_RTC_PER_EINT_SHIFT                    3  /* RTC_PER_EINT */
 196 #define WM831X_RTC_PER_EINT_WIDTH                    1  /* RTC_PER_EINT */
 197 #define WM831X_RTC_ALM_EINT                     0x0004  /* RTC_ALM_EINT */
 198 #define WM831X_RTC_ALM_EINT_MASK                0x0004  /* RTC_ALM_EINT */
 199 #define WM831X_RTC_ALM_EINT_SHIFT                    2  /* RTC_ALM_EINT */
 200 #define WM831X_RTC_ALM_EINT_WIDTH                    1  /* RTC_ALM_EINT */
 201 #define WM831X_TEMP_THW_EINT                    0x0002  /* TEMP_THW_EINT */
 202 #define WM831X_TEMP_THW_EINT_MASK               0x0002  /* TEMP_THW_EINT */
 203 #define WM831X_TEMP_THW_EINT_SHIFT                   1  /* TEMP_THW_EINT */
 204 #define WM831X_TEMP_THW_EINT_WIDTH                   1  /* TEMP_THW_EINT */
 205 
 206 /*
 207  * R16402 (0x4012) - Interrupt Status 2
 208  */
 209 #define WM831X_CHG_BATT_HOT_EINT                0x8000  /* CHG_BATT_HOT_EINT */
 210 #define WM831X_CHG_BATT_HOT_EINT_MASK           0x8000  /* CHG_BATT_HOT_EINT */
 211 #define WM831X_CHG_BATT_HOT_EINT_SHIFT              15  /* CHG_BATT_HOT_EINT */
 212 #define WM831X_CHG_BATT_HOT_EINT_WIDTH               1  /* CHG_BATT_HOT_EINT */
 213 #define WM831X_CHG_BATT_COLD_EINT               0x4000  /* CHG_BATT_COLD_EINT */
 214 #define WM831X_CHG_BATT_COLD_EINT_MASK          0x4000  /* CHG_BATT_COLD_EINT */
 215 #define WM831X_CHG_BATT_COLD_EINT_SHIFT             14  /* CHG_BATT_COLD_EINT */
 216 #define WM831X_CHG_BATT_COLD_EINT_WIDTH              1  /* CHG_BATT_COLD_EINT */
 217 #define WM831X_CHG_BATT_FAIL_EINT               0x2000  /* CHG_BATT_FAIL_EINT */
 218 #define WM831X_CHG_BATT_FAIL_EINT_MASK          0x2000  /* CHG_BATT_FAIL_EINT */
 219 #define WM831X_CHG_BATT_FAIL_EINT_SHIFT             13  /* CHG_BATT_FAIL_EINT */
 220 #define WM831X_CHG_BATT_FAIL_EINT_WIDTH              1  /* CHG_BATT_FAIL_EINT */
 221 #define WM831X_CHG_OV_EINT                      0x1000  /* CHG_OV_EINT */
 222 #define WM831X_CHG_OV_EINT_MASK                 0x1000  /* CHG_OV_EINT */
 223 #define WM831X_CHG_OV_EINT_SHIFT                    12  /* CHG_OV_EINT */
 224 #define WM831X_CHG_OV_EINT_WIDTH                     1  /* CHG_OV_EINT */
 225 #define WM831X_CHG_END_EINT                     0x0800  /* CHG_END_EINT */
 226 #define WM831X_CHG_END_EINT_MASK                0x0800  /* CHG_END_EINT */
 227 #define WM831X_CHG_END_EINT_SHIFT                   11  /* CHG_END_EINT */
 228 #define WM831X_CHG_END_EINT_WIDTH                    1  /* CHG_END_EINT */
 229 #define WM831X_CHG_TO_EINT                      0x0400  /* CHG_TO_EINT */
 230 #define WM831X_CHG_TO_EINT_MASK                 0x0400  /* CHG_TO_EINT */
 231 #define WM831X_CHG_TO_EINT_SHIFT                    10  /* CHG_TO_EINT */
 232 #define WM831X_CHG_TO_EINT_WIDTH                     1  /* CHG_TO_EINT */
 233 #define WM831X_CHG_MODE_EINT                    0x0200  /* CHG_MODE_EINT */
 234 #define WM831X_CHG_MODE_EINT_MASK               0x0200  /* CHG_MODE_EINT */
 235 #define WM831X_CHG_MODE_EINT_SHIFT                   9  /* CHG_MODE_EINT */
 236 #define WM831X_CHG_MODE_EINT_WIDTH                   1  /* CHG_MODE_EINT */
 237 #define WM831X_CHG_START_EINT                   0x0100  /* CHG_START_EINT */
 238 #define WM831X_CHG_START_EINT_MASK              0x0100  /* CHG_START_EINT */
 239 #define WM831X_CHG_START_EINT_SHIFT                  8  /* CHG_START_EINT */
 240 #define WM831X_CHG_START_EINT_WIDTH                  1  /* CHG_START_EINT */
 241 #define WM831X_CS2_EINT                         0x0080  /* CS2_EINT */
 242 #define WM831X_CS2_EINT_MASK                    0x0080  /* CS2_EINT */
 243 #define WM831X_CS2_EINT_SHIFT                        7  /* CS2_EINT */
 244 #define WM831X_CS2_EINT_WIDTH                        1  /* CS2_EINT */
 245 #define WM831X_CS1_EINT                         0x0040  /* CS1_EINT */
 246 #define WM831X_CS1_EINT_MASK                    0x0040  /* CS1_EINT */
 247 #define WM831X_CS1_EINT_SHIFT                        6  /* CS1_EINT */
 248 #define WM831X_CS1_EINT_WIDTH                        1  /* CS1_EINT */
 249 #define WM831X_OTP_CMD_END_EINT                 0x0020  /* OTP_CMD_END_EINT */
 250 #define WM831X_OTP_CMD_END_EINT_MASK            0x0020  /* OTP_CMD_END_EINT */
 251 #define WM831X_OTP_CMD_END_EINT_SHIFT                5  /* OTP_CMD_END_EINT */
 252 #define WM831X_OTP_CMD_END_EINT_WIDTH                1  /* OTP_CMD_END_EINT */
 253 #define WM831X_OTP_ERR_EINT                     0x0010  /* OTP_ERR_EINT */
 254 #define WM831X_OTP_ERR_EINT_MASK                0x0010  /* OTP_ERR_EINT */
 255 #define WM831X_OTP_ERR_EINT_SHIFT                    4  /* OTP_ERR_EINT */
 256 #define WM831X_OTP_ERR_EINT_WIDTH                    1  /* OTP_ERR_EINT */
 257 #define WM831X_PS_POR_EINT                      0x0004  /* PS_POR_EINT */
 258 #define WM831X_PS_POR_EINT_MASK                 0x0004  /* PS_POR_EINT */
 259 #define WM831X_PS_POR_EINT_SHIFT                     2  /* PS_POR_EINT */
 260 #define WM831X_PS_POR_EINT_WIDTH                     1  /* PS_POR_EINT */
 261 #define WM831X_PS_SLEEP_OFF_EINT                0x0002  /* PS_SLEEP_OFF_EINT */
 262 #define WM831X_PS_SLEEP_OFF_EINT_MASK           0x0002  /* PS_SLEEP_OFF_EINT */
 263 #define WM831X_PS_SLEEP_OFF_EINT_SHIFT               1  /* PS_SLEEP_OFF_EINT */
 264 #define WM831X_PS_SLEEP_OFF_EINT_WIDTH               1  /* PS_SLEEP_OFF_EINT */
 265 #define WM831X_PS_ON_WAKE_EINT                  0x0001  /* PS_ON_WAKE_EINT */
 266 #define WM831X_PS_ON_WAKE_EINT_MASK             0x0001  /* PS_ON_WAKE_EINT */
 267 #define WM831X_PS_ON_WAKE_EINT_SHIFT                 0  /* PS_ON_WAKE_EINT */
 268 #define WM831X_PS_ON_WAKE_EINT_WIDTH                 1  /* PS_ON_WAKE_EINT */
 269 
 270 /*
 271  * R16403 (0x4013) - Interrupt Status 3
 272  */
 273 #define WM831X_UV_LDO10_EINT                    0x0200  /* UV_LDO10_EINT */
 274 #define WM831X_UV_LDO10_EINT_MASK               0x0200  /* UV_LDO10_EINT */
 275 #define WM831X_UV_LDO10_EINT_SHIFT                   9  /* UV_LDO10_EINT */
 276 #define WM831X_UV_LDO10_EINT_WIDTH                   1  /* UV_LDO10_EINT */
 277 #define WM831X_UV_LDO9_EINT                     0x0100  /* UV_LDO9_EINT */
 278 #define WM831X_UV_LDO9_EINT_MASK                0x0100  /* UV_LDO9_EINT */
 279 #define WM831X_UV_LDO9_EINT_SHIFT                    8  /* UV_LDO9_EINT */
 280 #define WM831X_UV_LDO9_EINT_WIDTH                    1  /* UV_LDO9_EINT */
 281 #define WM831X_UV_LDO8_EINT                     0x0080  /* UV_LDO8_EINT */
 282 #define WM831X_UV_LDO8_EINT_MASK                0x0080  /* UV_LDO8_EINT */
 283 #define WM831X_UV_LDO8_EINT_SHIFT                    7  /* UV_LDO8_EINT */
 284 #define WM831X_UV_LDO8_EINT_WIDTH                    1  /* UV_LDO8_EINT */
 285 #define WM831X_UV_LDO7_EINT                     0x0040  /* UV_LDO7_EINT */
 286 #define WM831X_UV_LDO7_EINT_MASK                0x0040  /* UV_LDO7_EINT */
 287 #define WM831X_UV_LDO7_EINT_SHIFT                    6  /* UV_LDO7_EINT */
 288 #define WM831X_UV_LDO7_EINT_WIDTH                    1  /* UV_LDO7_EINT */
 289 #define WM831X_UV_LDO6_EINT                     0x0020  /* UV_LDO6_EINT */
 290 #define WM831X_UV_LDO6_EINT_MASK                0x0020  /* UV_LDO6_EINT */
 291 #define WM831X_UV_LDO6_EINT_SHIFT                    5  /* UV_LDO6_EINT */
 292 #define WM831X_UV_LDO6_EINT_WIDTH                    1  /* UV_LDO6_EINT */
 293 #define WM831X_UV_LDO5_EINT                     0x0010  /* UV_LDO5_EINT */
 294 #define WM831X_UV_LDO5_EINT_MASK                0x0010  /* UV_LDO5_EINT */
 295 #define WM831X_UV_LDO5_EINT_SHIFT                    4  /* UV_LDO5_EINT */
 296 #define WM831X_UV_LDO5_EINT_WIDTH                    1  /* UV_LDO5_EINT */
 297 #define WM831X_UV_LDO4_EINT                     0x0008  /* UV_LDO4_EINT */
 298 #define WM831X_UV_LDO4_EINT_MASK                0x0008  /* UV_LDO4_EINT */
 299 #define WM831X_UV_LDO4_EINT_SHIFT                    3  /* UV_LDO4_EINT */
 300 #define WM831X_UV_LDO4_EINT_WIDTH                    1  /* UV_LDO4_EINT */
 301 #define WM831X_UV_LDO3_EINT                     0x0004  /* UV_LDO3_EINT */
 302 #define WM831X_UV_LDO3_EINT_MASK                0x0004  /* UV_LDO3_EINT */
 303 #define WM831X_UV_LDO3_EINT_SHIFT                    2  /* UV_LDO3_EINT */
 304 #define WM831X_UV_LDO3_EINT_WIDTH                    1  /* UV_LDO3_EINT */
 305 #define WM831X_UV_LDO2_EINT                     0x0002  /* UV_LDO2_EINT */
 306 #define WM831X_UV_LDO2_EINT_MASK                0x0002  /* UV_LDO2_EINT */
 307 #define WM831X_UV_LDO2_EINT_SHIFT                    1  /* UV_LDO2_EINT */
 308 #define WM831X_UV_LDO2_EINT_WIDTH                    1  /* UV_LDO2_EINT */
 309 #define WM831X_UV_LDO1_EINT                     0x0001  /* UV_LDO1_EINT */
 310 #define WM831X_UV_LDO1_EINT_MASK                0x0001  /* UV_LDO1_EINT */
 311 #define WM831X_UV_LDO1_EINT_SHIFT                    0  /* UV_LDO1_EINT */
 312 #define WM831X_UV_LDO1_EINT_WIDTH                    1  /* UV_LDO1_EINT */
 313 
 314 /*
 315  * R16404 (0x4014) - Interrupt Status 4
 316  */
 317 #define WM831X_HC_DC2_EINT                      0x0200  /* HC_DC2_EINT */
 318 #define WM831X_HC_DC2_EINT_MASK                 0x0200  /* HC_DC2_EINT */
 319 #define WM831X_HC_DC2_EINT_SHIFT                     9  /* HC_DC2_EINT */
 320 #define WM831X_HC_DC2_EINT_WIDTH                     1  /* HC_DC2_EINT */
 321 #define WM831X_HC_DC1_EINT                      0x0100  /* HC_DC1_EINT */
 322 #define WM831X_HC_DC1_EINT_MASK                 0x0100  /* HC_DC1_EINT */
 323 #define WM831X_HC_DC1_EINT_SHIFT                     8  /* HC_DC1_EINT */
 324 #define WM831X_HC_DC1_EINT_WIDTH                     1  /* HC_DC1_EINT */
 325 #define WM831X_UV_DC4_EINT                      0x0008  /* UV_DC4_EINT */
 326 #define WM831X_UV_DC4_EINT_MASK                 0x0008  /* UV_DC4_EINT */
 327 #define WM831X_UV_DC4_EINT_SHIFT                     3  /* UV_DC4_EINT */
 328 #define WM831X_UV_DC4_EINT_WIDTH                     1  /* UV_DC4_EINT */
 329 #define WM831X_UV_DC3_EINT                      0x0004  /* UV_DC3_EINT */
 330 #define WM831X_UV_DC3_EINT_MASK                 0x0004  /* UV_DC3_EINT */
 331 #define WM831X_UV_DC3_EINT_SHIFT                     2  /* UV_DC3_EINT */
 332 #define WM831X_UV_DC3_EINT_WIDTH                     1  /* UV_DC3_EINT */
 333 #define WM831X_UV_DC2_EINT                      0x0002  /* UV_DC2_EINT */
 334 #define WM831X_UV_DC2_EINT_MASK                 0x0002  /* UV_DC2_EINT */
 335 #define WM831X_UV_DC2_EINT_SHIFT                     1  /* UV_DC2_EINT */
 336 #define WM831X_UV_DC2_EINT_WIDTH                     1  /* UV_DC2_EINT */
 337 #define WM831X_UV_DC1_EINT                      0x0001  /* UV_DC1_EINT */
 338 #define WM831X_UV_DC1_EINT_MASK                 0x0001  /* UV_DC1_EINT */
 339 #define WM831X_UV_DC1_EINT_SHIFT                     0  /* UV_DC1_EINT */
 340 #define WM831X_UV_DC1_EINT_WIDTH                     1  /* UV_DC1_EINT */
 341 
 342 /*
 343  * R16405 (0x4015) - Interrupt Status 5
 344  */
 345 #define WM831X_GP16_EINT                        0x8000  /* GP16_EINT */
 346 #define WM831X_GP16_EINT_MASK                   0x8000  /* GP16_EINT */
 347 #define WM831X_GP16_EINT_SHIFT                      15  /* GP16_EINT */
 348 #define WM831X_GP16_EINT_WIDTH                       1  /* GP16_EINT */
 349 #define WM831X_GP15_EINT                        0x4000  /* GP15_EINT */
 350 #define WM831X_GP15_EINT_MASK                   0x4000  /* GP15_EINT */
 351 #define WM831X_GP15_EINT_SHIFT                      14  /* GP15_EINT */
 352 #define WM831X_GP15_EINT_WIDTH                       1  /* GP15_EINT */
 353 #define WM831X_GP14_EINT                        0x2000  /* GP14_EINT */
 354 #define WM831X_GP14_EINT_MASK                   0x2000  /* GP14_EINT */
 355 #define WM831X_GP14_EINT_SHIFT                      13  /* GP14_EINT */
 356 #define WM831X_GP14_EINT_WIDTH                       1  /* GP14_EINT */
 357 #define WM831X_GP13_EINT                        0x1000  /* GP13_EINT */
 358 #define WM831X_GP13_EINT_MASK                   0x1000  /* GP13_EINT */
 359 #define WM831X_GP13_EINT_SHIFT                      12  /* GP13_EINT */
 360 #define WM831X_GP13_EINT_WIDTH                       1  /* GP13_EINT */
 361 #define WM831X_GP12_EINT                        0x0800  /* GP12_EINT */
 362 #define WM831X_GP12_EINT_MASK                   0x0800  /* GP12_EINT */
 363 #define WM831X_GP12_EINT_SHIFT                      11  /* GP12_EINT */
 364 #define WM831X_GP12_EINT_WIDTH                       1  /* GP12_EINT */
 365 #define WM831X_GP11_EINT                        0x0400  /* GP11_EINT */
 366 #define WM831X_GP11_EINT_MASK                   0x0400  /* GP11_EINT */
 367 #define WM831X_GP11_EINT_SHIFT                      10  /* GP11_EINT */
 368 #define WM831X_GP11_EINT_WIDTH                       1  /* GP11_EINT */
 369 #define WM831X_GP10_EINT                        0x0200  /* GP10_EINT */
 370 #define WM831X_GP10_EINT_MASK                   0x0200  /* GP10_EINT */
 371 #define WM831X_GP10_EINT_SHIFT                       9  /* GP10_EINT */
 372 #define WM831X_GP10_EINT_WIDTH                       1  /* GP10_EINT */
 373 #define WM831X_GP9_EINT                         0x0100  /* GP9_EINT */
 374 #define WM831X_GP9_EINT_MASK                    0x0100  /* GP9_EINT */
 375 #define WM831X_GP9_EINT_SHIFT                        8  /* GP9_EINT */
 376 #define WM831X_GP9_EINT_WIDTH                        1  /* GP9_EINT */
 377 #define WM831X_GP8_EINT                         0x0080  /* GP8_EINT */
 378 #define WM831X_GP8_EINT_MASK                    0x0080  /* GP8_EINT */
 379 #define WM831X_GP8_EINT_SHIFT                        7  /* GP8_EINT */
 380 #define WM831X_GP8_EINT_WIDTH                        1  /* GP8_EINT */
 381 #define WM831X_GP7_EINT                         0x0040  /* GP7_EINT */
 382 #define WM831X_GP7_EINT_MASK                    0x0040  /* GP7_EINT */
 383 #define WM831X_GP7_EINT_SHIFT                        6  /* GP7_EINT */
 384 #define WM831X_GP7_EINT_WIDTH                        1  /* GP7_EINT */
 385 #define WM831X_GP6_EINT                         0x0020  /* GP6_EINT */
 386 #define WM831X_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
 387 #define WM831X_GP6_EINT_SHIFT                        5  /* GP6_EINT */
 388 #define WM831X_GP6_EINT_WIDTH                        1  /* GP6_EINT */
 389 #define WM831X_GP5_EINT                         0x0010  /* GP5_EINT */
 390 #define WM831X_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
 391 #define WM831X_GP5_EINT_SHIFT                        4  /* GP5_EINT */
 392 #define WM831X_GP5_EINT_WIDTH                        1  /* GP5_EINT */
 393 #define WM831X_GP4_EINT                         0x0008  /* GP4_EINT */
 394 #define WM831X_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
 395 #define WM831X_GP4_EINT_SHIFT                        3  /* GP4_EINT */
 396 #define WM831X_GP4_EINT_WIDTH                        1  /* GP4_EINT */
 397 #define WM831X_GP3_EINT                         0x0004  /* GP3_EINT */
 398 #define WM831X_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
 399 #define WM831X_GP3_EINT_SHIFT                        2  /* GP3_EINT */
 400 #define WM831X_GP3_EINT_WIDTH                        1  /* GP3_EINT */
 401 #define WM831X_GP2_EINT                         0x0002  /* GP2_EINT */
 402 #define WM831X_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
 403 #define WM831X_GP2_EINT_SHIFT                        1  /* GP2_EINT */
 404 #define WM831X_GP2_EINT_WIDTH                        1  /* GP2_EINT */
 405 #define WM831X_GP1_EINT                         0x0001  /* GP1_EINT */
 406 #define WM831X_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
 407 #define WM831X_GP1_EINT_SHIFT                        0  /* GP1_EINT */
 408 #define WM831X_GP1_EINT_WIDTH                        1  /* GP1_EINT */
 409 
 410 /*
 411  * R16407 (0x4017) - IRQ Config
 412  */
 413 #define WM831X_IRQ_OD                           0x0002  /* IRQ_OD */
 414 #define WM831X_IRQ_OD_MASK                      0x0002  /* IRQ_OD */
 415 #define WM831X_IRQ_OD_SHIFT                          1  /* IRQ_OD */
 416 #define WM831X_IRQ_OD_WIDTH                          1  /* IRQ_OD */
 417 #define WM831X_IM_IRQ                           0x0001  /* IM_IRQ */
 418 #define WM831X_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
 419 #define WM831X_IM_IRQ_SHIFT                          0  /* IM_IRQ */
 420 #define WM831X_IM_IRQ_WIDTH                          1  /* IM_IRQ */
 421 
 422 /*
 423  * R16408 (0x4018) - System Interrupts Mask
 424  */
 425 #define WM831X_IM_PS_INT                        0x8000  /* IM_PS_INT */
 426 #define WM831X_IM_PS_INT_MASK                   0x8000  /* IM_PS_INT */
 427 #define WM831X_IM_PS_INT_SHIFT                      15  /* IM_PS_INT */
 428 #define WM831X_IM_PS_INT_WIDTH                       1  /* IM_PS_INT */
 429 #define WM831X_IM_TEMP_INT                      0x4000  /* IM_TEMP_INT */
 430 #define WM831X_IM_TEMP_INT_MASK                 0x4000  /* IM_TEMP_INT */
 431 #define WM831X_IM_TEMP_INT_SHIFT                    14  /* IM_TEMP_INT */
 432 #define WM831X_IM_TEMP_INT_WIDTH                     1  /* IM_TEMP_INT */
 433 #define WM831X_IM_GP_INT                        0x2000  /* IM_GP_INT */
 434 #define WM831X_IM_GP_INT_MASK                   0x2000  /* IM_GP_INT */
 435 #define WM831X_IM_GP_INT_SHIFT                      13  /* IM_GP_INT */
 436 #define WM831X_IM_GP_INT_WIDTH                       1  /* IM_GP_INT */
 437 #define WM831X_IM_ON_PIN_INT                    0x1000  /* IM_ON_PIN_INT */
 438 #define WM831X_IM_ON_PIN_INT_MASK               0x1000  /* IM_ON_PIN_INT */
 439 #define WM831X_IM_ON_PIN_INT_SHIFT                  12  /* IM_ON_PIN_INT */
 440 #define WM831X_IM_ON_PIN_INT_WIDTH                   1  /* IM_ON_PIN_INT */
 441 #define WM831X_IM_WDOG_INT                      0x0800  /* IM_WDOG_INT */
 442 #define WM831X_IM_WDOG_INT_MASK                 0x0800  /* IM_WDOG_INT */
 443 #define WM831X_IM_WDOG_INT_SHIFT                    11  /* IM_WDOG_INT */
 444 #define WM831X_IM_WDOG_INT_WIDTH                     1  /* IM_WDOG_INT */
 445 #define WM831X_IM_TCHDATA_INT                   0x0400  /* IM_TCHDATA_INT */
 446 #define WM831X_IM_TCHDATA_INT_MASK              0x0400  /* IM_TCHDATA_INT */
 447 #define WM831X_IM_TCHDATA_INT_SHIFT                 10  /* IM_TCHDATA_INT */
 448 #define WM831X_IM_TCHDATA_INT_WIDTH                  1  /* IM_TCHDATA_INT */
 449 #define WM831X_IM_TCHPD_INT                     0x0200  /* IM_TCHPD_INT */
 450 #define WM831X_IM_TCHPD_INT_MASK                0x0200  /* IM_TCHPD_INT */
 451 #define WM831X_IM_TCHPD_INT_SHIFT                    9  /* IM_TCHPD_INT */
 452 #define WM831X_IM_TCHPD_INT_WIDTH                    1  /* IM_TCHPD_INT */
 453 #define WM831X_IM_AUXADC_INT                    0x0100  /* IM_AUXADC_INT */
 454 #define WM831X_IM_AUXADC_INT_MASK               0x0100  /* IM_AUXADC_INT */
 455 #define WM831X_IM_AUXADC_INT_SHIFT                   8  /* IM_AUXADC_INT */
 456 #define WM831X_IM_AUXADC_INT_WIDTH                   1  /* IM_AUXADC_INT */
 457 #define WM831X_IM_PPM_INT                       0x0080  /* IM_PPM_INT */
 458 #define WM831X_IM_PPM_INT_MASK                  0x0080  /* IM_PPM_INT */
 459 #define WM831X_IM_PPM_INT_SHIFT                      7  /* IM_PPM_INT */
 460 #define WM831X_IM_PPM_INT_WIDTH                      1  /* IM_PPM_INT */
 461 #define WM831X_IM_CS_INT                        0x0040  /* IM_CS_INT */
 462 #define WM831X_IM_CS_INT_MASK                   0x0040  /* IM_CS_INT */
 463 #define WM831X_IM_CS_INT_SHIFT                       6  /* IM_CS_INT */
 464 #define WM831X_IM_CS_INT_WIDTH                       1  /* IM_CS_INT */
 465 #define WM831X_IM_RTC_INT                       0x0020  /* IM_RTC_INT */
 466 #define WM831X_IM_RTC_INT_MASK                  0x0020  /* IM_RTC_INT */
 467 #define WM831X_IM_RTC_INT_SHIFT                      5  /* IM_RTC_INT */
 468 #define WM831X_IM_RTC_INT_WIDTH                      1  /* IM_RTC_INT */
 469 #define WM831X_IM_OTP_INT                       0x0010  /* IM_OTP_INT */
 470 #define WM831X_IM_OTP_INT_MASK                  0x0010  /* IM_OTP_INT */
 471 #define WM831X_IM_OTP_INT_SHIFT                      4  /* IM_OTP_INT */
 472 #define WM831X_IM_OTP_INT_WIDTH                      1  /* IM_OTP_INT */
 473 #define WM831X_IM_CHILD_INT                     0x0008  /* IM_CHILD_INT */
 474 #define WM831X_IM_CHILD_INT_MASK                0x0008  /* IM_CHILD_INT */
 475 #define WM831X_IM_CHILD_INT_SHIFT                    3  /* IM_CHILD_INT */
 476 #define WM831X_IM_CHILD_INT_WIDTH                    1  /* IM_CHILD_INT */
 477 #define WM831X_IM_CHG_INT                       0x0004  /* IM_CHG_INT */
 478 #define WM831X_IM_CHG_INT_MASK                  0x0004  /* IM_CHG_INT */
 479 #define WM831X_IM_CHG_INT_SHIFT                      2  /* IM_CHG_INT */
 480 #define WM831X_IM_CHG_INT_WIDTH                      1  /* IM_CHG_INT */
 481 #define WM831X_IM_HC_INT                        0x0002  /* IM_HC_INT */
 482 #define WM831X_IM_HC_INT_MASK                   0x0002  /* IM_HC_INT */
 483 #define WM831X_IM_HC_INT_SHIFT                       1  /* IM_HC_INT */
 484 #define WM831X_IM_HC_INT_WIDTH                       1  /* IM_HC_INT */
 485 #define WM831X_IM_UV_INT                        0x0001  /* IM_UV_INT */
 486 #define WM831X_IM_UV_INT_MASK                   0x0001  /* IM_UV_INT */
 487 #define WM831X_IM_UV_INT_SHIFT                       0  /* IM_UV_INT */
 488 #define WM831X_IM_UV_INT_WIDTH                       1  /* IM_UV_INT */
 489 
 490 /*
 491  * R16409 (0x4019) - Interrupt Status 1 Mask
 492  */
 493 #define WM831X_IM_PPM_SYSLO_EINT                0x8000  /* IM_PPM_SYSLO_EINT */
 494 #define WM831X_IM_PPM_SYSLO_EINT_MASK           0x8000  /* IM_PPM_SYSLO_EINT */
 495 #define WM831X_IM_PPM_SYSLO_EINT_SHIFT              15  /* IM_PPM_SYSLO_EINT */
 496 #define WM831X_IM_PPM_SYSLO_EINT_WIDTH               1  /* IM_PPM_SYSLO_EINT */
 497 #define WM831X_IM_PPM_PWR_SRC_EINT              0x4000  /* IM_PPM_PWR_SRC_EINT */
 498 #define WM831X_IM_PPM_PWR_SRC_EINT_MASK         0x4000  /* IM_PPM_PWR_SRC_EINT */
 499 #define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT            14  /* IM_PPM_PWR_SRC_EINT */
 500 #define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH             1  /* IM_PPM_PWR_SRC_EINT */
 501 #define WM831X_IM_PPM_USB_CURR_EINT             0x2000  /* IM_PPM_USB_CURR_EINT */
 502 #define WM831X_IM_PPM_USB_CURR_EINT_MASK        0x2000  /* IM_PPM_USB_CURR_EINT */
 503 #define WM831X_IM_PPM_USB_CURR_EINT_SHIFT           13  /* IM_PPM_USB_CURR_EINT */
 504 #define WM831X_IM_PPM_USB_CURR_EINT_WIDTH            1  /* IM_PPM_USB_CURR_EINT */
 505 #define WM831X_IM_ON_PIN_EINT                   0x1000  /* IM_ON_PIN_EINT */
 506 #define WM831X_IM_ON_PIN_EINT_MASK              0x1000  /* IM_ON_PIN_EINT */
 507 #define WM831X_IM_ON_PIN_EINT_SHIFT                 12  /* IM_ON_PIN_EINT */
 508 #define WM831X_IM_ON_PIN_EINT_WIDTH                  1  /* IM_ON_PIN_EINT */
 509 #define WM831X_IM_WDOG_TO_EINT                  0x0800  /* IM_WDOG_TO_EINT */
 510 #define WM831X_IM_WDOG_TO_EINT_MASK             0x0800  /* IM_WDOG_TO_EINT */
 511 #define WM831X_IM_WDOG_TO_EINT_SHIFT                11  /* IM_WDOG_TO_EINT */
 512 #define WM831X_IM_WDOG_TO_EINT_WIDTH                 1  /* IM_WDOG_TO_EINT */
 513 #define WM831X_IM_TCHDATA_EINT                  0x0400  /* IM_TCHDATA_EINT */
 514 #define WM831X_IM_TCHDATA_EINT_MASK             0x0400  /* IM_TCHDATA_EINT */
 515 #define WM831X_IM_TCHDATA_EINT_SHIFT                10  /* IM_TCHDATA_EINT */
 516 #define WM831X_IM_TCHDATA_EINT_WIDTH                 1  /* IM_TCHDATA_EINT */
 517 #define WM831X_IM_TCHPD_EINT                    0x0200  /* IM_TCHPD_EINT */
 518 #define WM831X_IM_TCHPD_EINT_MASK               0x0200  /* IM_TCHPD_EINT */
 519 #define WM831X_IM_TCHPD_EINT_SHIFT                   9  /* IM_TCHPD_EINT */
 520 #define WM831X_IM_TCHPD_EINT_WIDTH                   1  /* IM_TCHPD_EINT */
 521 #define WM831X_IM_AUXADC_DATA_EINT              0x0100  /* IM_AUXADC_DATA_EINT */
 522 #define WM831X_IM_AUXADC_DATA_EINT_MASK         0x0100  /* IM_AUXADC_DATA_EINT */
 523 #define WM831X_IM_AUXADC_DATA_EINT_SHIFT             8  /* IM_AUXADC_DATA_EINT */
 524 #define WM831X_IM_AUXADC_DATA_EINT_WIDTH             1  /* IM_AUXADC_DATA_EINT */
 525 #define WM831X_IM_AUXADC_DCOMP4_EINT            0x0080  /* IM_AUXADC_DCOMP4_EINT */
 526 #define WM831X_IM_AUXADC_DCOMP4_EINT_MASK       0x0080  /* IM_AUXADC_DCOMP4_EINT */
 527 #define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT           7  /* IM_AUXADC_DCOMP4_EINT */
 528 #define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH           1  /* IM_AUXADC_DCOMP4_EINT */
 529 #define WM831X_IM_AUXADC_DCOMP3_EINT            0x0040  /* IM_AUXADC_DCOMP3_EINT */
 530 #define WM831X_IM_AUXADC_DCOMP3_EINT_MASK       0x0040  /* IM_AUXADC_DCOMP3_EINT */
 531 #define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT           6  /* IM_AUXADC_DCOMP3_EINT */
 532 #define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH           1  /* IM_AUXADC_DCOMP3_EINT */
 533 #define WM831X_IM_AUXADC_DCOMP2_EINT            0x0020  /* IM_AUXADC_DCOMP2_EINT */
 534 #define WM831X_IM_AUXADC_DCOMP2_EINT_MASK       0x0020  /* IM_AUXADC_DCOMP2_EINT */
 535 #define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT           5  /* IM_AUXADC_DCOMP2_EINT */
 536 #define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH           1  /* IM_AUXADC_DCOMP2_EINT */
 537 #define WM831X_IM_AUXADC_DCOMP1_EINT            0x0010  /* IM_AUXADC_DCOMP1_EINT */
 538 #define WM831X_IM_AUXADC_DCOMP1_EINT_MASK       0x0010  /* IM_AUXADC_DCOMP1_EINT */
 539 #define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT           4  /* IM_AUXADC_DCOMP1_EINT */
 540 #define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH           1  /* IM_AUXADC_DCOMP1_EINT */
 541 #define WM831X_IM_RTC_PER_EINT                  0x0008  /* IM_RTC_PER_EINT */
 542 #define WM831X_IM_RTC_PER_EINT_MASK             0x0008  /* IM_RTC_PER_EINT */
 543 #define WM831X_IM_RTC_PER_EINT_SHIFT                 3  /* IM_RTC_PER_EINT */
 544 #define WM831X_IM_RTC_PER_EINT_WIDTH                 1  /* IM_RTC_PER_EINT */
 545 #define WM831X_IM_RTC_ALM_EINT                  0x0004  /* IM_RTC_ALM_EINT */
 546 #define WM831X_IM_RTC_ALM_EINT_MASK             0x0004  /* IM_RTC_ALM_EINT */
 547 #define WM831X_IM_RTC_ALM_EINT_SHIFT                 2  /* IM_RTC_ALM_EINT */
 548 #define WM831X_IM_RTC_ALM_EINT_WIDTH                 1  /* IM_RTC_ALM_EINT */
 549 #define WM831X_IM_TEMP_THW_EINT                 0x0002  /* IM_TEMP_THW_EINT */
 550 #define WM831X_IM_TEMP_THW_EINT_MASK            0x0002  /* IM_TEMP_THW_EINT */
 551 #define WM831X_IM_TEMP_THW_EINT_SHIFT                1  /* IM_TEMP_THW_EINT */
 552 #define WM831X_IM_TEMP_THW_EINT_WIDTH                1  /* IM_TEMP_THW_EINT */
 553 
 554 /*
 555  * R16410 (0x401A) - Interrupt Status 2 Mask
 556  */
 557 #define WM831X_IM_CHG_BATT_HOT_EINT             0x8000  /* IM_CHG_BATT_HOT_EINT */
 558 #define WM831X_IM_CHG_BATT_HOT_EINT_MASK        0x8000  /* IM_CHG_BATT_HOT_EINT */
 559 #define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT           15  /* IM_CHG_BATT_HOT_EINT */
 560 #define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH            1  /* IM_CHG_BATT_HOT_EINT */
 561 #define WM831X_IM_CHG_BATT_COLD_EINT            0x4000  /* IM_CHG_BATT_COLD_EINT */
 562 #define WM831X_IM_CHG_BATT_COLD_EINT_MASK       0x4000  /* IM_CHG_BATT_COLD_EINT */
 563 #define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT          14  /* IM_CHG_BATT_COLD_EINT */
 564 #define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH           1  /* IM_CHG_BATT_COLD_EINT */
 565 #define WM831X_IM_CHG_BATT_FAIL_EINT            0x2000  /* IM_CHG_BATT_FAIL_EINT */
 566 #define WM831X_IM_CHG_BATT_FAIL_EINT_MASK       0x2000  /* IM_CHG_BATT_FAIL_EINT */
 567 #define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT          13  /* IM_CHG_BATT_FAIL_EINT */
 568 #define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH           1  /* IM_CHG_BATT_FAIL_EINT */
 569 #define WM831X_IM_CHG_OV_EINT                   0x1000  /* IM_CHG_OV_EINT */
 570 #define WM831X_IM_CHG_OV_EINT_MASK              0x1000  /* IM_CHG_OV_EINT */
 571 #define WM831X_IM_CHG_OV_EINT_SHIFT                 12  /* IM_CHG_OV_EINT */
 572 #define WM831X_IM_CHG_OV_EINT_WIDTH                  1  /* IM_CHG_OV_EINT */
 573 #define WM831X_IM_CHG_END_EINT                  0x0800  /* IM_CHG_END_EINT */
 574 #define WM831X_IM_CHG_END_EINT_MASK             0x0800  /* IM_CHG_END_EINT */
 575 #define WM831X_IM_CHG_END_EINT_SHIFT                11  /* IM_CHG_END_EINT */
 576 #define WM831X_IM_CHG_END_EINT_WIDTH                 1  /* IM_CHG_END_EINT */
 577 #define WM831X_IM_CHG_TO_EINT                   0x0400  /* IM_CHG_TO_EINT */
 578 #define WM831X_IM_CHG_TO_EINT_MASK              0x0400  /* IM_CHG_TO_EINT */
 579 #define WM831X_IM_CHG_TO_EINT_SHIFT                 10  /* IM_CHG_TO_EINT */
 580 #define WM831X_IM_CHG_TO_EINT_WIDTH                  1  /* IM_CHG_TO_EINT */
 581 #define WM831X_IM_CHG_MODE_EINT                 0x0200  /* IM_CHG_MODE_EINT */
 582 #define WM831X_IM_CHG_MODE_EINT_MASK            0x0200  /* IM_CHG_MODE_EINT */
 583 #define WM831X_IM_CHG_MODE_EINT_SHIFT                9  /* IM_CHG_MODE_EINT */
 584 #define WM831X_IM_CHG_MODE_EINT_WIDTH                1  /* IM_CHG_MODE_EINT */
 585 #define WM831X_IM_CHG_START_EINT                0x0100  /* IM_CHG_START_EINT */
 586 #define WM831X_IM_CHG_START_EINT_MASK           0x0100  /* IM_CHG_START_EINT */
 587 #define WM831X_IM_CHG_START_EINT_SHIFT               8  /* IM_CHG_START_EINT */
 588 #define WM831X_IM_CHG_START_EINT_WIDTH               1  /* IM_CHG_START_EINT */
 589 #define WM831X_IM_CS2_EINT                      0x0080  /* IM_CS2_EINT */
 590 #define WM831X_IM_CS2_EINT_MASK                 0x0080  /* IM_CS2_EINT */
 591 #define WM831X_IM_CS2_EINT_SHIFT                     7  /* IM_CS2_EINT */
 592 #define WM831X_IM_CS2_EINT_WIDTH                     1  /* IM_CS2_EINT */
 593 #define WM831X_IM_CS1_EINT                      0x0040  /* IM_CS1_EINT */
 594 #define WM831X_IM_CS1_EINT_MASK                 0x0040  /* IM_CS1_EINT */
 595 #define WM831X_IM_CS1_EINT_SHIFT                     6  /* IM_CS1_EINT */
 596 #define WM831X_IM_CS1_EINT_WIDTH                     1  /* IM_CS1_EINT */
 597 #define WM831X_IM_OTP_CMD_END_EINT              0x0020  /* IM_OTP_CMD_END_EINT */
 598 #define WM831X_IM_OTP_CMD_END_EINT_MASK         0x0020  /* IM_OTP_CMD_END_EINT */
 599 #define WM831X_IM_OTP_CMD_END_EINT_SHIFT             5  /* IM_OTP_CMD_END_EINT */
 600 #define WM831X_IM_OTP_CMD_END_EINT_WIDTH             1  /* IM_OTP_CMD_END_EINT */
 601 #define WM831X_IM_OTP_ERR_EINT                  0x0010  /* IM_OTP_ERR_EINT */
 602 #define WM831X_IM_OTP_ERR_EINT_MASK             0x0010  /* IM_OTP_ERR_EINT */
 603 #define WM831X_IM_OTP_ERR_EINT_SHIFT                 4  /* IM_OTP_ERR_EINT */
 604 #define WM831X_IM_OTP_ERR_EINT_WIDTH                 1  /* IM_OTP_ERR_EINT */
 605 #define WM831X_IM_PS_POR_EINT                   0x0004  /* IM_PS_POR_EINT */
 606 #define WM831X_IM_PS_POR_EINT_MASK              0x0004  /* IM_PS_POR_EINT */
 607 #define WM831X_IM_PS_POR_EINT_SHIFT                  2  /* IM_PS_POR_EINT */
 608 #define WM831X_IM_PS_POR_EINT_WIDTH                  1  /* IM_PS_POR_EINT */
 609 #define WM831X_IM_PS_SLEEP_OFF_EINT             0x0002  /* IM_PS_SLEEP_OFF_EINT */
 610 #define WM831X_IM_PS_SLEEP_OFF_EINT_MASK        0x0002  /* IM_PS_SLEEP_OFF_EINT */
 611 #define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT            1  /* IM_PS_SLEEP_OFF_EINT */
 612 #define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH            1  /* IM_PS_SLEEP_OFF_EINT */
 613 #define WM831X_IM_PS_ON_WAKE_EINT               0x0001  /* IM_PS_ON_WAKE_EINT */
 614 #define WM831X_IM_PS_ON_WAKE_EINT_MASK          0x0001  /* IM_PS_ON_WAKE_EINT */
 615 #define WM831X_IM_PS_ON_WAKE_EINT_SHIFT              0  /* IM_PS_ON_WAKE_EINT */
 616 #define WM831X_IM_PS_ON_WAKE_EINT_WIDTH              1  /* IM_PS_ON_WAKE_EINT */
 617 
 618 /*
 619  * R16411 (0x401B) - Interrupt Status 3 Mask
 620  */
 621 #define WM831X_IM_UV_LDO10_EINT                 0x0200  /* IM_UV_LDO10_EINT */
 622 #define WM831X_IM_UV_LDO10_EINT_MASK            0x0200  /* IM_UV_LDO10_EINT */
 623 #define WM831X_IM_UV_LDO10_EINT_SHIFT                9  /* IM_UV_LDO10_EINT */
 624 #define WM831X_IM_UV_LDO10_EINT_WIDTH                1  /* IM_UV_LDO10_EINT */
 625 #define WM831X_IM_UV_LDO9_EINT                  0x0100  /* IM_UV_LDO9_EINT */
 626 #define WM831X_IM_UV_LDO9_EINT_MASK             0x0100  /* IM_UV_LDO9_EINT */
 627 #define WM831X_IM_UV_LDO9_EINT_SHIFT                 8  /* IM_UV_LDO9_EINT */
 628 #define WM831X_IM_UV_LDO9_EINT_WIDTH                 1  /* IM_UV_LDO9_EINT */
 629 #define WM831X_IM_UV_LDO8_EINT                  0x0080  /* IM_UV_LDO8_EINT */
 630 #define WM831X_IM_UV_LDO8_EINT_MASK             0x0080  /* IM_UV_LDO8_EINT */
 631 #define WM831X_IM_UV_LDO8_EINT_SHIFT                 7  /* IM_UV_LDO8_EINT */
 632 #define WM831X_IM_UV_LDO8_EINT_WIDTH                 1  /* IM_UV_LDO8_EINT */
 633 #define WM831X_IM_UV_LDO7_EINT                  0x0040  /* IM_UV_LDO7_EINT */
 634 #define WM831X_IM_UV_LDO7_EINT_MASK             0x0040  /* IM_UV_LDO7_EINT */
 635 #define WM831X_IM_UV_LDO7_EINT_SHIFT                 6  /* IM_UV_LDO7_EINT */
 636 #define WM831X_IM_UV_LDO7_EINT_WIDTH                 1  /* IM_UV_LDO7_EINT */
 637 #define WM831X_IM_UV_LDO6_EINT                  0x0020  /* IM_UV_LDO6_EINT */
 638 #define WM831X_IM_UV_LDO6_EINT_MASK             0x0020  /* IM_UV_LDO6_EINT */
 639 #define WM831X_IM_UV_LDO6_EINT_SHIFT                 5  /* IM_UV_LDO6_EINT */
 640 #define WM831X_IM_UV_LDO6_EINT_WIDTH                 1  /* IM_UV_LDO6_EINT */
 641 #define WM831X_IM_UV_LDO5_EINT                  0x0010  /* IM_UV_LDO5_EINT */
 642 #define WM831X_IM_UV_LDO5_EINT_MASK             0x0010  /* IM_UV_LDO5_EINT */
 643 #define WM831X_IM_UV_LDO5_EINT_SHIFT                 4  /* IM_UV_LDO5_EINT */
 644 #define WM831X_IM_UV_LDO5_EINT_WIDTH                 1  /* IM_UV_LDO5_EINT */
 645 #define WM831X_IM_UV_LDO4_EINT                  0x0008  /* IM_UV_LDO4_EINT */
 646 #define WM831X_IM_UV_LDO4_EINT_MASK             0x0008  /* IM_UV_LDO4_EINT */
 647 #define WM831X_IM_UV_LDO4_EINT_SHIFT                 3  /* IM_UV_LDO4_EINT */
 648 #define WM831X_IM_UV_LDO4_EINT_WIDTH                 1  /* IM_UV_LDO4_EINT */
 649 #define WM831X_IM_UV_LDO3_EINT                  0x0004  /* IM_UV_LDO3_EINT */
 650 #define WM831X_IM_UV_LDO3_EINT_MASK             0x0004  /* IM_UV_LDO3_EINT */
 651 #define WM831X_IM_UV_LDO3_EINT_SHIFT                 2  /* IM_UV_LDO3_EINT */
 652 #define WM831X_IM_UV_LDO3_EINT_WIDTH                 1  /* IM_UV_LDO3_EINT */
 653 #define WM831X_IM_UV_LDO2_EINT                  0x0002  /* IM_UV_LDO2_EINT */
 654 #define WM831X_IM_UV_LDO2_EINT_MASK             0x0002  /* IM_UV_LDO2_EINT */
 655 #define WM831X_IM_UV_LDO2_EINT_SHIFT                 1  /* IM_UV_LDO2_EINT */
 656 #define WM831X_IM_UV_LDO2_EINT_WIDTH                 1  /* IM_UV_LDO2_EINT */
 657 #define WM831X_IM_UV_LDO1_EINT                  0x0001  /* IM_UV_LDO1_EINT */
 658 #define WM831X_IM_UV_LDO1_EINT_MASK             0x0001  /* IM_UV_LDO1_EINT */
 659 #define WM831X_IM_UV_LDO1_EINT_SHIFT                 0  /* IM_UV_LDO1_EINT */
 660 #define WM831X_IM_UV_LDO1_EINT_WIDTH                 1  /* IM_UV_LDO1_EINT */
 661 
 662 /*
 663  * R16412 (0x401C) - Interrupt Status 4 Mask
 664  */
 665 #define WM831X_IM_HC_DC2_EINT                   0x0200  /* IM_HC_DC2_EINT */
 666 #define WM831X_IM_HC_DC2_EINT_MASK              0x0200  /* IM_HC_DC2_EINT */
 667 #define WM831X_IM_HC_DC2_EINT_SHIFT                  9  /* IM_HC_DC2_EINT */
 668 #define WM831X_IM_HC_DC2_EINT_WIDTH                  1  /* IM_HC_DC2_EINT */
 669 #define WM831X_IM_HC_DC1_EINT                   0x0100  /* IM_HC_DC1_EINT */
 670 #define WM831X_IM_HC_DC1_EINT_MASK              0x0100  /* IM_HC_DC1_EINT */
 671 #define WM831X_IM_HC_DC1_EINT_SHIFT                  8  /* IM_HC_DC1_EINT */
 672 #define WM831X_IM_HC_DC1_EINT_WIDTH                  1  /* IM_HC_DC1_EINT */
 673 #define WM831X_IM_UV_DC4_EINT                   0x0008  /* IM_UV_DC4_EINT */
 674 #define WM831X_IM_UV_DC4_EINT_MASK              0x0008  /* IM_UV_DC4_EINT */
 675 #define WM831X_IM_UV_DC4_EINT_SHIFT                  3  /* IM_UV_DC4_EINT */
 676 #define WM831X_IM_UV_DC4_EINT_WIDTH                  1  /* IM_UV_DC4_EINT */
 677 #define WM831X_IM_UV_DC3_EINT                   0x0004  /* IM_UV_DC3_EINT */
 678 #define WM831X_IM_UV_DC3_EINT_MASK              0x0004  /* IM_UV_DC3_EINT */
 679 #define WM831X_IM_UV_DC3_EINT_SHIFT                  2  /* IM_UV_DC3_EINT */
 680 #define WM831X_IM_UV_DC3_EINT_WIDTH                  1  /* IM_UV_DC3_EINT */
 681 #define WM831X_IM_UV_DC2_EINT                   0x0002  /* IM_UV_DC2_EINT */
 682 #define WM831X_IM_UV_DC2_EINT_MASK              0x0002  /* IM_UV_DC2_EINT */
 683 #define WM831X_IM_UV_DC2_EINT_SHIFT                  1  /* IM_UV_DC2_EINT */
 684 #define WM831X_IM_UV_DC2_EINT_WIDTH                  1  /* IM_UV_DC2_EINT */
 685 #define WM831X_IM_UV_DC1_EINT                   0x0001  /* IM_UV_DC1_EINT */
 686 #define WM831X_IM_UV_DC1_EINT_MASK              0x0001  /* IM_UV_DC1_EINT */
 687 #define WM831X_IM_UV_DC1_EINT_SHIFT                  0  /* IM_UV_DC1_EINT */
 688 #define WM831X_IM_UV_DC1_EINT_WIDTH                  1  /* IM_UV_DC1_EINT */
 689 
 690 /*
 691  * R16413 (0x401D) - Interrupt Status 5 Mask
 692  */
 693 #define WM831X_IM_GP16_EINT                     0x8000  /* IM_GP16_EINT */
 694 #define WM831X_IM_GP16_EINT_MASK                0x8000  /* IM_GP16_EINT */
 695 #define WM831X_IM_GP16_EINT_SHIFT                   15  /* IM_GP16_EINT */
 696 #define WM831X_IM_GP16_EINT_WIDTH                    1  /* IM_GP16_EINT */
 697 #define WM831X_IM_GP15_EINT                     0x4000  /* IM_GP15_EINT */
 698 #define WM831X_IM_GP15_EINT_MASK                0x4000  /* IM_GP15_EINT */
 699 #define WM831X_IM_GP15_EINT_SHIFT                   14  /* IM_GP15_EINT */
 700 #define WM831X_IM_GP15_EINT_WIDTH                    1  /* IM_GP15_EINT */
 701 #define WM831X_IM_GP14_EINT                     0x2000  /* IM_GP14_EINT */
 702 #define WM831X_IM_GP14_EINT_MASK                0x2000  /* IM_GP14_EINT */
 703 #define WM831X_IM_GP14_EINT_SHIFT                   13  /* IM_GP14_EINT */
 704 #define WM831X_IM_GP14_EINT_WIDTH                    1  /* IM_GP14_EINT */
 705 #define WM831X_IM_GP13_EINT                     0x1000  /* IM_GP13_EINT */
 706 #define WM831X_IM_GP13_EINT_MASK                0x1000  /* IM_GP13_EINT */
 707 #define WM831X_IM_GP13_EINT_SHIFT                   12  /* IM_GP13_EINT */
 708 #define WM831X_IM_GP13_EINT_WIDTH                    1  /* IM_GP13_EINT */
 709 #define WM831X_IM_GP12_EINT                     0x0800  /* IM_GP12_EINT */
 710 #define WM831X_IM_GP12_EINT_MASK                0x0800  /* IM_GP12_EINT */
 711 #define WM831X_IM_GP12_EINT_SHIFT                   11  /* IM_GP12_EINT */
 712 #define WM831X_IM_GP12_EINT_WIDTH                    1  /* IM_GP12_EINT */
 713 #define WM831X_IM_GP11_EINT                     0x0400  /* IM_GP11_EINT */
 714 #define WM831X_IM_GP11_EINT_MASK                0x0400  /* IM_GP11_EINT */
 715 #define WM831X_IM_GP11_EINT_SHIFT                   10  /* IM_GP11_EINT */
 716 #define WM831X_IM_GP11_EINT_WIDTH                    1  /* IM_GP11_EINT */
 717 #define WM831X_IM_GP10_EINT                     0x0200  /* IM_GP10_EINT */
 718 #define WM831X_IM_GP10_EINT_MASK                0x0200  /* IM_GP10_EINT */
 719 #define WM831X_IM_GP10_EINT_SHIFT                    9  /* IM_GP10_EINT */
 720 #define WM831X_IM_GP10_EINT_WIDTH                    1  /* IM_GP10_EINT */
 721 #define WM831X_IM_GP9_EINT                      0x0100  /* IM_GP9_EINT */
 722 #define WM831X_IM_GP9_EINT_MASK                 0x0100  /* IM_GP9_EINT */
 723 #define WM831X_IM_GP9_EINT_SHIFT                     8  /* IM_GP9_EINT */
 724 #define WM831X_IM_GP9_EINT_WIDTH                     1  /* IM_GP9_EINT */
 725 #define WM831X_IM_GP8_EINT                      0x0080  /* IM_GP8_EINT */
 726 #define WM831X_IM_GP8_EINT_MASK                 0x0080  /* IM_GP8_EINT */
 727 #define WM831X_IM_GP8_EINT_SHIFT                     7  /* IM_GP8_EINT */
 728 #define WM831X_IM_GP8_EINT_WIDTH                     1  /* IM_GP8_EINT */
 729 #define WM831X_IM_GP7_EINT                      0x0040  /* IM_GP7_EINT */
 730 #define WM831X_IM_GP7_EINT_MASK                 0x0040  /* IM_GP7_EINT */
 731 #define WM831X_IM_GP7_EINT_SHIFT                     6  /* IM_GP7_EINT */
 732 #define WM831X_IM_GP7_EINT_WIDTH                     1  /* IM_GP7_EINT */
 733 #define WM831X_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
 734 #define WM831X_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
 735 #define WM831X_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
 736 #define WM831X_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
 737 #define WM831X_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
 738 #define WM831X_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
 739 #define WM831X_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
 740 #define WM831X_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
 741 #define WM831X_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
 742 #define WM831X_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
 743 #define WM831X_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
 744 #define WM831X_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
 745 #define WM831X_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
 746 #define WM831X_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
 747 #define WM831X_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
 748 #define WM831X_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
 749 #define WM831X_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
 750 #define WM831X_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
 751 #define WM831X_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
 752 #define WM831X_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
 753 #define WM831X_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
 754 #define WM831X_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
 755 #define WM831X_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
 756 #define WM831X_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
 757 
 758 
 759 #endif
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