This source file includes following definitions.
- as3722_read
- as3722_write
- as3722_block_read
- as3722_block_write
- as3722_update_bits
- as3722_irq_get_virq
1
2
3
4
5
6
7
8
9
10
11
12 #ifndef __LINUX_MFD_AS3722_H__
13 #define __LINUX_MFD_AS3722_H__
14
15 #include <linux/regmap.h>
16
17
18 #define AS3722_SD0_VOLTAGE_REG 0x00
19 #define AS3722_SD1_VOLTAGE_REG 0x01
20 #define AS3722_SD2_VOLTAGE_REG 0x02
21 #define AS3722_SD3_VOLTAGE_REG 0x03
22 #define AS3722_SD4_VOLTAGE_REG 0x04
23 #define AS3722_SD5_VOLTAGE_REG 0x05
24 #define AS3722_SD6_VOLTAGE_REG 0x06
25 #define AS3722_GPIO0_CONTROL_REG 0x08
26 #define AS3722_GPIO1_CONTROL_REG 0x09
27 #define AS3722_GPIO2_CONTROL_REG 0x0A
28 #define AS3722_GPIO3_CONTROL_REG 0x0B
29 #define AS3722_GPIO4_CONTROL_REG 0x0C
30 #define AS3722_GPIO5_CONTROL_REG 0x0D
31 #define AS3722_GPIO6_CONTROL_REG 0x0E
32 #define AS3722_GPIO7_CONTROL_REG 0x0F
33 #define AS3722_LDO0_VOLTAGE_REG 0x10
34 #define AS3722_LDO1_VOLTAGE_REG 0x11
35 #define AS3722_LDO2_VOLTAGE_REG 0x12
36 #define AS3722_LDO3_VOLTAGE_REG 0x13
37 #define AS3722_LDO4_VOLTAGE_REG 0x14
38 #define AS3722_LDO5_VOLTAGE_REG 0x15
39 #define AS3722_LDO6_VOLTAGE_REG 0x16
40 #define AS3722_LDO7_VOLTAGE_REG 0x17
41 #define AS3722_LDO9_VOLTAGE_REG 0x19
42 #define AS3722_LDO10_VOLTAGE_REG 0x1A
43 #define AS3722_LDO11_VOLTAGE_REG 0x1B
44 #define AS3722_GPIO_DEB1_REG 0x1E
45 #define AS3722_GPIO_DEB2_REG 0x1F
46 #define AS3722_GPIO_SIGNAL_OUT_REG 0x20
47 #define AS3722_GPIO_SIGNAL_IN_REG 0x21
48 #define AS3722_REG_SEQU_MOD1_REG 0x22
49 #define AS3722_REG_SEQU_MOD2_REG 0x23
50 #define AS3722_REG_SEQU_MOD3_REG 0x24
51 #define AS3722_SD_PHSW_CTRL_REG 0x27
52 #define AS3722_SD_PHSW_STATUS 0x28
53 #define AS3722_SD0_CONTROL_REG 0x29
54 #define AS3722_SD1_CONTROL_REG 0x2A
55 #define AS3722_SDmph_CONTROL_REG 0x2B
56 #define AS3722_SD23_CONTROL_REG 0x2C
57 #define AS3722_SD4_CONTROL_REG 0x2D
58 #define AS3722_SD5_CONTROL_REG 0x2E
59 #define AS3722_SD6_CONTROL_REG 0x2F
60 #define AS3722_SD_DVM_REG 0x30
61 #define AS3722_RESET_REASON_REG 0x31
62 #define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32
63 #define AS3722_STARTUP_CONTROL_REG 0x33
64 #define AS3722_RESET_TIMER_REG 0x34
65 #define AS3722_REFERENCE_CONTROL_REG 0x35
66 #define AS3722_RESET_CONTROL_REG 0x36
67 #define AS3722_OVER_TEMP_CONTROL_REG 0x37
68 #define AS3722_WATCHDOG_CONTROL_REG 0x38
69 #define AS3722_REG_STANDBY_MOD1_REG 0x39
70 #define AS3722_REG_STANDBY_MOD2_REG 0x3A
71 #define AS3722_REG_STANDBY_MOD3_REG 0x3B
72 #define AS3722_ENABLE_CTRL1_REG 0x3C
73 #define AS3722_ENABLE_CTRL2_REG 0x3D
74 #define AS3722_ENABLE_CTRL3_REG 0x3E
75 #define AS3722_ENABLE_CTRL4_REG 0x3F
76 #define AS3722_ENABLE_CTRL5_REG 0x40
77 #define AS3722_PWM_CONTROL_L_REG 0x41
78 #define AS3722_PWM_CONTROL_H_REG 0x42
79 #define AS3722_WATCHDOG_TIMER_REG 0x46
80 #define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48
81 #define AS3722_IOVOLTAGE_REG 0x49
82 #define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A
83 #define AS3722_SD_CONTROL_REG 0x4D
84 #define AS3722_LDOCONTROL0_REG 0x4E
85 #define AS3722_LDOCONTROL1_REG 0x4F
86 #define AS3722_SD0_PROTECT_REG 0x50
87 #define AS3722_SD6_PROTECT_REG 0x51
88 #define AS3722_PWM_VCONTROL1_REG 0x52
89 #define AS3722_PWM_VCONTROL2_REG 0x53
90 #define AS3722_PWM_VCONTROL3_REG 0x54
91 #define AS3722_PWM_VCONTROL4_REG 0x55
92 #define AS3722_BB_CHARGER_REG 0x57
93 #define AS3722_CTRL_SEQU1_REG 0x58
94 #define AS3722_CTRL_SEQU2_REG 0x59
95 #define AS3722_OVCURRENT_REG 0x5A
96 #define AS3722_OVCURRENT_DEB_REG 0x5B
97 #define AS3722_SDLV_DEB_REG 0x5C
98 #define AS3722_OC_PG_CTRL_REG 0x5D
99 #define AS3722_OC_PG_CTRL2_REG 0x5E
100 #define AS3722_CTRL_STATUS 0x5F
101 #define AS3722_RTC_CONTROL_REG 0x60
102 #define AS3722_RTC_SECOND_REG 0x61
103 #define AS3722_RTC_MINUTE_REG 0x62
104 #define AS3722_RTC_HOUR_REG 0x63
105 #define AS3722_RTC_DAY_REG 0x64
106 #define AS3722_RTC_MONTH_REG 0x65
107 #define AS3722_RTC_YEAR_REG 0x66
108 #define AS3722_RTC_ALARM_SECOND_REG 0x67
109 #define AS3722_RTC_ALARM_MINUTE_REG 0x68
110 #define AS3722_RTC_ALARM_HOUR_REG 0x69
111 #define AS3722_RTC_ALARM_DAY_REG 0x6A
112 #define AS3722_RTC_ALARM_MONTH_REG 0x6B
113 #define AS3722_RTC_ALARM_YEAR_REG 0x6C
114 #define AS3722_SRAM_REG 0x6D
115 #define AS3722_RTC_ACCESS_REG 0x6F
116 #define AS3722_RTC_STATUS_REG 0x73
117 #define AS3722_INTERRUPT_MASK1_REG 0x74
118 #define AS3722_INTERRUPT_MASK2_REG 0x75
119 #define AS3722_INTERRUPT_MASK3_REG 0x76
120 #define AS3722_INTERRUPT_MASK4_REG 0x77
121 #define AS3722_INTERRUPT_STATUS1_REG 0x78
122 #define AS3722_INTERRUPT_STATUS2_REG 0x79
123 #define AS3722_INTERRUPT_STATUS3_REG 0x7A
124 #define AS3722_INTERRUPT_STATUS4_REG 0x7B
125 #define AS3722_TEMP_STATUS_REG 0x7D
126 #define AS3722_ADC0_CONTROL_REG 0x80
127 #define AS3722_ADC1_CONTROL_REG 0x81
128 #define AS3722_ADC0_MSB_RESULT_REG 0x82
129 #define AS3722_ADC0_LSB_RESULT_REG 0x83
130 #define AS3722_ADC1_MSB_RESULT_REG 0x84
131 #define AS3722_ADC1_LSB_RESULT_REG 0x85
132 #define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86
133 #define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87
134 #define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88
135 #define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89
136 #define AS3722_ADC_CONFIGURATION_REG 0x8A
137 #define AS3722_ASIC_ID1_REG 0x90
138 #define AS3722_ASIC_ID2_REG 0x91
139 #define AS3722_LOCK_REG 0x9E
140 #define AS3722_FUSE7_REG 0xA7
141 #define AS3722_MAX_REGISTER 0xF4
142
143 #define AS3722_SD0_EXT_ENABLE_MASK 0x03
144 #define AS3722_SD1_EXT_ENABLE_MASK 0x0C
145 #define AS3722_SD2_EXT_ENABLE_MASK 0x30
146 #define AS3722_SD3_EXT_ENABLE_MASK 0xC0
147 #define AS3722_SD4_EXT_ENABLE_MASK 0x03
148 #define AS3722_SD5_EXT_ENABLE_MASK 0x0C
149 #define AS3722_SD6_EXT_ENABLE_MASK 0x30
150 #define AS3722_LDO0_EXT_ENABLE_MASK 0x03
151 #define AS3722_LDO1_EXT_ENABLE_MASK 0x0C
152 #define AS3722_LDO2_EXT_ENABLE_MASK 0x30
153 #define AS3722_LDO3_EXT_ENABLE_MASK 0xC0
154 #define AS3722_LDO4_EXT_ENABLE_MASK 0x03
155 #define AS3722_LDO5_EXT_ENABLE_MASK 0x0C
156 #define AS3722_LDO6_EXT_ENABLE_MASK 0x30
157 #define AS3722_LDO7_EXT_ENABLE_MASK 0xC0
158 #define AS3722_LDO9_EXT_ENABLE_MASK 0x0C
159 #define AS3722_LDO10_EXT_ENABLE_MASK 0x30
160 #define AS3722_LDO11_EXT_ENABLE_MASK 0xC0
161
162 #define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07
163 #define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01
164 #define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18
165 #define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03
166 #define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60
167 #define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05
168
169 #define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07
170 #define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01
171 #define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18
172 #define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03
173
174
175 #define AS3722_LDO_ILIMIT_MASK BIT(7)
176 #define AS3722_LDO_ILIMIT_BIT BIT(7)
177 #define AS3722_LDO0_VSEL_MASK 0x1F
178 #define AS3722_LDO0_VSEL_MIN 0x01
179 #define AS3722_LDO0_VSEL_MAX 0x12
180 #define AS3722_LDO0_NUM_VOLT 0x12
181 #define AS3722_LDO3_VSEL_MASK 0x3F
182 #define AS3722_LDO3_VSEL_MIN 0x01
183 #define AS3722_LDO3_VSEL_MAX 0x2D
184 #define AS3722_LDO3_NUM_VOLT 0x2D
185 #define AS3722_LDO6_VSEL_BYPASS 0x3F
186 #define AS3722_LDO_VSEL_MASK 0x7F
187 #define AS3722_LDO_VSEL_MIN 0x01
188 #define AS3722_LDO_VSEL_MAX 0x7F
189 #define AS3722_LDO_VSEL_DNU_MIN 0x25
190 #define AS3722_LDO_VSEL_DNU_MAX 0x3F
191 #define AS3722_LDO_NUM_VOLT 0x80
192
193 #define AS3722_LDO0_CTRL BIT(0)
194 #define AS3722_LDO1_CTRL BIT(1)
195 #define AS3722_LDO2_CTRL BIT(2)
196 #define AS3722_LDO3_CTRL BIT(3)
197 #define AS3722_LDO4_CTRL BIT(4)
198 #define AS3722_LDO5_CTRL BIT(5)
199 #define AS3722_LDO6_CTRL BIT(6)
200 #define AS3722_LDO7_CTRL BIT(7)
201 #define AS3722_LDO9_CTRL BIT(1)
202 #define AS3722_LDO10_CTRL BIT(2)
203 #define AS3722_LDO11_CTRL BIT(3)
204
205 #define AS3722_LDO3_MODE_MASK (3 << 6)
206 #define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6)
207 #define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0)
208 #define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1)
209 #define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2)
210 #define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3)
211
212 #define AS3722_SD_VSEL_MASK 0x7F
213 #define AS3722_SD0_VSEL_MIN 0x01
214 #define AS3722_SD0_VSEL_MAX 0x5A
215 #define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E
216 #define AS3722_SD2_VSEL_MIN 0x01
217 #define AS3722_SD2_VSEL_MAX 0x7F
218
219 #define AS3722_SDn_CTRL(n) BIT(n)
220
221 #define AS3722_SD0_MODE_FAST BIT(4)
222 #define AS3722_SD1_MODE_FAST BIT(4)
223 #define AS3722_SD2_MODE_FAST BIT(2)
224 #define AS3722_SD3_MODE_FAST BIT(6)
225 #define AS3722_SD4_MODE_FAST BIT(2)
226 #define AS3722_SD5_MODE_FAST BIT(2)
227 #define AS3722_SD6_MODE_FAST BIT(4)
228
229 #define AS3722_POWER_OFF BIT(1)
230
231 #define AS3722_INTERRUPT_MASK1_LID BIT(0)
232 #define AS3722_INTERRUPT_MASK1_ACOK BIT(1)
233 #define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2)
234 #define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3)
235 #define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4)
236 #define AS3722_INTERRUPT_MASK1_ONKEY BIT(5)
237 #define AS3722_INTERRUPT_MASK1_OVTMP BIT(6)
238 #define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7)
239
240 #define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0)
241 #define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1)
242 #define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2)
243 #define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3)
244 #define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4)
245 #define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5)
246 #define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6)
247 #define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7)
248
249 #define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0)
250 #define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1)
251 #define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2)
252 #define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3)
253 #define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4)
254 #define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5)
255 #define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6)
256 #define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7)
257
258 #define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0)
259 #define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1)
260 #define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2)
261 #define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3)
262 #define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4)
263 #define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5)
264 #define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6)
265 #define AS3722_INTERRUPT_MASK4_ADC BIT(7)
266
267 #define AS3722_ADC1_INTERVAL_TIME BIT(0)
268 #define AS3722_ADC1_INT_MODE_ON BIT(1)
269 #define AS3722_ADC_BUF_ON BIT(2)
270 #define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5)
271 #define AS3722_ADC1_INTEVAL_SCAN BIT(6)
272 #define AS3722_ADC1_INT_MASK BIT(7)
273
274 #define AS3722_ADC_MSB_VAL_MASK 0x7F
275 #define AS3722_ADC_LSB_VAL_MASK 0x07
276
277 #define AS3722_ADC0_CONV_START BIT(7)
278 #define AS3722_ADC0_CONV_NOTREADY BIT(7)
279 #define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F
280
281 #define AS3722_ADC1_CONV_START BIT(7)
282 #define AS3722_ADC1_CONV_NOTREADY BIT(7)
283 #define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F
284
285 #define AS3722_CTRL_SEQU1_AC_OK_PWR_ON BIT(0)
286
287
288 #define AS3722_GPIO_MODE_MASK 0x07
289 #define AS3722_GPIO_MODE_INPUT 0x00
290 #define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01
291 #define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02
292 #define AS3722_GPIO_MODE_ADC_IN 0x03
293 #define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04
294 #define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05
295 #define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06
296 #define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07
297 #define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK)
298
299 #define AS3722_GPIO_INV BIT(7)
300 #define AS3722_GPIO_IOSF_MASK 0x78
301 #define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3)
302 #define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0)
303 #define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1)
304 #define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2)
305 #define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3)
306 #define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4)
307 #define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5)
308 #define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6)
309 #define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7)
310 #define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8)
311 #define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9)
312 #define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11)
313 #define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12)
314 #define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13)
315 #define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14)
316
317 #define AS3722_GPIOn_SIGNAL(n) BIT(n)
318 #define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n)
319 #define AS3722_I2C_PULL_UP BIT(4)
320 #define AS3722_INT_PULL_UP BIT(5)
321
322 #define AS3722_RTC_REP_WAKEUP_EN BIT(0)
323 #define AS3722_RTC_ALARM_WAKEUP_EN BIT(1)
324 #define AS3722_RTC_ON BIT(2)
325 #define AS3722_RTC_IRQMODE BIT(3)
326 #define AS3722_RTC_CLK32K_OUT_EN BIT(5)
327
328 #define AS3722_WATCHDOG_TIMER_MAX 0x7F
329 #define AS3722_WATCHDOG_ON BIT(0)
330 #define AS3722_WATCHDOG_SW_SIG BIT(0)
331
332 #define AS3722_EXT_CONTROL_ENABLE1 0x1
333 #define AS3722_EXT_CONTROL_ENABLE2 0x2
334 #define AS3722_EXT_CONTROL_ENABLE3 0x3
335
336 #define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4)
337
338
339 enum as3722_irq {
340 AS3722_IRQ_LID,
341 AS3722_IRQ_ACOK,
342 AS3722_IRQ_ENABLE1,
343 AS3722_IRQ_OCCUR_ALARM_SD0,
344 AS3722_IRQ_ONKEY_LONG_PRESS,
345 AS3722_IRQ_ONKEY,
346 AS3722_IRQ_OVTMP,
347 AS3722_IRQ_LOWBAT,
348 AS3722_IRQ_SD0_LV,
349 AS3722_IRQ_SD1_LV,
350 AS3722_IRQ_SD2_LV,
351 AS3722_IRQ_PWM1_OV_PROT,
352 AS3722_IRQ_PWM2_OV_PROT,
353 AS3722_IRQ_ENABLE2,
354 AS3722_IRQ_SD6_LV,
355 AS3722_IRQ_RTC_REP,
356 AS3722_IRQ_RTC_ALARM,
357 AS3722_IRQ_GPIO1,
358 AS3722_IRQ_GPIO2,
359 AS3722_IRQ_GPIO3,
360 AS3722_IRQ_GPIO4,
361 AS3722_IRQ_GPIO5,
362 AS3722_IRQ_WATCHDOG,
363 AS3722_IRQ_ENABLE3,
364 AS3722_IRQ_TEMP_SD0_SHUTDOWN,
365 AS3722_IRQ_TEMP_SD1_SHUTDOWN,
366 AS3722_IRQ_TEMP_SD2_SHUTDOWN,
367 AS3722_IRQ_TEMP_SD0_ALARM,
368 AS3722_IRQ_TEMP_SD1_ALARM,
369 AS3722_IRQ_TEMP_SD6_ALARM,
370 AS3722_IRQ_OCCUR_ALARM_SD6,
371 AS3722_IRQ_ADC,
372 AS3722_IRQ_MAX,
373 };
374
375 struct as3722 {
376 struct device *dev;
377 struct regmap *regmap;
378 int chip_irq;
379 unsigned long irq_flags;
380 bool en_intern_int_pullup;
381 bool en_intern_i2c_pullup;
382 bool en_ac_ok_pwr_on;
383 struct regmap_irq_chip_data *irq_data;
384 };
385
386 static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest)
387 {
388 return regmap_read(as3722->regmap, reg, dest);
389 }
390
391 static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value)
392 {
393 return regmap_write(as3722->regmap, reg, value);
394 }
395
396 static inline int as3722_block_read(struct as3722 *as3722, u32 reg,
397 int count, u8 *buf)
398 {
399 return regmap_bulk_read(as3722->regmap, reg, buf, count);
400 }
401
402 static inline int as3722_block_write(struct as3722 *as3722, u32 reg,
403 int count, u8 *data)
404 {
405 return regmap_bulk_write(as3722->regmap, reg, data, count);
406 }
407
408 static inline int as3722_update_bits(struct as3722 *as3722, u32 reg,
409 u32 mask, u8 val)
410 {
411 return regmap_update_bits(as3722->regmap, reg, mask, val);
412 }
413
414 static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq)
415 {
416 return regmap_irq_get_virq(as3722->irq_data, irq);
417 }
418 #endif