This source file includes following definitions.
- dev_to_pcf50633
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9 #ifndef __LINUX_MFD_PCF50633_CORE_H
10 #define __LINUX_MFD_PCF50633_CORE_H
11
12 #include <linux/i2c.h>
13 #include <linux/workqueue.h>
14 #include <linux/regulator/driver.h>
15 #include <linux/regulator/machine.h>
16 #include <linux/power_supply.h>
17 #include <linux/mfd/pcf50633/backlight.h>
18
19 struct pcf50633;
20 struct regmap;
21
22 #define PCF50633_NUM_REGULATORS 11
23
24 struct pcf50633_platform_data {
25 struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
26
27 char **batteries;
28 int num_batteries;
29
30
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32
33
34
35 int charger_reference_current_ma;
36
37
38 void (*probe_done)(struct pcf50633 *);
39 void (*mbc_event_callback)(struct pcf50633 *, int);
40 void (*regulator_registered)(struct pcf50633 *, int);
41 void (*force_shutdown)(struct pcf50633 *);
42
43 u8 resumers[5];
44
45 struct pcf50633_bl_platform_data *backlight_data;
46 };
47
48 struct pcf50633_irq {
49 void (*handler) (int, void *);
50 void *data;
51 };
52
53 int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
54 void (*handler) (int, void *), void *data);
55 int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
56
57 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
58 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
59 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
60
61 int pcf50633_read_block(struct pcf50633 *, u8 reg,
62 int nr_regs, u8 *data);
63 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
64 int nr_regs, u8 *data);
65 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
66 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
67
68 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
69 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
70
71
72
73 #define PCF50633_REG_INT1 0x02
74 #define PCF50633_REG_INT2 0x03
75 #define PCF50633_REG_INT3 0x04
76 #define PCF50633_REG_INT4 0x05
77 #define PCF50633_REG_INT5 0x06
78
79 #define PCF50633_REG_INT1M 0x07
80 #define PCF50633_REG_INT2M 0x08
81 #define PCF50633_REG_INT3M 0x09
82 #define PCF50633_REG_INT4M 0x0a
83 #define PCF50633_REG_INT5M 0x0b
84
85 enum {
86
87 PCF50633_IRQ_ADPINS,
88 PCF50633_IRQ_ADPREM,
89 PCF50633_IRQ_USBINS,
90 PCF50633_IRQ_USBREM,
91 PCF50633_IRQ_RESERVED1,
92 PCF50633_IRQ_RESERVED2,
93 PCF50633_IRQ_ALARM,
94 PCF50633_IRQ_SECOND,
95 PCF50633_IRQ_ONKEYR,
96 PCF50633_IRQ_ONKEYF,
97 PCF50633_IRQ_EXTON1R,
98 PCF50633_IRQ_EXTON1F,
99 PCF50633_IRQ_EXTON2R,
100 PCF50633_IRQ_EXTON2F,
101 PCF50633_IRQ_EXTON3R,
102 PCF50633_IRQ_EXTON3F,
103 PCF50633_IRQ_BATFULL,
104 PCF50633_IRQ_CHGHALT,
105 PCF50633_IRQ_THLIMON,
106 PCF50633_IRQ_THLIMOFF,
107 PCF50633_IRQ_USBLIMON,
108 PCF50633_IRQ_USBLIMOFF,
109 PCF50633_IRQ_ADCRDY,
110 PCF50633_IRQ_ONKEY1S,
111 PCF50633_IRQ_LOWSYS,
112 PCF50633_IRQ_LOWBAT,
113 PCF50633_IRQ_HIGHTMP,
114 PCF50633_IRQ_AUTOPWRFAIL,
115 PCF50633_IRQ_DWN1PWRFAIL,
116 PCF50633_IRQ_DWN2PWRFAIL,
117 PCF50633_IRQ_LEDPWRFAIL,
118 PCF50633_IRQ_LEDOVP,
119 PCF50633_IRQ_LDO1PWRFAIL,
120 PCF50633_IRQ_LDO2PWRFAIL,
121 PCF50633_IRQ_LDO3PWRFAIL,
122 PCF50633_IRQ_LDO4PWRFAIL,
123 PCF50633_IRQ_LDO5PWRFAIL,
124 PCF50633_IRQ_LDO6PWRFAIL,
125 PCF50633_IRQ_HCLDOPWRFAIL,
126 PCF50633_IRQ_HCLDOOVL,
127
128
129 PCF50633_NUM_IRQ,
130 };
131
132 struct pcf50633 {
133 struct device *dev;
134 struct regmap *regmap;
135
136 struct pcf50633_platform_data *pdata;
137 int irq;
138 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
139 struct work_struct irq_work;
140 struct workqueue_struct *work_queue;
141 struct mutex lock;
142
143 u8 mask_regs[5];
144
145 u8 suspend_irq_masks[5];
146 u8 resume_reason[5];
147 int is_suspended;
148
149 int onkey1s_held;
150
151 struct platform_device *rtc_pdev;
152 struct platform_device *mbc_pdev;
153 struct platform_device *adc_pdev;
154 struct platform_device *input_pdev;
155 struct platform_device *bl_pdev;
156 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
157 };
158
159 enum pcf50633_reg_int1 {
160 PCF50633_INT1_ADPINS = 0x01,
161 PCF50633_INT1_ADPREM = 0x02,
162 PCF50633_INT1_USBINS = 0x04,
163 PCF50633_INT1_USBREM = 0x08,
164
165 PCF50633_INT1_ALARM = 0x40,
166 PCF50633_INT1_SECOND = 0x80,
167 };
168
169 enum pcf50633_reg_int2 {
170 PCF50633_INT2_ONKEYR = 0x01,
171 PCF50633_INT2_ONKEYF = 0x02,
172 PCF50633_INT2_EXTON1R = 0x04,
173 PCF50633_INT2_EXTON1F = 0x08,
174 PCF50633_INT2_EXTON2R = 0x10,
175 PCF50633_INT2_EXTON2F = 0x20,
176 PCF50633_INT2_EXTON3R = 0x40,
177 PCF50633_INT2_EXTON3F = 0x80,
178 };
179
180 enum pcf50633_reg_int3 {
181 PCF50633_INT3_BATFULL = 0x01,
182 PCF50633_INT3_CHGHALT = 0x02,
183 PCF50633_INT3_THLIMON = 0x04,
184 PCF50633_INT3_THLIMOFF = 0x08,
185 PCF50633_INT3_USBLIMON = 0x10,
186 PCF50633_INT3_USBLIMOFF = 0x20,
187 PCF50633_INT3_ADCRDY = 0x40,
188 PCF50633_INT3_ONKEY1S = 0x80,
189 };
190
191 enum pcf50633_reg_int4 {
192 PCF50633_INT4_LOWSYS = 0x01,
193 PCF50633_INT4_LOWBAT = 0x02,
194 PCF50633_INT4_HIGHTMP = 0x04,
195 PCF50633_INT4_AUTOPWRFAIL = 0x08,
196 PCF50633_INT4_DWN1PWRFAIL = 0x10,
197 PCF50633_INT4_DWN2PWRFAIL = 0x20,
198 PCF50633_INT4_LEDPWRFAIL = 0x40,
199 PCF50633_INT4_LEDOVP = 0x80,
200 };
201
202 enum pcf50633_reg_int5 {
203 PCF50633_INT5_LDO1PWRFAIL = 0x01,
204 PCF50633_INT5_LDO2PWRFAIL = 0x02,
205 PCF50633_INT5_LDO3PWRFAIL = 0x04,
206 PCF50633_INT5_LDO4PWRFAIL = 0x08,
207 PCF50633_INT5_LDO5PWRFAIL = 0x10,
208 PCF50633_INT5_LDO6PWRFAIL = 0x20,
209 PCF50633_INT5_HCLDOPWRFAIL = 0x40,
210 PCF50633_INT5_HCLDOOVL = 0x80,
211 };
212
213
214 #define PCF50633_REG_OOCSHDWN 0x0c
215
216
217 #define PCF50633_REG_LEDOUT 0x28
218 #define PCF50633_REG_LEDENA 0x29
219 #define PCF50633_REG_LEDCTL 0x2a
220 #define PCF50633_REG_LEDDIM 0x2b
221
222 static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
223 {
224 return dev_get_drvdata(dev);
225 }
226
227 int pcf50633_irq_init(struct pcf50633 *pcf, int irq);
228 void pcf50633_irq_free(struct pcf50633 *pcf);
229 #ifdef CONFIG_PM
230 int pcf50633_irq_suspend(struct pcf50633 *pcf);
231 int pcf50633_irq_resume(struct pcf50633 *pcf);
232 #endif
233
234 #endif