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7 #ifndef __MFD_MT6397_CORE_H__
8 #define __MFD_MT6397_CORE_H__
9
10 #include <linux/mutex.h>
11
12 enum chip_id {
13 MT6323_CHIP_ID = 0x23,
14 MT6391_CHIP_ID = 0x91,
15 MT6397_CHIP_ID = 0x97,
16 };
17
18 enum mt6397_irq_numbers {
19 MT6397_IRQ_SPKL_AB = 0,
20 MT6397_IRQ_SPKR_AB,
21 MT6397_IRQ_SPKL,
22 MT6397_IRQ_SPKR,
23 MT6397_IRQ_BAT_L,
24 MT6397_IRQ_BAT_H,
25 MT6397_IRQ_FG_BAT_L,
26 MT6397_IRQ_FG_BAT_H,
27 MT6397_IRQ_WATCHDOG,
28 MT6397_IRQ_PWRKEY,
29 MT6397_IRQ_THR_L,
30 MT6397_IRQ_THR_H,
31 MT6397_IRQ_VBATON_UNDET,
32 MT6397_IRQ_BVALID_DET,
33 MT6397_IRQ_CHRDET,
34 MT6397_IRQ_OV,
35 MT6397_IRQ_LDO,
36 MT6397_IRQ_HOMEKEY,
37 MT6397_IRQ_ACCDET,
38 MT6397_IRQ_AUDIO,
39 MT6397_IRQ_RTC,
40 MT6397_IRQ_PWRKEY_RSTB,
41 MT6397_IRQ_HDMI_SIFM,
42 MT6397_IRQ_HDMI_CEC,
43 MT6397_IRQ_VCA15,
44 MT6397_IRQ_VSRMCA15,
45 MT6397_IRQ_VCORE,
46 MT6397_IRQ_VGPU,
47 MT6397_IRQ_VIO18,
48 MT6397_IRQ_VPCA7,
49 MT6397_IRQ_VSRMCA7,
50 MT6397_IRQ_VDRM,
51 MT6397_IRQ_NR,
52 };
53
54 struct mt6397_chip {
55 struct device *dev;
56 struct regmap *regmap;
57 int irq;
58 struct irq_domain *irq_domain;
59 struct mutex irqlock;
60 u16 wake_mask[2];
61 u16 irq_masks_cur[2];
62 u16 irq_masks_cache[2];
63 u16 int_con[2];
64 u16 int_status[2];
65 u16 chip_id;
66 };
67
68 int mt6397_irq_init(struct mt6397_chip *chip);
69
70 #endif