1
2 #ifndef _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
3 #define _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
4
5 struct regmap;
6 struct clk;
7
8 struct mx25_tsadc {
9 struct regmap *regs;
10 struct irq_domain *domain;
11 struct clk *clk;
12 };
13
14 #define MX25_TSC_TGCR 0x00
15 #define MX25_TSC_TGSR 0x04
16 #define MX25_TSC_TICR 0x08
17
18
19 #define MX25_ADCQ_FIFO 0x00
20 #define MX25_ADCQ_CR 0x04
21 #define MX25_ADCQ_SR 0x08
22 #define MX25_ADCQ_MR 0x0c
23 #define MX25_ADCQ_ITEM_7_0 0x20
24 #define MX25_ADCQ_ITEM_15_8 0x24
25 #define MX25_ADCQ_CFG(n) (0x40 + ((n) * 0x4))
26
27 #define MX25_ADCQ_MR_MASK 0xffffffff
28
29
30 #define MX25_TGCR_PDBTIME(x) ((x) << 25)
31 #define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25)
32 #define MX25_TGCR_PDBEN BIT(24)
33 #define MX25_TGCR_PDEN BIT(23)
34 #define MX25_TGCR_ADCCLKCFG(x) ((x) << 16)
35 #define MX25_TGCR_GET_ADCCLK(x) (((x) >> 16) & 0x1f)
36 #define MX25_TGCR_INTREFEN BIT(10)
37 #define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8)
38 #define MX25_TGCR_POWERMODE_SAVE (1 << 8)
39 #define MX25_TGCR_POWERMODE_ON (2 << 8)
40 #define MX25_TGCR_STLC BIT(5)
41 #define MX25_TGCR_SLPC BIT(4)
42 #define MX25_TGCR_FUNC_RST BIT(2)
43 #define MX25_TGCR_TSC_RST BIT(1)
44 #define MX25_TGCR_CLK_EN BIT(0)
45
46
47 #define MX25_TGSR_SLP_INT BIT(2)
48 #define MX25_TGSR_GCQ_INT BIT(1)
49 #define MX25_TGSR_TCQ_INT BIT(0)
50
51
52 #define _MX25_ADCQ_ITEM(item, x) ((x) << ((item) * 4))
53 #define MX25_ADCQ_ITEM(item, x) ((item) >= 8 ? \
54 _MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x)))
55
56
57 #define MX25_ADCQ_FIFO_DATA(x) (((x) >> 4) & 0xfff)
58 #define MX25_ADCQ_FIFO_ID(x) ((x) & 0xf)
59
60
61 #define MX25_ADCQ_CR_PDCFG_LEVEL BIT(19)
62 #define MX25_ADCQ_CR_PDMSK BIT(18)
63 #define MX25_ADCQ_CR_FRST BIT(17)
64 #define MX25_ADCQ_CR_QRST BIT(16)
65 #define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12)
66 #define MX25_ADCQ_CR_RWAIT(x) ((x) << 12)
67 #define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8)
68 #define MX25_ADCQ_CR_WMRK(x) ((x) << 8)
69 #define MX25_ADCQ_CR_LITEMID_MASK (0xf << 4)
70 #define MX25_ADCQ_CR_LITEMID(x) ((x) << 4)
71 #define MX25_ADCQ_CR_RPT BIT(3)
72 #define MX25_ADCQ_CR_FQS BIT(2)
73 #define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0)
74 #define MX25_ADCQ_CR_QSM_PD 0x1
75 #define MX25_ADCQ_CR_QSM_FQS 0x2
76 #define MX25_ADCQ_CR_QSM_FQS_PD 0x3
77
78
79 #define MX25_ADCQ_SR_FDRY BIT(15)
80 #define MX25_ADCQ_SR_FULL BIT(14)
81 #define MX25_ADCQ_SR_EMPT BIT(13)
82 #define MX25_ADCQ_SR_FDN(x) (((x) >> 8) & 0x1f)
83 #define MX25_ADCQ_SR_FRR BIT(6)
84 #define MX25_ADCQ_SR_FUR BIT(5)
85 #define MX25_ADCQ_SR_FOR BIT(4)
86 #define MX25_ADCQ_SR_EOQ BIT(1)
87 #define MX25_ADCQ_SR_PD BIT(0)
88
89
90 #define MX25_ADCQ_MR_FDRY_DMA BIT(31)
91 #define MX25_ADCQ_MR_FER_DMA BIT(22)
92 #define MX25_ADCQ_MR_FUR_DMA BIT(21)
93 #define MX25_ADCQ_MR_FOR_DMA BIT(20)
94 #define MX25_ADCQ_MR_EOQ_DMA BIT(17)
95 #define MX25_ADCQ_MR_PD_DMA BIT(16)
96 #define MX25_ADCQ_MR_FDRY_IRQ BIT(15)
97 #define MX25_ADCQ_MR_FER_IRQ BIT(6)
98 #define MX25_ADCQ_MR_FUR_IRQ BIT(5)
99 #define MX25_ADCQ_MR_FOR_IRQ BIT(4)
100 #define MX25_ADCQ_MR_EOQ_IRQ BIT(1)
101 #define MX25_ADCQ_MR_PD_IRQ BIT(0)
102
103
104 #define MX25_ADCQ_CFG_SETTLING_TIME(x) ((x) << 24)
105 #define MX25_ADCQ_CFG_IGS (1 << 20)
106 #define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16)
107 #define MX25_ADCQ_CFG_NOS(x) (((x) - 1) << 16)
108 #define MX25_ADCQ_CFG_WIPER (1 << 15)
109 #define MX25_ADCQ_CFG_YNLR (1 << 14)
110 #define MX25_ADCQ_CFG_YPLL_HIGH (0 << 12)
111 #define MX25_ADCQ_CFG_YPLL_OFF (1 << 12)
112 #define MX25_ADCQ_CFG_YPLL_LOW (3 << 12)
113 #define MX25_ADCQ_CFG_XNUR_HIGH (0 << 10)
114 #define MX25_ADCQ_CFG_XNUR_OFF (1 << 10)
115 #define MX25_ADCQ_CFG_XNUR_LOW (3 << 10)
116 #define MX25_ADCQ_CFG_XPUL_HIGH (0 << 9)
117 #define MX25_ADCQ_CFG_XPUL_OFF (1 << 9)
118 #define MX25_ADCQ_CFG_REFP(sel) ((sel) << 7)
119 #define MX25_ADCQ_CFG_REFP_YP MX25_ADCQ_CFG_REFP(0)
120 #define MX25_ADCQ_CFG_REFP_XP MX25_ADCQ_CFG_REFP(1)
121 #define MX25_ADCQ_CFG_REFP_EXT MX25_ADCQ_CFG_REFP(2)
122 #define MX25_ADCQ_CFG_REFP_INT MX25_ADCQ_CFG_REFP(3)
123 #define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7)
124 #define MX25_ADCQ_CFG_IN(sel) ((sel) << 4)
125 #define MX25_ADCQ_CFG_IN_XP MX25_ADCQ_CFG_IN(0)
126 #define MX25_ADCQ_CFG_IN_YP MX25_ADCQ_CFG_IN(1)
127 #define MX25_ADCQ_CFG_IN_XN MX25_ADCQ_CFG_IN(2)
128 #define MX25_ADCQ_CFG_IN_YN MX25_ADCQ_CFG_IN(3)
129 #define MX25_ADCQ_CFG_IN_WIPER MX25_ADCQ_CFG_IN(4)
130 #define MX25_ADCQ_CFG_IN_AUX0 MX25_ADCQ_CFG_IN(5)
131 #define MX25_ADCQ_CFG_IN_AUX1 MX25_ADCQ_CFG_IN(6)
132 #define MX25_ADCQ_CFG_IN_AUX2 MX25_ADCQ_CFG_IN(7)
133 #define MX25_ADCQ_CFG_REFN(sel) ((sel) << 2)
134 #define MX25_ADCQ_CFG_REFN_XN MX25_ADCQ_CFG_REFN(0)
135 #define MX25_ADCQ_CFG_REFN_YN MX25_ADCQ_CFG_REFN(1)
136 #define MX25_ADCQ_CFG_REFN_NGND MX25_ADCQ_CFG_REFN(2)
137 #define MX25_ADCQ_CFG_REFN_NGND2 MX25_ADCQ_CFG_REFN(3)
138 #define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2)
139 #define MX25_ADCQ_CFG_PENIACK (1 << 1)
140
141 #endif