root/include/linux/mfd/syscon/atmel-mc.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2005 Ivan Kokshaysky
   4  * Copyright (C) SAN People
   5  *
   6  * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
   7  * registers.
   8  * Based on AT91RM9200 datasheet revision E.
   9  */
  10 
  11 #ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
  12 #define _LINUX_MFD_SYSCON_ATMEL_MC_H_
  13 
  14 /* Memory Controller */
  15 #define AT91_MC_RCR                     0x00
  16 #define AT91_MC_RCB                     BIT(0)
  17 
  18 #define AT91_MC_ASR                     0x04
  19 #define AT91_MC_UNADD                   BIT(0)
  20 #define AT91_MC_MISADD                  BIT(1)
  21 #define AT91_MC_ABTSZ                   GENMASK(9, 8)
  22 #define AT91_MC_ABTSZ_BYTE              (0 << 8)
  23 #define AT91_MC_ABTSZ_HALFWORD          (1 << 8)
  24 #define AT91_MC_ABTSZ_WORD              (2 << 8)
  25 #define AT91_MC_ABTTYP                  GENMASK(11, 10)
  26 #define AT91_MC_ABTTYP_DATAREAD         (0 << 10)
  27 #define AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
  28 #define AT91_MC_ABTTYP_FETCH            (2 << 10)
  29 #define AT91_MC_MST(n)                  BIT(16 + (n))
  30 #define AT91_MC_SVMST(n)                BIT(24 + (n))
  31 
  32 #define AT91_MC_AASR                    0x08
  33 
  34 #define AT91_MC_MPR                     0x0c
  35 #define AT91_MPR_MSTP(n)                GENMASK(2 + ((x) * 4), ((x) * 4))
  36 
  37 /* External Bus Interface (EBI) registers */
  38 #define AT91_MC_EBI_CSA                 0x60
  39 #define AT91_MC_EBI_CS(n)               BIT(x)
  40 #define AT91_MC_EBI_NUM_CS              8
  41 
  42 #define AT91_MC_EBI_CFGR                0x64
  43 #define AT91_MC_EBI_DBPUC               BIT(0)
  44 
  45 /* Static Memory Controller (SMC) registers */
  46 #define AT91_MC_SMC_CSR(n)              (0x70 + ((n) * 4))
  47 #define AT91_MC_SMC_NWS                 GENMASK(6, 0)
  48 #define AT91_MC_SMC_NWS_(x)             ((x) << 0)
  49 #define AT91_MC_SMC_WSEN                BIT(7)
  50 #define AT91_MC_SMC_TDF                 GENMASK(11, 8)
  51 #define AT91_MC_SMC_TDF_(x)             ((x) << 8)
  52 #define AT91_MC_SMC_TDF_MAX             0xf
  53 #define AT91_MC_SMC_BAT                 BIT(12)
  54 #define AT91_MC_SMC_DBW                 GENMASK(14, 13)
  55 #define AT91_MC_SMC_DBW_16              (1 << 13)
  56 #define AT91_MC_SMC_DBW_8               (2 << 13)
  57 #define AT91_MC_SMC_DPR                 BIT(15)
  58 #define AT91_MC_SMC_ACSS                GENMASK(17, 16)
  59 #define AT91_MC_SMC_ACSS_(x)            ((x) << 16)
  60 #define AT91_MC_SMC_ACSS_MAX            3
  61 #define AT91_MC_SMC_RWSETUP             GENMASK(26, 24)
  62 #define AT91_MC_SMC_RWSETUP_(x)         ((x) << 24)
  63 #define AT91_MC_SMC_RWHOLD              GENMASK(30, 28)
  64 #define AT91_MC_SMC_RWHOLD_(x)          ((x) << 28)
  65 #define AT91_MC_SMC_RWHOLDSETUP_MAX     7
  66 
  67 /* SDRAM Controller registers */
  68 #define AT91_MC_SDRAMC_MR               0x90
  69 #define AT91_MC_SDRAMC_MODE             GENMASK(3, 0)
  70 #define AT91_MC_SDRAMC_MODE_NORMAL      (0 << 0)
  71 #define AT91_MC_SDRAMC_MODE_NOP         (1 << 0)
  72 #define AT91_MC_SDRAMC_MODE_PRECHARGE   (2 << 0)
  73 #define AT91_MC_SDRAMC_MODE_LMR         (3 << 0)
  74 #define AT91_MC_SDRAMC_MODE_REFRESH     (4 << 0)
  75 #define AT91_MC_SDRAMC_DBW_16           BIT(4)
  76 
  77 #define AT91_MC_SDRAMC_TR               0x94
  78 #define AT91_MC_SDRAMC_COUNT            GENMASK(11, 0)
  79 
  80 #define AT91_MC_SDRAMC_CR               0x98
  81 #define AT91_MC_SDRAMC_NC               GENMASK(1, 0)
  82 #define AT91_MC_SDRAMC_NC_8             (0 << 0)
  83 #define AT91_MC_SDRAMC_NC_9             (1 << 0)
  84 #define AT91_MC_SDRAMC_NC_10            (2 << 0)
  85 #define AT91_MC_SDRAMC_NC_11            (3 << 0)
  86 #define AT91_MC_SDRAMC_NR               GENMASK(3, 2)
  87 #define AT91_MC_SDRAMC_NR_11            (0 << 2)
  88 #define AT91_MC_SDRAMC_NR_12            (1 << 2)
  89 #define AT91_MC_SDRAMC_NR_13            (2 << 2)
  90 #define AT91_MC_SDRAMC_NB               BIT(4)
  91 #define AT91_MC_SDRAMC_NB_2             (0 << 4)
  92 #define AT91_MC_SDRAMC_NB_4             (1 << 4)
  93 #define AT91_MC_SDRAMC_CAS              GENMASK(6, 5)
  94 #define AT91_MC_SDRAMC_CAS_2            (2 << 5)
  95 #define AT91_MC_SDRAMC_TWR              GENMASK(10,  7)
  96 #define AT91_MC_SDRAMC_TRC              GENMASK(14, 11)
  97 #define AT91_MC_SDRAMC_TRP              GENMASK(18, 15)
  98 #define AT91_MC_SDRAMC_TRCD             GENMASK(22, 19)
  99 #define AT91_MC_SDRAMC_TRAS             GENMASK(26, 23)
 100 #define AT91_MC_SDRAMC_TXSR             GENMASK(30, 27)
 101 
 102 #define AT91_MC_SDRAMC_SRR              0x9c
 103 #define AT91_MC_SDRAMC_SRCB             BIT(0)
 104 
 105 #define AT91_MC_SDRAMC_LPR              0xa0
 106 #define AT91_MC_SDRAMC_LPCB             BIT(0)
 107 
 108 #define AT91_MC_SDRAMC_IER              0xa4
 109 #define AT91_MC_SDRAMC_IDR              0xa8
 110 #define AT91_MC_SDRAMC_IMR              0xac
 111 #define AT91_MC_SDRAMC_ISR              0xb0
 112 #define AT91_MC_SDRAMC_RES              BIT(0)
 113 
 114 /* Burst Flash Controller register */
 115 #define AT91_MC_BFC_MR                  0xc0
 116 #define AT91_MC_BFC_BFCOM               GENMASK(1, 0)
 117 #define AT91_MC_BFC_BFCOM_DISABLED      (0 << 0)
 118 #define AT91_MC_BFC_BFCOM_ASYNC         (1 << 0)
 119 #define AT91_MC_BFC_BFCOM_BURST         (2 << 0)
 120 #define AT91_MC_BFC_BFCC                GENMASK(3, 2)
 121 #define AT91_MC_BFC_BFCC_MCK            (1 << 2)
 122 #define AT91_MC_BFC_BFCC_DIV2           (2 << 2)
 123 #define AT91_MC_BFC_BFCC_DIV4           (3 << 2)
 124 #define AT91_MC_BFC_AVL                 GENMASK(7,  4)
 125 #define AT91_MC_BFC_PAGES               GENMASK(10, 8)
 126 #define AT91_MC_BFC_PAGES_NO_PAGE       (0 << 8)
 127 #define AT91_MC_BFC_PAGES_16            (1 << 8)
 128 #define AT91_MC_BFC_PAGES_32            (2 << 8)
 129 #define AT91_MC_BFC_PAGES_64            (3 << 8)
 130 #define AT91_MC_BFC_PAGES_128           (4 << 8)
 131 #define AT91_MC_BFC_PAGES_256           (5 << 8)
 132 #define AT91_MC_BFC_PAGES_512           (6 << 8)
 133 #define AT91_MC_BFC_PAGES_1024          (7 << 8)
 134 #define AT91_MC_BFC_OEL                 GENMASK(13, 12)
 135 #define AT91_MC_BFC_BAAEN               BIT(16)
 136 #define AT91_MC_BFC_BFOEH               BIT(17)
 137 #define AT91_MC_BFC_MUXEN               BIT(18)
 138 #define AT91_MC_BFC_RDYEN               BIT(19)
 139 
 140 #endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */