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9 #ifndef __LINUX_MFD_MAX8997_PRIV_H
10 #define __LINUX_MFD_MAX8997_PRIV_H
11
12 #include <linux/i2c.h>
13 #include <linux/export.h>
14 #include <linux/irqdomain.h>
15
16 #define MAX8997_REG_INVALID (0xff)
17
18 enum max8997_pmic_reg {
19 MAX8997_REG_PMIC_ID0 = 0x00,
20 MAX8997_REG_PMIC_ID1 = 0x01,
21 MAX8997_REG_INTSRC = 0x02,
22 MAX8997_REG_INT1 = 0x03,
23 MAX8997_REG_INT2 = 0x04,
24 MAX8997_REG_INT3 = 0x05,
25 MAX8997_REG_INT4 = 0x06,
26
27 MAX8997_REG_INT1MSK = 0x08,
28 MAX8997_REG_INT2MSK = 0x09,
29 MAX8997_REG_INT3MSK = 0x0a,
30 MAX8997_REG_INT4MSK = 0x0b,
31
32 MAX8997_REG_STATUS1 = 0x0d,
33 MAX8997_REG_STATUS2 = 0x0e,
34 MAX8997_REG_STATUS3 = 0x0f,
35 MAX8997_REG_STATUS4 = 0x10,
36
37 MAX8997_REG_MAINCON1 = 0x13,
38 MAX8997_REG_MAINCON2 = 0x14,
39 MAX8997_REG_BUCKRAMP = 0x15,
40
41 MAX8997_REG_BUCK1CTRL = 0x18,
42 MAX8997_REG_BUCK1DVS1 = 0x19,
43 MAX8997_REG_BUCK1DVS2 = 0x1a,
44 MAX8997_REG_BUCK1DVS3 = 0x1b,
45 MAX8997_REG_BUCK1DVS4 = 0x1c,
46 MAX8997_REG_BUCK1DVS5 = 0x1d,
47 MAX8997_REG_BUCK1DVS6 = 0x1e,
48 MAX8997_REG_BUCK1DVS7 = 0x1f,
49 MAX8997_REG_BUCK1DVS8 = 0x20,
50 MAX8997_REG_BUCK2CTRL = 0x21,
51 MAX8997_REG_BUCK2DVS1 = 0x22,
52 MAX8997_REG_BUCK2DVS2 = 0x23,
53 MAX8997_REG_BUCK2DVS3 = 0x24,
54 MAX8997_REG_BUCK2DVS4 = 0x25,
55 MAX8997_REG_BUCK2DVS5 = 0x26,
56 MAX8997_REG_BUCK2DVS6 = 0x27,
57 MAX8997_REG_BUCK2DVS7 = 0x28,
58 MAX8997_REG_BUCK2DVS8 = 0x29,
59 MAX8997_REG_BUCK3CTRL = 0x2a,
60 MAX8997_REG_BUCK3DVS = 0x2b,
61 MAX8997_REG_BUCK4CTRL = 0x2c,
62 MAX8997_REG_BUCK4DVS = 0x2d,
63 MAX8997_REG_BUCK5CTRL = 0x2e,
64 MAX8997_REG_BUCK5DVS1 = 0x2f,
65 MAX8997_REG_BUCK5DVS2 = 0x30,
66 MAX8997_REG_BUCK5DVS3 = 0x31,
67 MAX8997_REG_BUCK5DVS4 = 0x32,
68 MAX8997_REG_BUCK5DVS5 = 0x33,
69 MAX8997_REG_BUCK5DVS6 = 0x34,
70 MAX8997_REG_BUCK5DVS7 = 0x35,
71 MAX8997_REG_BUCK5DVS8 = 0x36,
72 MAX8997_REG_BUCK6CTRL = 0x37,
73 MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
74 MAX8997_REG_BUCK7CTRL = 0x39,
75 MAX8997_REG_BUCK7DVS = 0x3a,
76 MAX8997_REG_LDO1CTRL = 0x3b,
77 MAX8997_REG_LDO2CTRL = 0x3c,
78 MAX8997_REG_LDO3CTRL = 0x3d,
79 MAX8997_REG_LDO4CTRL = 0x3e,
80 MAX8997_REG_LDO5CTRL = 0x3f,
81 MAX8997_REG_LDO6CTRL = 0x40,
82 MAX8997_REG_LDO7CTRL = 0x41,
83 MAX8997_REG_LDO8CTRL = 0x42,
84 MAX8997_REG_LDO9CTRL = 0x43,
85 MAX8997_REG_LDO10CTRL = 0x44,
86 MAX8997_REG_LDO11CTRL = 0x45,
87 MAX8997_REG_LDO12CTRL = 0x46,
88 MAX8997_REG_LDO13CTRL = 0x47,
89 MAX8997_REG_LDO14CTRL = 0x48,
90 MAX8997_REG_LDO15CTRL = 0x49,
91 MAX8997_REG_LDO16CTRL = 0x4a,
92 MAX8997_REG_LDO17CTRL = 0x4b,
93 MAX8997_REG_LDO18CTRL = 0x4c,
94 MAX8997_REG_LDO21CTRL = 0x4d,
95
96 MAX8997_REG_MBCCTRL1 = 0x50,
97 MAX8997_REG_MBCCTRL2 = 0x51,
98 MAX8997_REG_MBCCTRL3 = 0x52,
99 MAX8997_REG_MBCCTRL4 = 0x53,
100 MAX8997_REG_MBCCTRL5 = 0x54,
101 MAX8997_REG_MBCCTRL6 = 0x55,
102 MAX8997_REG_OTPCGHCVS = 0x56,
103
104 MAX8997_REG_SAFEOUTCTRL = 0x5a,
105
106 MAX8997_REG_LBCNFG1 = 0x5e,
107 MAX8997_REG_LBCNFG2 = 0x5f,
108 MAX8997_REG_BBCCTRL = 0x60,
109
110 MAX8997_REG_FLASH1_CUR = 0x63,
111 MAX8997_REG_FLASH2_CUR = 0x64,
112 MAX8997_REG_MOVIE_CUR = 0x65,
113 MAX8997_REG_GSMB_CUR = 0x66,
114 MAX8997_REG_BOOST_CNTL = 0x67,
115 MAX8997_REG_LEN_CNTL = 0x68,
116 MAX8997_REG_FLASH_CNTL = 0x69,
117 MAX8997_REG_WDT_CNTL = 0x6a,
118 MAX8997_REG_MAXFLASH1 = 0x6b,
119 MAX8997_REG_MAXFLASH2 = 0x6c,
120 MAX8997_REG_FLASHSTATUS = 0x6d,
121 MAX8997_REG_FLASHSTATUSMASK = 0x6e,
122
123 MAX8997_REG_GPIOCNTL1 = 0x70,
124 MAX8997_REG_GPIOCNTL2 = 0x71,
125 MAX8997_REG_GPIOCNTL3 = 0x72,
126 MAX8997_REG_GPIOCNTL4 = 0x73,
127 MAX8997_REG_GPIOCNTL5 = 0x74,
128 MAX8997_REG_GPIOCNTL6 = 0x75,
129 MAX8997_REG_GPIOCNTL7 = 0x76,
130 MAX8997_REG_GPIOCNTL8 = 0x77,
131 MAX8997_REG_GPIOCNTL9 = 0x78,
132 MAX8997_REG_GPIOCNTL10 = 0x79,
133 MAX8997_REG_GPIOCNTL11 = 0x7a,
134 MAX8997_REG_GPIOCNTL12 = 0x7b,
135
136 MAX8997_REG_LDO1CONFIG = 0x80,
137 MAX8997_REG_LDO2CONFIG = 0x81,
138 MAX8997_REG_LDO3CONFIG = 0x82,
139 MAX8997_REG_LDO4CONFIG = 0x83,
140 MAX8997_REG_LDO5CONFIG = 0x84,
141 MAX8997_REG_LDO6CONFIG = 0x85,
142 MAX8997_REG_LDO7CONFIG = 0x86,
143 MAX8997_REG_LDO8CONFIG = 0x87,
144 MAX8997_REG_LDO9CONFIG = 0x88,
145 MAX8997_REG_LDO10CONFIG = 0x89,
146 MAX8997_REG_LDO11CONFIG = 0x8a,
147 MAX8997_REG_LDO12CONFIG = 0x8b,
148 MAX8997_REG_LDO13CONFIG = 0x8c,
149 MAX8997_REG_LDO14CONFIG = 0x8d,
150 MAX8997_REG_LDO15CONFIG = 0x8e,
151 MAX8997_REG_LDO16CONFIG = 0x8f,
152 MAX8997_REG_LDO17CONFIG = 0x90,
153 MAX8997_REG_LDO18CONFIG = 0x91,
154 MAX8997_REG_LDO21CONFIG = 0x92,
155
156 MAX8997_REG_DVSOKTIMER1 = 0x97,
157 MAX8997_REG_DVSOKTIMER2 = 0x98,
158 MAX8997_REG_DVSOKTIMER4 = 0x99,
159 MAX8997_REG_DVSOKTIMER5 = 0x9a,
160
161 MAX8997_REG_PMIC_END = 0x9b,
162 };
163
164 enum max8997_muic_reg {
165 MAX8997_MUIC_REG_ID = 0x0,
166 MAX8997_MUIC_REG_INT1 = 0x1,
167 MAX8997_MUIC_REG_INT2 = 0x2,
168 MAX8997_MUIC_REG_INT3 = 0x3,
169 MAX8997_MUIC_REG_STATUS1 = 0x4,
170 MAX8997_MUIC_REG_STATUS2 = 0x5,
171 MAX8997_MUIC_REG_STATUS3 = 0x6,
172 MAX8997_MUIC_REG_INTMASK1 = 0x7,
173 MAX8997_MUIC_REG_INTMASK2 = 0x8,
174 MAX8997_MUIC_REG_INTMASK3 = 0x9,
175 MAX8997_MUIC_REG_CDETCTRL = 0xa,
176
177 MAX8997_MUIC_REG_CONTROL1 = 0xc,
178 MAX8997_MUIC_REG_CONTROL2 = 0xd,
179 MAX8997_MUIC_REG_CONTROL3 = 0xe,
180
181 MAX8997_MUIC_REG_END = 0xf,
182 };
183
184
185 #define STATUS1_ADC_SHIFT 0
186 #define STATUS1_ADCLOW_SHIFT 5
187 #define STATUS1_ADCERR_SHIFT 6
188 #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
189 #define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
190 #define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
191
192
193 #define STATUS2_CHGTYP_SHIFT 0
194 #define STATUS2_CHGDETRUN_SHIFT 3
195 #define STATUS2_DCDTMR_SHIFT 4
196 #define STATUS2_DBCHG_SHIFT 5
197 #define STATUS2_VBVOLT_SHIFT 6
198 #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
199 #define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
200 #define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
201 #define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
202 #define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
203
204
205 #define STATUS3_OVP_SHIFT 2
206 #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
207
208
209 #define COMN1SW_SHIFT 0
210 #define COMP2SW_SHIFT 3
211 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
212 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
213 #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
214
215 #define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
216 | (1 << COMN1SW_SHIFT))
217 #define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
218 | (2 << COMN1SW_SHIFT))
219 #define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
220 | (3 << COMN1SW_SHIFT))
221 #define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
222 | (0 << COMN1SW_SHIFT))
223
224 #define CONTROL2_LOWPWR_SHIFT (0)
225 #define CONTROL2_ADCEN_SHIFT (1)
226 #define CONTROL2_CPEN_SHIFT (2)
227 #define CONTROL2_SFOUTASRT_SHIFT (3)
228 #define CONTROL2_SFOUTORD_SHIFT (4)
229 #define CONTROL2_ACCDET_SHIFT (5)
230 #define CONTROL2_USBCPINT_SHIFT (6)
231 #define CONTROL2_RCPS_SHIFT (7)
232 #define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
233 #define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
234 #define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
235 #define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
236 #define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
237 #define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
238 #define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
239 #define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
240
241 #define CONTROL3_JIGSET_SHIFT (0)
242 #define CONTROL3_BTLDSET_SHIFT (2)
243 #define CONTROL3_ADCDBSET_SHIFT (4)
244 #define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
245 #define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
246 #define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
247
248 enum max8997_haptic_reg {
249 MAX8997_HAPTIC_REG_GENERAL = 0x00,
250 MAX8997_HAPTIC_REG_CONF1 = 0x01,
251 MAX8997_HAPTIC_REG_CONF2 = 0x02,
252 MAX8997_HAPTIC_REG_DRVCONF = 0x03,
253 MAX8997_HAPTIC_REG_CYCLECONF1 = 0x04,
254 MAX8997_HAPTIC_REG_CYCLECONF2 = 0x05,
255 MAX8997_HAPTIC_REG_SIGCONF1 = 0x06,
256 MAX8997_HAPTIC_REG_SIGCONF2 = 0x07,
257 MAX8997_HAPTIC_REG_SIGCONF3 = 0x08,
258 MAX8997_HAPTIC_REG_SIGCONF4 = 0x09,
259 MAX8997_HAPTIC_REG_SIGDC1 = 0x0a,
260 MAX8997_HAPTIC_REG_SIGDC2 = 0x0b,
261 MAX8997_HAPTIC_REG_SIGPWMDC1 = 0x0c,
262 MAX8997_HAPTIC_REG_SIGPWMDC2 = 0x0d,
263 MAX8997_HAPTIC_REG_SIGPWMDC3 = 0x0e,
264 MAX8997_HAPTIC_REG_SIGPWMDC4 = 0x0f,
265 MAX8997_HAPTIC_REG_MTR_REV = 0x10,
266
267 MAX8997_HAPTIC_REG_END = 0x11,
268 };
269
270
271 enum max8997_rtc_reg {
272 MAX8997_RTC_CTRLMASK = 0x02,
273 MAX8997_RTC_CTRL = 0x03,
274 MAX8997_RTC_UPDATE1 = 0x04,
275 MAX8997_RTC_UPDATE2 = 0x05,
276 MAX8997_RTC_WTSR_SMPL = 0x06,
277
278 MAX8997_RTC_SEC = 0x10,
279 MAX8997_RTC_MIN = 0x11,
280 MAX8997_RTC_HOUR = 0x12,
281 MAX8997_RTC_DAY_OF_WEEK = 0x13,
282 MAX8997_RTC_MONTH = 0x14,
283 MAX8997_RTC_YEAR = 0x15,
284 MAX8997_RTC_DAY_OF_MONTH = 0x16,
285 MAX8997_RTC_ALARM1_SEC = 0x17,
286 MAX8997_RTC_ALARM1_MIN = 0x18,
287 MAX8997_RTC_ALARM1_HOUR = 0x19,
288 MAX8997_RTC_ALARM1_DAY_OF_WEEK = 0x1a,
289 MAX8997_RTC_ALARM1_MONTH = 0x1b,
290 MAX8997_RTC_ALARM1_YEAR = 0x1c,
291 MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
292 MAX8997_RTC_ALARM2_SEC = 0x1e,
293 MAX8997_RTC_ALARM2_MIN = 0x1f,
294 MAX8997_RTC_ALARM2_HOUR = 0x20,
295 MAX8997_RTC_ALARM2_DAY_OF_WEEK = 0x21,
296 MAX8997_RTC_ALARM2_MONTH = 0x22,
297 MAX8997_RTC_ALARM2_YEAR = 0x23,
298 MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24,
299 };
300
301 enum max8997_irq_source {
302 PMIC_INT1 = 0,
303 PMIC_INT2,
304 PMIC_INT3,
305 PMIC_INT4,
306
307 FUEL_GAUGE,
308
309 MUIC_INT1,
310 MUIC_INT2,
311 MUIC_INT3,
312
313 GPIO_LOW,
314 GPIO_HI,
315
316 FLASH_STATUS,
317
318 MAX8997_IRQ_GROUP_NR,
319 };
320
321 enum max8997_irq {
322 MAX8997_PMICIRQ_PWRONR,
323 MAX8997_PMICIRQ_PWRONF,
324 MAX8997_PMICIRQ_PWRON1SEC,
325 MAX8997_PMICIRQ_JIGONR,
326 MAX8997_PMICIRQ_JIGONF,
327 MAX8997_PMICIRQ_LOWBAT2,
328 MAX8997_PMICIRQ_LOWBAT1,
329
330 MAX8997_PMICIRQ_JIGR,
331 MAX8997_PMICIRQ_JIGF,
332 MAX8997_PMICIRQ_MR,
333 MAX8997_PMICIRQ_DVS1OK,
334 MAX8997_PMICIRQ_DVS2OK,
335 MAX8997_PMICIRQ_DVS3OK,
336 MAX8997_PMICIRQ_DVS4OK,
337
338 MAX8997_PMICIRQ_CHGINS,
339 MAX8997_PMICIRQ_CHGRM,
340 MAX8997_PMICIRQ_DCINOVP,
341 MAX8997_PMICIRQ_TOPOFFR,
342 MAX8997_PMICIRQ_CHGRSTF,
343 MAX8997_PMICIRQ_MBCHGTMEXPD,
344
345 MAX8997_PMICIRQ_RTC60S,
346 MAX8997_PMICIRQ_RTCA1,
347 MAX8997_PMICIRQ_RTCA2,
348 MAX8997_PMICIRQ_SMPL_INT,
349 MAX8997_PMICIRQ_RTC1S,
350 MAX8997_PMICIRQ_WTSR,
351
352 MAX8997_MUICIRQ_ADCError,
353 MAX8997_MUICIRQ_ADCLow,
354 MAX8997_MUICIRQ_ADC,
355
356 MAX8997_MUICIRQ_VBVolt,
357 MAX8997_MUICIRQ_DBChg,
358 MAX8997_MUICIRQ_DCDTmr,
359 MAX8997_MUICIRQ_ChgDetRun,
360 MAX8997_MUICIRQ_ChgTyp,
361
362 MAX8997_MUICIRQ_OVP,
363
364 MAX8997_IRQ_NR,
365 };
366
367 #define MAX8997_NUM_GPIO 12
368 struct max8997_dev {
369 struct device *dev;
370 struct max8997_platform_data *pdata;
371 struct i2c_client *i2c;
372 struct i2c_client *rtc;
373 struct i2c_client *haptic;
374 struct i2c_client *muic;
375 struct mutex iolock;
376
377 unsigned long type;
378 struct platform_device *battery;
379
380 int irq;
381 int ono;
382 struct irq_domain *irq_domain;
383 struct mutex irqlock;
384 int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
385 int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
386
387
388 u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
389 MAX8997_HAPTIC_REG_END];
390
391 bool gpio_status[MAX8997_NUM_GPIO];
392 };
393
394 enum max8997_types {
395 TYPE_MAX8997,
396 TYPE_MAX8966,
397 };
398
399 extern int max8997_irq_init(struct max8997_dev *max8997);
400 extern void max8997_irq_exit(struct max8997_dev *max8997);
401 extern int max8997_irq_resume(struct max8997_dev *max8997);
402
403 extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
404 extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
405 u8 *buf);
406 extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
407 extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
408 u8 *buf);
409 extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
410
411 #define MAX8997_GPIO_INT_BOTH (0x3 << 4)
412 #define MAX8997_GPIO_INT_RISE (0x2 << 4)
413 #define MAX8997_GPIO_INT_FALL (0x1 << 4)
414
415 #define MAX8997_GPIO_INT_MASK (0x3 << 4)
416 #define MAX8997_GPIO_DATA_MASK (0x1 << 2)
417 #endif