root/include/linux/mfd/rohm-bd70528.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. bd70528_wdt_set
  2. bd70528_wdt_lock
  3. bd70528_wdt_unlock
   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Copyright (C) 2018 ROHM Semiconductors */
   3 
   4 #ifndef __LINUX_MFD_BD70528_H__
   5 #define __LINUX_MFD_BD70528_H__
   6 
   7 #include <linux/bits.h>
   8 #include <linux/device.h>
   9 #include <linux/mfd/rohm-generic.h>
  10 #include <linux/regmap.h>
  11 
  12 enum {
  13         BD70528_BUCK1,
  14         BD70528_BUCK2,
  15         BD70528_BUCK3,
  16         BD70528_LDO1,
  17         BD70528_LDO2,
  18         BD70528_LDO3,
  19         BD70528_LED1,
  20         BD70528_LED2,
  21 };
  22 
  23 struct bd70528_data {
  24         struct rohm_regmap_dev chip;
  25         struct mutex rtc_timer_lock;
  26 };
  27 
  28 #define BD70528_BUCK_VOLTS 17
  29 #define BD70528_BUCK_VOLTS 17
  30 #define BD70528_BUCK_VOLTS 17
  31 #define BD70528_LDO_VOLTS 0x20
  32 
  33 #define BD70528_REG_BUCK1_EN    0x0F
  34 #define BD70528_REG_BUCK1_VOLT  0x15
  35 #define BD70528_REG_BUCK2_EN    0x10
  36 #define BD70528_REG_BUCK2_VOLT  0x16
  37 #define BD70528_REG_BUCK3_EN    0x11
  38 #define BD70528_REG_BUCK3_VOLT  0x17
  39 #define BD70528_REG_LDO1_EN     0x1b
  40 #define BD70528_REG_LDO1_VOLT   0x1e
  41 #define BD70528_REG_LDO2_EN     0x1c
  42 #define BD70528_REG_LDO2_VOLT   0x1f
  43 #define BD70528_REG_LDO3_EN     0x1d
  44 #define BD70528_REG_LDO3_VOLT   0x20
  45 #define BD70528_REG_LED_CTRL    0x2b
  46 #define BD70528_REG_LED_VOLT    0x29
  47 #define BD70528_REG_LED_EN      0x2a
  48 
  49 /* main irq registers */
  50 #define BD70528_REG_INT_MAIN    0x7E
  51 #define BD70528_REG_INT_MAIN_MASK 0x74
  52 
  53 /* 'sub irq' registers */
  54 #define BD70528_REG_INT_SHDN    0x7F
  55 #define BD70528_REG_INT_PWR_FLT 0x80
  56 #define BD70528_REG_INT_VR_FLT  0x81
  57 #define BD70528_REG_INT_MISC    0x82
  58 #define BD70528_REG_INT_BAT1    0x83
  59 #define BD70528_REG_INT_BAT2    0x84
  60 #define BD70528_REG_INT_RTC     0x85
  61 #define BD70528_REG_INT_GPIO    0x86
  62 #define BD70528_REG_INT_OP_FAIL 0x87
  63 
  64 #define BD70528_REG_INT_SHDN_MASK       0x75
  65 #define BD70528_REG_INT_PWR_FLT_MASK    0x76
  66 #define BD70528_REG_INT_VR_FLT_MASK     0x77
  67 #define BD70528_REG_INT_MISC_MASK       0x78
  68 #define BD70528_REG_INT_BAT1_MASK       0x79
  69 #define BD70528_REG_INT_BAT2_MASK       0x7a
  70 #define BD70528_REG_INT_RTC_MASK        0x7b
  71 #define BD70528_REG_INT_GPIO_MASK       0x7c
  72 #define BD70528_REG_INT_OP_FAIL_MASK    0x7d
  73 
  74 /* Reset related 'magic' registers */
  75 #define BD70528_REG_SHIPMODE    0x03
  76 #define BD70528_REG_HWRESET     0x04
  77 #define BD70528_REG_WARMRESET   0x05
  78 #define BD70528_REG_STANDBY     0x06
  79 
  80 /* GPIO registers */
  81 #define BD70528_REG_GPIO_STATE  0x8F
  82 
  83 #define BD70528_REG_GPIO1_IN    0x4d
  84 #define BD70528_REG_GPIO2_IN    0x4f
  85 #define BD70528_REG_GPIO3_IN    0x51
  86 #define BD70528_REG_GPIO4_IN    0x53
  87 #define BD70528_REG_GPIO1_OUT   0x4e
  88 #define BD70528_REG_GPIO2_OUT   0x50
  89 #define BD70528_REG_GPIO3_OUT   0x52
  90 #define BD70528_REG_GPIO4_OUT   0x54
  91 
  92 /* clk control */
  93 
  94 #define BD70528_REG_CLK_OUT     0x2c
  95 
  96 /* RTC */
  97 
  98 #define BD70528_REG_RTC_COUNT_H         0x2d
  99 #define BD70528_REG_RTC_COUNT_L         0x2e
 100 #define BD70528_REG_RTC_SEC             0x2f
 101 #define BD70528_REG_RTC_MINUTE          0x30
 102 #define BD70528_REG_RTC_HOUR            0x31
 103 #define BD70528_REG_RTC_WEEK            0x32
 104 #define BD70528_REG_RTC_DAY             0x33
 105 #define BD70528_REG_RTC_MONTH           0x34
 106 #define BD70528_REG_RTC_YEAR            0x35
 107 
 108 #define BD70528_REG_RTC_ALM_SEC         0x36
 109 #define BD70528_REG_RTC_ALM_START       BD70528_REG_RTC_ALM_SEC
 110 #define BD70528_REG_RTC_ALM_MINUTE      0x37
 111 #define BD70528_REG_RTC_ALM_HOUR        0x38
 112 #define BD70528_REG_RTC_ALM_WEEK        0x39
 113 #define BD70528_REG_RTC_ALM_DAY         0x3a
 114 #define BD70528_REG_RTC_ALM_MONTH       0x3b
 115 #define BD70528_REG_RTC_ALM_YEAR        0x3c
 116 #define BD70528_REG_RTC_ALM_MASK        0x3d
 117 #define BD70528_REG_RTC_ALM_REPEAT      0x3e
 118 #define BD70528_REG_RTC_START           BD70528_REG_RTC_SEC
 119 
 120 #define BD70528_REG_RTC_WAKE_SEC        0x43
 121 #define BD70528_REG_RTC_WAKE_START      BD70528_REG_RTC_WAKE_SEC
 122 #define BD70528_REG_RTC_WAKE_MIN        0x44
 123 #define BD70528_REG_RTC_WAKE_HOUR       0x45
 124 #define BD70528_REG_RTC_WAKE_CTRL       0x46
 125 
 126 #define BD70528_REG_ELAPSED_TIMER_EN    0x42
 127 #define BD70528_REG_WAKE_EN             0x46
 128 
 129 /* WDT registers */
 130 #define BD70528_REG_WDT_CTRL            0x4A
 131 #define BD70528_REG_WDT_HOUR            0x49
 132 #define BD70528_REG_WDT_MINUTE          0x48
 133 #define BD70528_REG_WDT_SEC             0x47
 134 
 135 /* Charger / Battery */
 136 #define BD70528_REG_CHG_CURR_STAT       0x59
 137 #define BD70528_REG_CHG_BAT_STAT        0x57
 138 #define BD70528_REG_CHG_BAT_TEMP        0x58
 139 #define BD70528_REG_CHG_IN_STAT         0x56
 140 #define BD70528_REG_CHG_DCIN_ILIM       0x5d
 141 #define BD70528_REG_CHG_CHG_CURR_WARM   0x61
 142 #define BD70528_REG_CHG_CHG_CURR_COLD   0x62
 143 
 144 /* Masks for main IRQ register bits */
 145 enum {
 146         BD70528_INT_SHDN,
 147 #define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
 148         BD70528_INT_PWR_FLT,
 149 #define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
 150         BD70528_INT_VR_FLT,
 151 #define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
 152         BD70528_INT_MISC,
 153 #define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
 154         BD70528_INT_BAT1,
 155 #define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
 156         BD70528_INT_RTC,
 157 #define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
 158         BD70528_INT_GPIO,
 159 #define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
 160         BD70528_INT_OP_FAIL,
 161 #define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
 162 };
 163 
 164 /* IRQs */
 165 enum {
 166         /* Shutdown register IRQs */
 167         BD70528_INT_LONGPUSH,
 168         BD70528_INT_WDT,
 169         BD70528_INT_HWRESET,
 170         BD70528_INT_RSTB_FAULT,
 171         BD70528_INT_VBAT_UVLO,
 172         BD70528_INT_TSD,
 173         BD70528_INT_RSTIN,
 174         /* Power failure register IRQs */
 175         BD70528_INT_BUCK1_FAULT,
 176         BD70528_INT_BUCK2_FAULT,
 177         BD70528_INT_BUCK3_FAULT,
 178         BD70528_INT_LDO1_FAULT,
 179         BD70528_INT_LDO2_FAULT,
 180         BD70528_INT_LDO3_FAULT,
 181         BD70528_INT_LED1_FAULT,
 182         BD70528_INT_LED2_FAULT,
 183         /* VR FAULT register IRQs */
 184         BD70528_INT_BUCK1_OCP,
 185         BD70528_INT_BUCK2_OCP,
 186         BD70528_INT_BUCK3_OCP,
 187         BD70528_INT_LED1_OCP,
 188         BD70528_INT_LED2_OCP,
 189         BD70528_INT_BUCK1_FULLON,
 190         BD70528_INT_BUCK2_FULLON,
 191         /* PMU register interrupts */
 192         BD70528_INT_SHORTPUSH,
 193         BD70528_INT_AUTO_WAKEUP,
 194         BD70528_INT_STATE_CHANGE,
 195         /* Charger 1 register IRQs */
 196         BD70528_INT_BAT_OV_RES,
 197         BD70528_INT_BAT_OV_DET,
 198         BD70528_INT_DBAT_DET,
 199         BD70528_INT_BATTSD_COLD_RES,
 200         BD70528_INT_BATTSD_COLD_DET,
 201         BD70528_INT_BATTSD_HOT_RES,
 202         BD70528_INT_BATTSD_HOT_DET,
 203         BD70528_INT_CHG_TSD,
 204         /* Charger 2 register IRQs */
 205         BD70528_INT_BAT_RMV,
 206         BD70528_INT_BAT_DET,
 207         BD70528_INT_DCIN2_OV_RES,
 208         BD70528_INT_DCIN2_OV_DET,
 209         BD70528_INT_DCIN2_RMV,
 210         BD70528_INT_DCIN2_DET,
 211         BD70528_INT_DCIN1_RMV,
 212         BD70528_INT_DCIN1_DET,
 213         /* RTC register IRQs */
 214         BD70528_INT_RTC_ALARM,
 215         BD70528_INT_ELPS_TIM,
 216         /* GPIO register IRQs */
 217         BD70528_INT_GPIO0,
 218         BD70528_INT_GPIO1,
 219         BD70528_INT_GPIO2,
 220         BD70528_INT_GPIO3,
 221         /* Invalid operation register IRQs */
 222         BD70528_INT_BUCK1_DVS_OPFAIL,
 223         BD70528_INT_BUCK2_DVS_OPFAIL,
 224         BD70528_INT_BUCK3_DVS_OPFAIL,
 225         BD70528_INT_LED1_VOLT_OPFAIL,
 226         BD70528_INT_LED2_VOLT_OPFAIL,
 227 };
 228 
 229 /* Masks */
 230 #define BD70528_INT_LONGPUSH_MASK 0x1
 231 #define BD70528_INT_WDT_MASK 0x2
 232 #define BD70528_INT_HWRESET_MASK 0x4
 233 #define BD70528_INT_RSTB_FAULT_MASK 0x8
 234 #define BD70528_INT_VBAT_UVLO_MASK 0x10
 235 #define BD70528_INT_TSD_MASK 0x20
 236 #define BD70528_INT_RSTIN_MASK 0x40
 237 
 238 #define BD70528_INT_BUCK1_FAULT_MASK 0x1
 239 #define BD70528_INT_BUCK2_FAULT_MASK 0x2
 240 #define BD70528_INT_BUCK3_FAULT_MASK 0x4
 241 #define BD70528_INT_LDO1_FAULT_MASK 0x8
 242 #define BD70528_INT_LDO2_FAULT_MASK 0x10
 243 #define BD70528_INT_LDO3_FAULT_MASK 0x20
 244 #define BD70528_INT_LED1_FAULT_MASK 0x40
 245 #define BD70528_INT_LED2_FAULT_MASK 0x80
 246 
 247 #define BD70528_INT_BUCK1_OCP_MASK 0x1
 248 #define BD70528_INT_BUCK2_OCP_MASK 0x2
 249 #define BD70528_INT_BUCK3_OCP_MASK 0x4
 250 #define BD70528_INT_LED1_OCP_MASK 0x8
 251 #define BD70528_INT_LED2_OCP_MASK 0x10
 252 #define BD70528_INT_BUCK1_FULLON_MASK 0x20
 253 #define BD70528_INT_BUCK2_FULLON_MASK 0x40
 254 
 255 #define BD70528_INT_SHORTPUSH_MASK 0x1
 256 #define BD70528_INT_AUTO_WAKEUP_MASK 0x2
 257 #define BD70528_INT_STATE_CHANGE_MASK 0x10
 258 
 259 #define BD70528_INT_BAT_OV_RES_MASK 0x1
 260 #define BD70528_INT_BAT_OV_DET_MASK 0x2
 261 #define BD70528_INT_DBAT_DET_MASK 0x4
 262 #define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
 263 #define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
 264 #define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
 265 #define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
 266 #define BD70528_INT_CHG_TSD_MASK 0x80
 267 
 268 #define BD70528_INT_BAT_RMV_MASK 0x1
 269 #define BD70528_INT_BAT_DET_MASK 0x2
 270 #define BD70528_INT_DCIN2_OV_RES_MASK 0x4
 271 #define BD70528_INT_DCIN2_OV_DET_MASK 0x8
 272 #define BD70528_INT_DCIN2_RMV_MASK 0x10
 273 #define BD70528_INT_DCIN2_DET_MASK 0x20
 274 #define BD70528_INT_DCIN1_RMV_MASK 0x40
 275 #define BD70528_INT_DCIN1_DET_MASK 0x80
 276 
 277 #define BD70528_INT_RTC_ALARM_MASK 0x1
 278 #define BD70528_INT_ELPS_TIM_MASK 0x2
 279 
 280 #define BD70528_INT_GPIO0_MASK 0x1
 281 #define BD70528_INT_GPIO1_MASK 0x2
 282 #define BD70528_INT_GPIO2_MASK 0x4
 283 #define BD70528_INT_GPIO3_MASK 0x8
 284 
 285 #define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
 286 #define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
 287 #define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
 288 #define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
 289 #define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
 290 
 291 #define BD70528_DEBOUNCE_MASK 0x3
 292 
 293 #define BD70528_DEBOUNCE_DISABLE 0
 294 #define BD70528_DEBOUNCE_15MS 1
 295 #define BD70528_DEBOUNCE_30MS 2
 296 #define BD70528_DEBOUNCE_50MS 3
 297 
 298 #define BD70528_GPIO_DRIVE_MASK 0x2
 299 #define BD70528_GPIO_PUSH_PULL 0x0
 300 #define BD70528_GPIO_OPEN_DRAIN 0x2
 301 
 302 #define BD70528_GPIO_OUT_EN_MASK 0x80
 303 #define BD70528_GPIO_OUT_ENABLE 0x80
 304 #define BD70528_GPIO_OUT_DISABLE 0x0
 305 
 306 #define BD70528_GPIO_OUT_HI 0x1
 307 #define BD70528_GPIO_OUT_LO 0x0
 308 #define BD70528_GPIO_OUT_MASK 0x1
 309 
 310 #define BD70528_GPIO_IN_STATE_BASE 1
 311 
 312 #define BD70528_CLK_OUT_EN_MASK 0x1
 313 
 314 /* RTC masks to mask out reserved bits */
 315 
 316 #define BD70528_MASK_RTC_SEC            0x7f
 317 #define BD70528_MASK_RTC_MINUTE         0x7f
 318 #define BD70528_MASK_RTC_HOUR_24H       0x80
 319 #define BD70528_MASK_RTC_HOUR_PM        0x20
 320 #define BD70528_MASK_RTC_HOUR           0x3f
 321 #define BD70528_MASK_RTC_DAY            0x3f
 322 #define BD70528_MASK_RTC_WEEK           0x07
 323 #define BD70528_MASK_RTC_MONTH          0x1f
 324 #define BD70528_MASK_RTC_YEAR           0xff
 325 #define BD70528_MASK_RTC_COUNT_L        0x7f
 326 
 327 #define BD70528_MASK_ELAPSED_TIMER_EN   0x1
 328 /* Mask second, min and hour fields
 329  * HW would support ALM irq for over 24h
 330  * (by setting day, month and year too)
 331  * but as we wish to keep this same as for
 332  * wake-up we limit ALM to 24H and only
 333  * unmask sec, min and hour
 334  */
 335 #define BD70528_MASK_ALM_EN             0x7
 336 #define BD70528_MASK_WAKE_EN            0x1
 337 
 338 /* WDT masks */
 339 #define BD70528_MASK_WDT_EN             0x1
 340 #define BD70528_MASK_WDT_HOUR           0x1
 341 #define BD70528_MASK_WDT_MINUTE         0x7f
 342 #define BD70528_MASK_WDT_SEC            0x7f
 343 
 344 #define BD70528_WDT_STATE_BIT           0x1
 345 #define BD70528_ELAPSED_STATE_BIT       0x2
 346 #define BD70528_WAKE_STATE_BIT          0x4
 347 
 348 /* Charger masks */
 349 #define BD70528_MASK_CHG_STAT           0x7f
 350 #define BD70528_MASK_CHG_BAT_TIMER      0x20
 351 #define BD70528_MASK_CHG_BAT_OVERVOLT   0x10
 352 #define BD70528_MASK_CHG_BAT_DETECT     0x1
 353 #define BD70528_MASK_CHG_DCIN1_UVLO     0x1
 354 #define BD70528_MASK_CHG_DCIN_ILIM      0x3f
 355 #define BD70528_MASK_CHG_CHG_CURR       0x1f
 356 #define BD70528_MASK_CHG_TRICKLE_CURR   0x10
 357 
 358 /*
 359  * Note, external battery register is the lonely rider at
 360  * address 0xc5. See how to stuff that in the regmap
 361  */
 362 #define BD70528_MAX_REGISTER 0x94
 363 
 364 /* Buck control masks */
 365 #define BD70528_MASK_RUN_EN     0x4
 366 #define BD70528_MASK_STBY_EN    0x2
 367 #define BD70528_MASK_IDLE_EN    0x1
 368 #define BD70528_MASK_LED1_EN    0x1
 369 #define BD70528_MASK_LED2_EN    0x10
 370 
 371 #define BD70528_MASK_BUCK_VOLT  0xf
 372 #define BD70528_MASK_LDO_VOLT   0x1f
 373 #define BD70528_MASK_LED1_VOLT  0x1
 374 #define BD70528_MASK_LED2_VOLT  0x10
 375 
 376 /* Misc irq masks */
 377 #define BD70528_INT_MASK_SHORT_PUSH     1
 378 #define BD70528_INT_MASK_AUTO_WAKE      2
 379 #define BD70528_INT_MASK_POWER_STATE    4
 380 
 381 #define BD70528_MASK_BUCK_RAMP 0x10
 382 #define BD70528_SIFT_BUCK_RAMP 4
 383 
 384 #if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
 385 
 386 int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
 387 void bd70528_wdt_lock(struct rohm_regmap_dev *data);
 388 void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
 389 
 390 #else /* CONFIG_BD70528_WATCHDOG */
 391 
 392 static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
 393                                   int *old_state)
 394 {
 395         return 0;
 396 }
 397 
 398 static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
 399 {
 400 }
 401 
 402 static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
 403 {
 404 }
 405 
 406 #endif /* CONFIG_BD70528_WATCHDOG */
 407 
 408 #endif /* __LINUX_MFD_BD70528_H__ */
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