root/include/linux/mfd/asic3.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * include/linux/mfd/asic3.h
   4  *
   5  * Compaq ASIC3 headers.
   6  *
   7  * Copyright 2001 Compaq Computer Corporation.
   8  * Copyright 2007-2008 OpenedHand Ltd.
   9  */
  10 
  11 #ifndef __ASIC3_H__
  12 #define __ASIC3_H__
  13 
  14 #include <linux/types.h>
  15 
  16 struct led_classdev;
  17 struct asic3_led {
  18         const char      *name;
  19         const char      *default_trigger;
  20         struct led_classdev *cdev;
  21 };
  22 
  23 struct asic3_platform_data {
  24         u16 *gpio_config;
  25         unsigned int gpio_config_num;
  26 
  27         unsigned int irq_base;
  28 
  29         unsigned int gpio_base;
  30 
  31         unsigned int clock_rate;
  32 
  33         struct asic3_led *leds;
  34 };
  35 
  36 #define ASIC3_NUM_GPIO_BANKS    4
  37 #define ASIC3_GPIOS_PER_BANK    16
  38 #define ASIC3_NUM_GPIOS         64
  39 #define ASIC3_NR_IRQS           ASIC3_NUM_GPIOS + 6
  40 
  41 #define ASIC3_IRQ_LED0          64
  42 #define ASIC3_IRQ_LED1          65
  43 #define ASIC3_IRQ_LED2          66
  44 #define ASIC3_IRQ_SPI           67
  45 #define ASIC3_IRQ_SMBUS         68
  46 #define ASIC3_IRQ_OWM           69
  47 
  48 #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
  49 
  50 #define ASIC3_GPIO_BANK_A       0
  51 #define ASIC3_GPIO_BANK_B       1
  52 #define ASIC3_GPIO_BANK_C       2
  53 #define ASIC3_GPIO_BANK_D       3
  54 
  55 #define ASIC3_GPIO(bank, gpio) \
  56         ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
  57 #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
  58 /* All offsets below are specified with this address bus shift */
  59 #define ASIC3_DEFAULT_ADDR_SHIFT 2
  60 
  61 #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
  62 #define ASIC3_GPIO_OFFSET(base, reg) \
  63         (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
  64 
  65 #define ASIC3_GPIO_A_BASE      0x0000
  66 #define ASIC3_GPIO_B_BASE      0x0100
  67 #define ASIC3_GPIO_C_BASE      0x0200
  68 #define ASIC3_GPIO_D_BASE      0x0300
  69 
  70 #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
  71 #define ASIC3_GPIO_TO_BIT(gpio)  ((gpio) - \
  72                                   (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
  73 #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
  74 #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
  75 #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
  76 
  77 #define ASIC3_GPIO_MASK          0x00    /* R/W 0:don't mask */
  78 #define ASIC3_GPIO_DIRECTION     0x04    /* R/W 0:input */
  79 #define ASIC3_GPIO_OUT           0x08    /* R/W 0:output low */
  80 #define ASIC3_GPIO_TRIGGER_TYPE  0x0c    /* R/W 0:level */
  81 #define ASIC3_GPIO_EDGE_TRIGGER  0x10    /* R/W 0:falling */
  82 #define ASIC3_GPIO_LEVEL_TRIGGER 0x14    /* R/W 0:low level detect */
  83 #define ASIC3_GPIO_SLEEP_MASK    0x18    /* R/W 0:don't mask in sleep mode */
  84 #define ASIC3_GPIO_SLEEP_OUT     0x1c    /* R/W level 0:low in sleep mode */
  85 #define ASIC3_GPIO_BAT_FAULT_OUT 0x20    /* R/W level 0:low in batt_fault */
  86 #define ASIC3_GPIO_INT_STATUS    0x24    /* R/W 0:none, 1:detect */
  87 #define ASIC3_GPIO_ALT_FUNCTION  0x28    /* R/W 1:LED register control */
  88 #define ASIC3_GPIO_SLEEP_CONF    0x2c    /*
  89                                           * R/W bit 1: autosleep
  90                                           * 0: disable gposlpout in normal mode,
  91                                           * enable gposlpout in sleep mode.
  92                                           */
  93 #define ASIC3_GPIO_STATUS        0x30    /* R   Pin status */
  94 
  95 /*
  96  * ASIC3 GPIO config
  97  *
  98  * Bits 0..6   gpio number
  99  * Bits 7..13  Alternate function
 100  * Bit  14     Direction
 101  * Bit  15     Initial value
 102  *
 103  */
 104 #define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
 105 #define ASIC3_CONFIG_GPIO_ALT(config)  (((config) & (0x7f << 7)) >> 7)
 106 #define ASIC3_CONFIG_GPIO_DIR(config)  ((config & (1 << 14)) >> 14)
 107 #define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
 108 #define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
 109         | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
 110         | (((init) & 0x1) << 15))
 111 #define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
 112         ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
 113 #define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
 114         ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
 115 
 116 /*
 117  * Alternate functions
 118  */
 119 #define ASIC3_GPIOA11_PWM0              ASIC3_CONFIG_GPIO(11, 1, 1, 0)
 120 #define ASIC3_GPIOA12_PWM1              ASIC3_CONFIG_GPIO(12, 1, 1, 0)
 121 #define ASIC3_GPIOA15_CONTROL_CX        ASIC3_CONFIG_GPIO(15, 1, 1, 0)
 122 #define ASIC3_GPIOC0_LED0               ASIC3_CONFIG_GPIO(32, 1, 0, 0)
 123 #define ASIC3_GPIOC1_LED1               ASIC3_CONFIG_GPIO(33, 1, 0, 0)
 124 #define ASIC3_GPIOC2_LED2               ASIC3_CONFIG_GPIO(34, 1, 0, 0)
 125 #define ASIC3_GPIOC3_SPI_RXD            ASIC3_CONFIG_GPIO(35, 1, 0, 0)
 126 #define ASIC3_GPIOC4_CF_nCD             ASIC3_CONFIG_GPIO(36, 1, 0, 0)
 127 #define ASIC3_GPIOC4_SPI_TXD            ASIC3_CONFIG_GPIO(36, 1, 1, 0)
 128 #define ASIC3_GPIOC5_SPI_CLK            ASIC3_CONFIG_GPIO(37, 1, 1, 0)
 129 #define ASIC3_GPIOC5_nCIOW              ASIC3_CONFIG_GPIO(37, 1, 1, 0)
 130 #define ASIC3_GPIOC6_nCIOR              ASIC3_CONFIG_GPIO(38, 1, 1, 0)
 131 #define ASIC3_GPIOC7_nPCE_1             ASIC3_CONFIG_GPIO(39, 1, 0, 0)
 132 #define ASIC3_GPIOC8_nPCE_2             ASIC3_CONFIG_GPIO(40, 1, 0, 0)
 133 #define ASIC3_GPIOC9_nPOE               ASIC3_CONFIG_GPIO(41, 1, 0, 0)
 134 #define ASIC3_GPIOC10_nPWE              ASIC3_CONFIG_GPIO(42, 1, 0, 0)
 135 #define ASIC3_GPIOC11_PSKTSEL           ASIC3_CONFIG_GPIO(43, 1, 0, 0)
 136 #define ASIC3_GPIOC12_nPREG             ASIC3_CONFIG_GPIO(44, 1, 0, 0)
 137 #define ASIC3_GPIOC13_nPWAIT            ASIC3_CONFIG_GPIO(45, 1, 1, 0)
 138 #define ASIC3_GPIOC14_nPIOIS16          ASIC3_CONFIG_GPIO(46, 1, 1, 0)
 139 #define ASIC3_GPIOC15_nPIOR             ASIC3_CONFIG_GPIO(47, 1, 0, 0)
 140 #define ASIC3_GPIOD4_CF_nCD             ASIC3_CONFIG_GPIO(52, 1, 0, 0)
 141 #define ASIC3_GPIOD11_nCIOIS16          ASIC3_CONFIG_GPIO(59, 1, 0, 0)
 142 #define ASIC3_GPIOD12_nCWAIT            ASIC3_CONFIG_GPIO(60, 1, 0, 0)
 143 #define ASIC3_GPIOD15_nPIOW             ASIC3_CONFIG_GPIO(63, 1, 0, 0)
 144 
 145 
 146 #define ASIC3_SPI_Base                0x0400
 147 #define ASIC3_SPI_Control               0x0000
 148 #define ASIC3_SPI_TxData                0x0004
 149 #define ASIC3_SPI_RxData                0x0008
 150 #define ASIC3_SPI_Int                   0x000c
 151 #define ASIC3_SPI_Status                0x0010
 152 
 153 #define SPI_CONTROL_SPR(clk)      ((clk) & 0x0f)  /* Clock rate */
 154 
 155 #define ASIC3_PWM_0_Base                0x0500
 156 #define ASIC3_PWM_1_Base                0x0600
 157 #define ASIC3_PWM_TimeBase              0x0000
 158 #define ASIC3_PWM_PeriodTime            0x0004
 159 #define ASIC3_PWM_DutyTime              0x0008
 160 
 161 #define PWM_TIMEBASE_VALUE(x)    ((x)&0xf)   /* Low 4 bits sets time base */
 162 #define PWM_TIMEBASE_ENABLE     (1 << 4)   /* Enable clock */
 163 
 164 #define ASIC3_NUM_LEDS                  3
 165 #define ASIC3_LED_0_Base                0x0700
 166 #define ASIC3_LED_1_Base                0x0800
 167 #define ASIC3_LED_2_Base                      0x0900
 168 #define ASIC3_LED_TimeBase              0x0000    /* R/W  7 bits */
 169 #define ASIC3_LED_PeriodTime            0x0004    /* R/W 12 bits */
 170 #define ASIC3_LED_DutyTime              0x0008    /* R/W 12 bits */
 171 #define ASIC3_LED_AutoStopCount         0x000c    /* R/W 16 bits */
 172 
 173 /* LED TimeBase bits - match ASIC2 */
 174 #define LED_TBS         0x0f /* Low 4 bits sets time base, max = 13 */
 175                              /* Note: max = 5 on hx4700 */
 176                              /* 0: maximum time base */
 177                              /* 1: maximum time base / 2 */
 178                              /* n: maximum time base / 2^n */
 179 
 180 #define LED_EN          (1 << 4) /* LED ON/OFF 0:off, 1:on */
 181 #define LED_AUTOSTOP    (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
 182 #define LED_ALWAYS      (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
 183 
 184 #define ASIC3_CLOCK_BASE           0x0A00
 185 #define ASIC3_CLOCK_CDEX           0x00
 186 #define ASIC3_CLOCK_SEL            0x04
 187 
 188 #define CLOCK_CDEX_SOURCE       (1 << 0)  /* 2 bits */
 189 #define CLOCK_CDEX_SOURCE0      (1 << 0)
 190 #define CLOCK_CDEX_SOURCE1      (1 << 1)
 191 #define CLOCK_CDEX_SPI          (1 << 2)
 192 #define CLOCK_CDEX_OWM          (1 << 3)
 193 #define CLOCK_CDEX_PWM0         (1 << 4)
 194 #define CLOCK_CDEX_PWM1         (1 << 5)
 195 #define CLOCK_CDEX_LED0         (1 << 6)
 196 #define CLOCK_CDEX_LED1         (1 << 7)
 197 #define CLOCK_CDEX_LED2         (1 << 8)
 198 
 199 /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
 200 #define CLOCK_CDEX_SD_HOST      (1 << 9)   /* R/W: SD host clock source */
 201 #define CLOCK_CDEX_SD_BUS       (1 << 10)  /* R/W: SD bus clock source ctrl */
 202 #define CLOCK_CDEX_SMBUS        (1 << 11)
 203 #define CLOCK_CDEX_CONTROL_CX   (1 << 12)
 204 
 205 #define CLOCK_CDEX_EX0          (1 << 13)  /* R/W: 32.768 kHz crystal */
 206 #define CLOCK_CDEX_EX1          (1 << 14)  /* R/W: 24.576 MHz crystal */
 207 
 208 #define CLOCK_SEL_SD_HCLK_SEL   (1 << 0)   /* R/W: SDIO host clock select */
 209 #define CLOCK_SEL_SD_BCLK_SEL   (1 << 1)   /* R/W: SDIO bus clock select */
 210 
 211 /* R/W: INT clock source control (32.768 kHz) */
 212 #define CLOCK_SEL_CX            (1 << 2)
 213 
 214 
 215 #define ASIC3_INTR_BASE         0x0B00
 216 
 217 #define ASIC3_INTR_INT_MASK       0x00  /* Interrupt mask control */
 218 #define ASIC3_INTR_P_INT_STAT     0x04  /* Peripheral interrupt status */
 219 #define ASIC3_INTR_INT_CPS        0x08  /* Interrupt timer clock pre-scale */
 220 #define ASIC3_INTR_INT_TBS        0x0c  /* Interrupt timer set */
 221 
 222 #define ASIC3_INTMASK_GINTMASK    (1 << 0)  /* Global INTs mask 1:enable */
 223 #define ASIC3_INTMASK_GINTEL      (1 << 1)  /* 1: rising edge, 0: hi level */
 224 #define ASIC3_INTMASK_MASK0       (1 << 2)
 225 #define ASIC3_INTMASK_MASK1       (1 << 3)
 226 #define ASIC3_INTMASK_MASK2       (1 << 4)
 227 #define ASIC3_INTMASK_MASK3       (1 << 5)
 228 #define ASIC3_INTMASK_MASK4       (1 << 6)
 229 #define ASIC3_INTMASK_MASK5       (1 << 7)
 230 
 231 #define ASIC3_INTR_PERIPHERAL_A   (1 << 0)
 232 #define ASIC3_INTR_PERIPHERAL_B   (1 << 1)
 233 #define ASIC3_INTR_PERIPHERAL_C   (1 << 2)
 234 #define ASIC3_INTR_PERIPHERAL_D   (1 << 3)
 235 #define ASIC3_INTR_LED0           (1 << 4)
 236 #define ASIC3_INTR_LED1           (1 << 5)
 237 #define ASIC3_INTR_LED2           (1 << 6)
 238 #define ASIC3_INTR_SPI            (1 << 7)
 239 #define ASIC3_INTR_SMBUS          (1 << 8)
 240 #define ASIC3_INTR_OWM            (1 << 9)
 241 
 242 #define ASIC3_INTR_CPS(x)         ((x)&0x0f)    /* 4 bits, max 14 */
 243 #define ASIC3_INTR_CPS_SET        (1 << 4)    /* Time base enable */
 244 
 245 
 246 /* Basic control of the SD ASIC */
 247 #define ASIC3_SDHWCTRL_BASE     0x0E00
 248 #define ASIC3_SDHWCTRL_SDCONF     0x00
 249 
 250 #define ASIC3_SDHWCTRL_SUSPEND    (1 << 0)  /* 1=suspend all SD operations */
 251 #define ASIC3_SDHWCTRL_CLKSEL     (1 << 1)  /* 1=SDICK, 0=HCLK */
 252 #define ASIC3_SDHWCTRL_PCLR       (1 << 2)  /* All registers of SDIO cleared */
 253 #define ASIC3_SDHWCTRL_LEVCD      (1 << 3)  /* SD card detection: 0:low */
 254 
 255 /* SD card write protection: 0=high */
 256 #define ASIC3_SDHWCTRL_LEVWP      (1 << 4)
 257 #define ASIC3_SDHWCTRL_SDLED      (1 << 5)  /* SD card LED signal 0=disable */
 258 
 259 /* SD card power supply ctrl 1=enable */
 260 #define ASIC3_SDHWCTRL_SDPWR      (1 << 6)
 261 
 262 #define ASIC3_EXTCF_BASE        0x1100
 263 
 264 #define ASIC3_EXTCF_SELECT        0x00
 265 #define ASIC3_EXTCF_RESET         0x04
 266 
 267 #define ASIC3_EXTCF_SMOD0                (1 << 0)  /* slot number of mode 0 */
 268 #define ASIC3_EXTCF_SMOD1                (1 << 1)  /* slot number of mode 1 */
 269 #define ASIC3_EXTCF_SMOD2                (1 << 2)  /* slot number of mode 2 */
 270 #define ASIC3_EXTCF_OWM_EN               (1 << 4)  /* enable onewire module */
 271 #define ASIC3_EXTCF_OWM_SMB              (1 << 5)  /* OWM bus selection */
 272 #define ASIC3_EXTCF_OWM_RESET            (1 << 6)  /* ?? used by OWM and CF */
 273 #define ASIC3_EXTCF_CF0_SLEEP_MODE       (1 << 7)  /* CF0 sleep state */
 274 #define ASIC3_EXTCF_CF1_SLEEP_MODE       (1 << 8)  /* CF1 sleep state */
 275 #define ASIC3_EXTCF_CF0_PWAIT_EN         (1 << 10) /* CF0 PWAIT_n control */
 276 #define ASIC3_EXTCF_CF1_PWAIT_EN         (1 << 11) /* CF1 PWAIT_n control */
 277 #define ASIC3_EXTCF_CF0_BUF_EN           (1 << 12) /* CF0 buffer control */
 278 #define ASIC3_EXTCF_CF1_BUF_EN           (1 << 13) /* CF1 buffer control */
 279 #define ASIC3_EXTCF_SD_MEM_ENABLE        (1 << 14)
 280 #define ASIC3_EXTCF_CF_SLEEP             (1 << 15) /* CF sleep mode control */
 281 
 282 /*********************************************
 283  *  The Onewire interface (DS1WM) is handled
 284  *  by the ds1wm driver.
 285  *
 286  *********************************************/
 287 
 288 #define ASIC3_OWM_BASE          0xC00
 289 
 290 /*****************************************************************************
 291  *  The SD configuration registers are at a completely different location
 292  *  in memory.  They are divided into three sets of registers:
 293  *
 294  *  SD_CONFIG         Core configuration register
 295  *  SD_CTRL           Control registers for SD operations
 296  *  SDIO_CTRL         Control registers for SDIO operations
 297  *
 298  *****************************************************************************/
 299 #define ASIC3_SD_CONFIG_BASE    0x0400 /* Assumes 32 bit addressing */
 300 #define ASIC3_SD_CONFIG_SIZE    0x0200 /* Assumes 32 bit addressing */
 301 #define ASIC3_SD_CTRL_BASE      0x1000
 302 #define ASIC3_SDIO_CTRL_BASE    0x1200
 303 
 304 #define ASIC3_MAP_SIZE_32BIT    0x2000
 305 #define ASIC3_MAP_SIZE_16BIT    0x1000
 306 
 307 /* Functions needed by leds-asic3 */
 308 
 309 struct asic3;
 310 extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
 311 extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
 312 
 313 #endif /* __ASIC3_H__ */