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8 #ifndef __LINUX_MFD_WM8400_PRIV_H
9 #define __LINUX_MFD_WM8400_PRIV_H
10
11 #include <linux/mfd/wm8400.h>
12 #include <linux/mutex.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #define WM8400_REGISTER_COUNT 0x55
17
18 struct wm8400 {
19 struct device *dev;
20 struct regmap *regmap;
21
22 struct platform_device regulators[6];
23 };
24
25
26
27
28 #define WM8400_RESET_ID 0x00
29 #define WM8400_ID 0x01
30 #define WM8400_POWER_MANAGEMENT_1 0x02
31 #define WM8400_POWER_MANAGEMENT_2 0x03
32 #define WM8400_POWER_MANAGEMENT_3 0x04
33 #define WM8400_AUDIO_INTERFACE_1 0x05
34 #define WM8400_AUDIO_INTERFACE_2 0x06
35 #define WM8400_CLOCKING_1 0x07
36 #define WM8400_CLOCKING_2 0x08
37 #define WM8400_AUDIO_INTERFACE_3 0x09
38 #define WM8400_AUDIO_INTERFACE_4 0x0A
39 #define WM8400_DAC_CTRL 0x0B
40 #define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C
41 #define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D
42 #define WM8400_DIGITAL_SIDE_TONE 0x0E
43 #define WM8400_ADC_CTRL 0x0F
44 #define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10
45 #define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11
46 #define WM8400_GPIO_CTRL_1 0x12
47 #define WM8400_GPIO1_GPIO2 0x13
48 #define WM8400_GPIO3_GPIO4 0x14
49 #define WM8400_GPIO5_GPIO6 0x15
50 #define WM8400_GPIOCTRL_2 0x16
51 #define WM8400_GPIO_POL 0x17
52 #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18
53 #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19
54 #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
55 #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
56 #define WM8400_LEFT_OUTPUT_VOLUME 0x1C
57 #define WM8400_RIGHT_OUTPUT_VOLUME 0x1D
58 #define WM8400_LINE_OUTPUTS_VOLUME 0x1E
59 #define WM8400_OUT3_4_VOLUME 0x1F
60 #define WM8400_LEFT_OPGA_VOLUME 0x20
61 #define WM8400_RIGHT_OPGA_VOLUME 0x21
62 #define WM8400_SPEAKER_VOLUME 0x22
63 #define WM8400_CLASSD1 0x23
64 #define WM8400_CLASSD3 0x25
65 #define WM8400_INPUT_MIXER1 0x27
66 #define WM8400_INPUT_MIXER2 0x28
67 #define WM8400_INPUT_MIXER3 0x29
68 #define WM8400_INPUT_MIXER4 0x2A
69 #define WM8400_INPUT_MIXER5 0x2B
70 #define WM8400_INPUT_MIXER6 0x2C
71 #define WM8400_OUTPUT_MIXER1 0x2D
72 #define WM8400_OUTPUT_MIXER2 0x2E
73 #define WM8400_OUTPUT_MIXER3 0x2F
74 #define WM8400_OUTPUT_MIXER4 0x30
75 #define WM8400_OUTPUT_MIXER5 0x31
76 #define WM8400_OUTPUT_MIXER6 0x32
77 #define WM8400_OUT3_4_MIXER 0x33
78 #define WM8400_LINE_MIXER1 0x34
79 #define WM8400_LINE_MIXER2 0x35
80 #define WM8400_SPEAKER_MIXER 0x36
81 #define WM8400_ADDITIONAL_CONTROL 0x37
82 #define WM8400_ANTIPOP1 0x38
83 #define WM8400_ANTIPOP2 0x39
84 #define WM8400_MICBIAS 0x3A
85 #define WM8400_FLL_CONTROL_1 0x3C
86 #define WM8400_FLL_CONTROL_2 0x3D
87 #define WM8400_FLL_CONTROL_3 0x3E
88 #define WM8400_FLL_CONTROL_4 0x3F
89 #define WM8400_LDO1_CONTROL 0x41
90 #define WM8400_LDO2_CONTROL 0x42
91 #define WM8400_LDO3_CONTROL 0x43
92 #define WM8400_LDO4_CONTROL 0x44
93 #define WM8400_DCDC1_CONTROL_1 0x46
94 #define WM8400_DCDC1_CONTROL_2 0x47
95 #define WM8400_DCDC2_CONTROL_1 0x48
96 #define WM8400_DCDC2_CONTROL_2 0x49
97 #define WM8400_INTERFACE 0x4B
98 #define WM8400_PM_GENERAL 0x4C
99 #define WM8400_PM_SHUTDOWN_CONTROL 0x4E
100 #define WM8400_INTERRUPT_STATUS_1 0x4F
101 #define WM8400_INTERRUPT_STATUS_1_MASK 0x50
102 #define WM8400_INTERRUPT_LEVELS 0x51
103 #define WM8400_SHUTDOWN_REASON 0x52
104 #define WM8400_LINE_CIRCUITS 0x54
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112
113 #define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF
114 #define WM8400_SW_RESET_CHIP_ID_SHIFT 0
115 #define WM8400_SW_RESET_CHIP_ID_WIDTH 16
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120 #define WM8400_CHIP_REV_MASK 0x7000
121 #define WM8400_CHIP_REV_SHIFT 12
122 #define WM8400_CHIP_REV_WIDTH 3
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127 #define WM8400_IRQ 0x1000
128 #define WM8400_IRQ_MASK 0x1000
129 #define WM8400_IRQ_SHIFT 12
130 #define WM8400_IRQ_WIDTH 1
131 #define WM8400_TEMPOK 0x0800
132 #define WM8400_TEMPOK_MASK 0x0800
133 #define WM8400_TEMPOK_SHIFT 11
134 #define WM8400_TEMPOK_WIDTH 1
135 #define WM8400_MIC1SHRT 0x0400
136 #define WM8400_MIC1SHRT_MASK 0x0400
137 #define WM8400_MIC1SHRT_SHIFT 10
138 #define WM8400_MIC1SHRT_WIDTH 1
139 #define WM8400_MIC1DET 0x0200
140 #define WM8400_MIC1DET_MASK 0x0200
141 #define WM8400_MIC1DET_SHIFT 9
142 #define WM8400_MIC1DET_WIDTH 1
143 #define WM8400_FLL_LCK 0x0100
144 #define WM8400_FLL_LCK_MASK 0x0100
145 #define WM8400_FLL_LCK_SHIFT 8
146 #define WM8400_FLL_LCK_WIDTH 1
147 #define WM8400_GPIO_STATUS_MASK 0x00FF
148 #define WM8400_GPIO_STATUS_SHIFT 0
149 #define WM8400_GPIO_STATUS_WIDTH 8
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153
154 #define WM8400_GPIO2_DEB_ENA 0x8000
155 #define WM8400_GPIO2_DEB_ENA_MASK 0x8000
156 #define WM8400_GPIO2_DEB_ENA_SHIFT 15
157 #define WM8400_GPIO2_DEB_ENA_WIDTH 1
158 #define WM8400_GPIO2_IRQ_ENA 0x4000
159 #define WM8400_GPIO2_IRQ_ENA_MASK 0x4000
160 #define WM8400_GPIO2_IRQ_ENA_SHIFT 14
161 #define WM8400_GPIO2_IRQ_ENA_WIDTH 1
162 #define WM8400_GPIO2_PU 0x2000
163 #define WM8400_GPIO2_PU_MASK 0x2000
164 #define WM8400_GPIO2_PU_SHIFT 13
165 #define WM8400_GPIO2_PU_WIDTH 1
166 #define WM8400_GPIO2_PD 0x1000
167 #define WM8400_GPIO2_PD_MASK 0x1000
168 #define WM8400_GPIO2_PD_SHIFT 12
169 #define WM8400_GPIO2_PD_WIDTH 1
170 #define WM8400_GPIO2_SEL_MASK 0x0F00
171 #define WM8400_GPIO2_SEL_SHIFT 8
172 #define WM8400_GPIO2_SEL_WIDTH 4
173 #define WM8400_GPIO1_DEB_ENA 0x0080
174 #define WM8400_GPIO1_DEB_ENA_MASK 0x0080
175 #define WM8400_GPIO1_DEB_ENA_SHIFT 7
176 #define WM8400_GPIO1_DEB_ENA_WIDTH 1
177 #define WM8400_GPIO1_IRQ_ENA 0x0040
178 #define WM8400_GPIO1_IRQ_ENA_MASK 0x0040
179 #define WM8400_GPIO1_IRQ_ENA_SHIFT 6
180 #define WM8400_GPIO1_IRQ_ENA_WIDTH 1
181 #define WM8400_GPIO1_PU 0x0020
182 #define WM8400_GPIO1_PU_MASK 0x0020
183 #define WM8400_GPIO1_PU_SHIFT 5
184 #define WM8400_GPIO1_PU_WIDTH 1
185 #define WM8400_GPIO1_PD 0x0010
186 #define WM8400_GPIO1_PD_MASK 0x0010
187 #define WM8400_GPIO1_PD_SHIFT 4
188 #define WM8400_GPIO1_PD_WIDTH 1
189 #define WM8400_GPIO1_SEL_MASK 0x000F
190 #define WM8400_GPIO1_SEL_SHIFT 0
191 #define WM8400_GPIO1_SEL_WIDTH 4
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195
196 #define WM8400_GPIO4_DEB_ENA 0x8000
197 #define WM8400_GPIO4_DEB_ENA_MASK 0x8000
198 #define WM8400_GPIO4_DEB_ENA_SHIFT 15
199 #define WM8400_GPIO4_DEB_ENA_WIDTH 1
200 #define WM8400_GPIO4_IRQ_ENA 0x4000
201 #define WM8400_GPIO4_IRQ_ENA_MASK 0x4000
202 #define WM8400_GPIO4_IRQ_ENA_SHIFT 14
203 #define WM8400_GPIO4_IRQ_ENA_WIDTH 1
204 #define WM8400_GPIO4_PU 0x2000
205 #define WM8400_GPIO4_PU_MASK 0x2000
206 #define WM8400_GPIO4_PU_SHIFT 13
207 #define WM8400_GPIO4_PU_WIDTH 1
208 #define WM8400_GPIO4_PD 0x1000
209 #define WM8400_GPIO4_PD_MASK 0x1000
210 #define WM8400_GPIO4_PD_SHIFT 12
211 #define WM8400_GPIO4_PD_WIDTH 1
212 #define WM8400_GPIO4_SEL_MASK 0x0F00
213 #define WM8400_GPIO4_SEL_SHIFT 8
214 #define WM8400_GPIO4_SEL_WIDTH 4
215 #define WM8400_GPIO3_DEB_ENA 0x0080
216 #define WM8400_GPIO3_DEB_ENA_MASK 0x0080
217 #define WM8400_GPIO3_DEB_ENA_SHIFT 7
218 #define WM8400_GPIO3_DEB_ENA_WIDTH 1
219 #define WM8400_GPIO3_IRQ_ENA 0x0040
220 #define WM8400_GPIO3_IRQ_ENA_MASK 0x0040
221 #define WM8400_GPIO3_IRQ_ENA_SHIFT 6
222 #define WM8400_GPIO3_IRQ_ENA_WIDTH 1
223 #define WM8400_GPIO3_PU 0x0020
224 #define WM8400_GPIO3_PU_MASK 0x0020
225 #define WM8400_GPIO3_PU_SHIFT 5
226 #define WM8400_GPIO3_PU_WIDTH 1
227 #define WM8400_GPIO3_PD 0x0010
228 #define WM8400_GPIO3_PD_MASK 0x0010
229 #define WM8400_GPIO3_PD_SHIFT 4
230 #define WM8400_GPIO3_PD_WIDTH 1
231 #define WM8400_GPIO3_SEL_MASK 0x000F
232 #define WM8400_GPIO3_SEL_SHIFT 0
233 #define WM8400_GPIO3_SEL_WIDTH 4
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237
238 #define WM8400_GPIO6_DEB_ENA 0x8000
239 #define WM8400_GPIO6_DEB_ENA_MASK 0x8000
240 #define WM8400_GPIO6_DEB_ENA_SHIFT 15
241 #define WM8400_GPIO6_DEB_ENA_WIDTH 1
242 #define WM8400_GPIO6_IRQ_ENA 0x4000
243 #define WM8400_GPIO6_IRQ_ENA_MASK 0x4000
244 #define WM8400_GPIO6_IRQ_ENA_SHIFT 14
245 #define WM8400_GPIO6_IRQ_ENA_WIDTH 1
246 #define WM8400_GPIO6_PU 0x2000
247 #define WM8400_GPIO6_PU_MASK 0x2000
248 #define WM8400_GPIO6_PU_SHIFT 13
249 #define WM8400_GPIO6_PU_WIDTH 1
250 #define WM8400_GPIO6_PD 0x1000
251 #define WM8400_GPIO6_PD_MASK 0x1000
252 #define WM8400_GPIO6_PD_SHIFT 12
253 #define WM8400_GPIO6_PD_WIDTH 1
254 #define WM8400_GPIO6_SEL_MASK 0x0F00
255 #define WM8400_GPIO6_SEL_SHIFT 8
256 #define WM8400_GPIO6_SEL_WIDTH 4
257 #define WM8400_GPIO5_DEB_ENA 0x0080
258 #define WM8400_GPIO5_DEB_ENA_MASK 0x0080
259 #define WM8400_GPIO5_DEB_ENA_SHIFT 7
260 #define WM8400_GPIO5_DEB_ENA_WIDTH 1
261 #define WM8400_GPIO5_IRQ_ENA 0x0040
262 #define WM8400_GPIO5_IRQ_ENA_MASK 0x0040
263 #define WM8400_GPIO5_IRQ_ENA_SHIFT 6
264 #define WM8400_GPIO5_IRQ_ENA_WIDTH 1
265 #define WM8400_GPIO5_PU 0x0020
266 #define WM8400_GPIO5_PU_MASK 0x0020
267 #define WM8400_GPIO5_PU_SHIFT 5
268 #define WM8400_GPIO5_PU_WIDTH 1
269 #define WM8400_GPIO5_PD 0x0010
270 #define WM8400_GPIO5_PD_MASK 0x0010
271 #define WM8400_GPIO5_PD_SHIFT 4
272 #define WM8400_GPIO5_PD_WIDTH 1
273 #define WM8400_GPIO5_SEL_MASK 0x000F
274 #define WM8400_GPIO5_SEL_SHIFT 0
275 #define WM8400_GPIO5_SEL_WIDTH 4
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279
280 #define WM8400_TEMPOK_IRQ_ENA 0x0800
281 #define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800
282 #define WM8400_TEMPOK_IRQ_ENA_SHIFT 11
283 #define WM8400_TEMPOK_IRQ_ENA_WIDTH 1
284 #define WM8400_MIC1SHRT_IRQ_ENA 0x0400
285 #define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400
286 #define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10
287 #define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1
288 #define WM8400_MIC1DET_IRQ_ENA 0x0200
289 #define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200
290 #define WM8400_MIC1DET_IRQ_ENA_SHIFT 9
291 #define WM8400_MIC1DET_IRQ_ENA_WIDTH 1
292 #define WM8400_FLL_LCK_IRQ_ENA 0x0100
293 #define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100
294 #define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8
295 #define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1
296 #define WM8400_GPI8_DEB_ENA 0x0080
297 #define WM8400_GPI8_DEB_ENA_MASK 0x0080
298 #define WM8400_GPI8_DEB_ENA_SHIFT 7
299 #define WM8400_GPI8_DEB_ENA_WIDTH 1
300 #define WM8400_GPI8_IRQ_ENA 0x0040
301 #define WM8400_GPI8_IRQ_ENA_MASK 0x0040
302 #define WM8400_GPI8_IRQ_ENA_SHIFT 6
303 #define WM8400_GPI8_IRQ_ENA_WIDTH 1
304 #define WM8400_GPI8_ENA 0x0010
305 #define WM8400_GPI8_ENA_MASK 0x0010
306 #define WM8400_GPI8_ENA_SHIFT 4
307 #define WM8400_GPI8_ENA_WIDTH 1
308 #define WM8400_GPI7_DEB_ENA 0x0008
309 #define WM8400_GPI7_DEB_ENA_MASK 0x0008
310 #define WM8400_GPI7_DEB_ENA_SHIFT 3
311 #define WM8400_GPI7_DEB_ENA_WIDTH 1
312 #define WM8400_GPI7_IRQ_ENA 0x0004
313 #define WM8400_GPI7_IRQ_ENA_MASK 0x0004
314 #define WM8400_GPI7_IRQ_ENA_SHIFT 2
315 #define WM8400_GPI7_IRQ_ENA_WIDTH 1
316 #define WM8400_GPI7_ENA 0x0001
317 #define WM8400_GPI7_ENA_MASK 0x0001
318 #define WM8400_GPI7_ENA_SHIFT 0
319 #define WM8400_GPI7_ENA_WIDTH 1
320
321
322
323
324 #define WM8400_IRQ_INV 0x1000
325 #define WM8400_IRQ_INV_MASK 0x1000
326 #define WM8400_IRQ_INV_SHIFT 12
327 #define WM8400_IRQ_INV_WIDTH 1
328 #define WM8400_TEMPOK_POL 0x0800
329 #define WM8400_TEMPOK_POL_MASK 0x0800
330 #define WM8400_TEMPOK_POL_SHIFT 11
331 #define WM8400_TEMPOK_POL_WIDTH 1
332 #define WM8400_MIC1SHRT_POL 0x0400
333 #define WM8400_MIC1SHRT_POL_MASK 0x0400
334 #define WM8400_MIC1SHRT_POL_SHIFT 10
335 #define WM8400_MIC1SHRT_POL_WIDTH 1
336 #define WM8400_MIC1DET_POL 0x0200
337 #define WM8400_MIC1DET_POL_MASK 0x0200
338 #define WM8400_MIC1DET_POL_SHIFT 9
339 #define WM8400_MIC1DET_POL_WIDTH 1
340 #define WM8400_FLL_LCK_POL 0x0100
341 #define WM8400_FLL_LCK_POL_MASK 0x0100
342 #define WM8400_FLL_LCK_POL_SHIFT 8
343 #define WM8400_FLL_LCK_POL_WIDTH 1
344 #define WM8400_GPIO_POL_MASK 0x00FF
345 #define WM8400_GPIO_POL_SHIFT 0
346 #define WM8400_GPIO_POL_WIDTH 8
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348
349
350
351 #define WM8400_LDO1_ENA 0x8000
352 #define WM8400_LDO1_ENA_MASK 0x8000
353 #define WM8400_LDO1_ENA_SHIFT 15
354 #define WM8400_LDO1_ENA_WIDTH 1
355 #define WM8400_LDO1_SWI 0x4000
356 #define WM8400_LDO1_SWI_MASK 0x4000
357 #define WM8400_LDO1_SWI_SHIFT 14
358 #define WM8400_LDO1_SWI_WIDTH 1
359 #define WM8400_LDO1_OPFLT 0x1000
360 #define WM8400_LDO1_OPFLT_MASK 0x1000
361 #define WM8400_LDO1_OPFLT_SHIFT 12
362 #define WM8400_LDO1_OPFLT_WIDTH 1
363 #define WM8400_LDO1_ERRACT 0x0800
364 #define WM8400_LDO1_ERRACT_MASK 0x0800
365 #define WM8400_LDO1_ERRACT_SHIFT 11
366 #define WM8400_LDO1_ERRACT_WIDTH 1
367 #define WM8400_LDO1_HIB_MODE 0x0400
368 #define WM8400_LDO1_HIB_MODE_MASK 0x0400
369 #define WM8400_LDO1_HIB_MODE_SHIFT 10
370 #define WM8400_LDO1_HIB_MODE_WIDTH 1
371 #define WM8400_LDO1_VIMG_MASK 0x03E0
372 #define WM8400_LDO1_VIMG_SHIFT 5
373 #define WM8400_LDO1_VIMG_WIDTH 5
374 #define WM8400_LDO1_VSEL_MASK 0x001F
375 #define WM8400_LDO1_VSEL_SHIFT 0
376 #define WM8400_LDO1_VSEL_WIDTH 5
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380
381 #define WM8400_LDO2_ENA 0x8000
382 #define WM8400_LDO2_ENA_MASK 0x8000
383 #define WM8400_LDO2_ENA_SHIFT 15
384 #define WM8400_LDO2_ENA_WIDTH 1
385 #define WM8400_LDO2_SWI 0x4000
386 #define WM8400_LDO2_SWI_MASK 0x4000
387 #define WM8400_LDO2_SWI_SHIFT 14
388 #define WM8400_LDO2_SWI_WIDTH 1
389 #define WM8400_LDO2_OPFLT 0x1000
390 #define WM8400_LDO2_OPFLT_MASK 0x1000
391 #define WM8400_LDO2_OPFLT_SHIFT 12
392 #define WM8400_LDO2_OPFLT_WIDTH 1
393 #define WM8400_LDO2_ERRACT 0x0800
394 #define WM8400_LDO2_ERRACT_MASK 0x0800
395 #define WM8400_LDO2_ERRACT_SHIFT 11
396 #define WM8400_LDO2_ERRACT_WIDTH 1
397 #define WM8400_LDO2_HIB_MODE 0x0400
398 #define WM8400_LDO2_HIB_MODE_MASK 0x0400
399 #define WM8400_LDO2_HIB_MODE_SHIFT 10
400 #define WM8400_LDO2_HIB_MODE_WIDTH 1
401 #define WM8400_LDO2_VIMG_MASK 0x03E0
402 #define WM8400_LDO2_VIMG_SHIFT 5
403 #define WM8400_LDO2_VIMG_WIDTH 5
404 #define WM8400_LDO2_VSEL_MASK 0x001F
405 #define WM8400_LDO2_VSEL_SHIFT 0
406 #define WM8400_LDO2_VSEL_WIDTH 5
407
408
409
410
411 #define WM8400_LDO3_ENA 0x8000
412 #define WM8400_LDO3_ENA_MASK 0x8000
413 #define WM8400_LDO3_ENA_SHIFT 15
414 #define WM8400_LDO3_ENA_WIDTH 1
415 #define WM8400_LDO3_SWI 0x4000
416 #define WM8400_LDO3_SWI_MASK 0x4000
417 #define WM8400_LDO3_SWI_SHIFT 14
418 #define WM8400_LDO3_SWI_WIDTH 1
419 #define WM8400_LDO3_OPFLT 0x1000
420 #define WM8400_LDO3_OPFLT_MASK 0x1000
421 #define WM8400_LDO3_OPFLT_SHIFT 12
422 #define WM8400_LDO3_OPFLT_WIDTH 1
423 #define WM8400_LDO3_ERRACT 0x0800
424 #define WM8400_LDO3_ERRACT_MASK 0x0800
425 #define WM8400_LDO3_ERRACT_SHIFT 11
426 #define WM8400_LDO3_ERRACT_WIDTH 1
427 #define WM8400_LDO3_HIB_MODE 0x0400
428 #define WM8400_LDO3_HIB_MODE_MASK 0x0400
429 #define WM8400_LDO3_HIB_MODE_SHIFT 10
430 #define WM8400_LDO3_HIB_MODE_WIDTH 1
431 #define WM8400_LDO3_VIMG_MASK 0x03E0
432 #define WM8400_LDO3_VIMG_SHIFT 5
433 #define WM8400_LDO3_VIMG_WIDTH 5
434 #define WM8400_LDO3_VSEL_MASK 0x001F
435 #define WM8400_LDO3_VSEL_SHIFT 0
436 #define WM8400_LDO3_VSEL_WIDTH 5
437
438
439
440
441 #define WM8400_LDO4_ENA 0x8000
442 #define WM8400_LDO4_ENA_MASK 0x8000
443 #define WM8400_LDO4_ENA_SHIFT 15
444 #define WM8400_LDO4_ENA_WIDTH 1
445 #define WM8400_LDO4_SWI 0x4000
446 #define WM8400_LDO4_SWI_MASK 0x4000
447 #define WM8400_LDO4_SWI_SHIFT 14
448 #define WM8400_LDO4_SWI_WIDTH 1
449 #define WM8400_LDO4_OPFLT 0x1000
450 #define WM8400_LDO4_OPFLT_MASK 0x1000
451 #define WM8400_LDO4_OPFLT_SHIFT 12
452 #define WM8400_LDO4_OPFLT_WIDTH 1
453 #define WM8400_LDO4_ERRACT 0x0800
454 #define WM8400_LDO4_ERRACT_MASK 0x0800
455 #define WM8400_LDO4_ERRACT_SHIFT 11
456 #define WM8400_LDO4_ERRACT_WIDTH 1
457 #define WM8400_LDO4_HIB_MODE 0x0400
458 #define WM8400_LDO4_HIB_MODE_MASK 0x0400
459 #define WM8400_LDO4_HIB_MODE_SHIFT 10
460 #define WM8400_LDO4_HIB_MODE_WIDTH 1
461 #define WM8400_LDO4_VIMG_MASK 0x03E0
462 #define WM8400_LDO4_VIMG_SHIFT 5
463 #define WM8400_LDO4_VIMG_WIDTH 5
464 #define WM8400_LDO4_VSEL_MASK 0x001F
465 #define WM8400_LDO4_VSEL_SHIFT 0
466 #define WM8400_LDO4_VSEL_WIDTH 5
467
468
469
470
471 #define WM8400_DC1_ENA 0x8000
472 #define WM8400_DC1_ENA_MASK 0x8000
473 #define WM8400_DC1_ENA_SHIFT 15
474 #define WM8400_DC1_ENA_WIDTH 1
475 #define WM8400_DC1_ACTIVE 0x4000
476 #define WM8400_DC1_ACTIVE_MASK 0x4000
477 #define WM8400_DC1_ACTIVE_SHIFT 14
478 #define WM8400_DC1_ACTIVE_WIDTH 1
479 #define WM8400_DC1_SLEEP 0x2000
480 #define WM8400_DC1_SLEEP_MASK 0x2000
481 #define WM8400_DC1_SLEEP_SHIFT 13
482 #define WM8400_DC1_SLEEP_WIDTH 1
483 #define WM8400_DC1_OPFLT 0x1000
484 #define WM8400_DC1_OPFLT_MASK 0x1000
485 #define WM8400_DC1_OPFLT_SHIFT 12
486 #define WM8400_DC1_OPFLT_WIDTH 1
487 #define WM8400_DC1_ERRACT 0x0800
488 #define WM8400_DC1_ERRACT_MASK 0x0800
489 #define WM8400_DC1_ERRACT_SHIFT 11
490 #define WM8400_DC1_ERRACT_WIDTH 1
491 #define WM8400_DC1_HIB_MODE 0x0400
492 #define WM8400_DC1_HIB_MODE_MASK 0x0400
493 #define WM8400_DC1_HIB_MODE_SHIFT 10
494 #define WM8400_DC1_HIB_MODE_WIDTH 1
495 #define WM8400_DC1_SOFTST_MASK 0x0300
496 #define WM8400_DC1_SOFTST_SHIFT 8
497 #define WM8400_DC1_SOFTST_WIDTH 2
498 #define WM8400_DC1_OV_PROT 0x0080
499 #define WM8400_DC1_OV_PROT_MASK 0x0080
500 #define WM8400_DC1_OV_PROT_SHIFT 7
501 #define WM8400_DC1_OV_PROT_WIDTH 1
502 #define WM8400_DC1_VSEL_MASK 0x007F
503 #define WM8400_DC1_VSEL_SHIFT 0
504 #define WM8400_DC1_VSEL_WIDTH 7
505
506
507
508
509 #define WM8400_DC1_FRC_PWM 0x2000
510 #define WM8400_DC1_FRC_PWM_MASK 0x2000
511 #define WM8400_DC1_FRC_PWM_SHIFT 13
512 #define WM8400_DC1_FRC_PWM_WIDTH 1
513 #define WM8400_DC1_STBY_LIM_MASK 0x0300
514 #define WM8400_DC1_STBY_LIM_SHIFT 8
515 #define WM8400_DC1_STBY_LIM_WIDTH 2
516 #define WM8400_DC1_ACT_LIM 0x0080
517 #define WM8400_DC1_ACT_LIM_MASK 0x0080
518 #define WM8400_DC1_ACT_LIM_SHIFT 7
519 #define WM8400_DC1_ACT_LIM_WIDTH 1
520 #define WM8400_DC1_VIMG_MASK 0x007F
521 #define WM8400_DC1_VIMG_SHIFT 0
522 #define WM8400_DC1_VIMG_WIDTH 7
523
524
525
526
527 #define WM8400_DC2_ENA 0x8000
528 #define WM8400_DC2_ENA_MASK 0x8000
529 #define WM8400_DC2_ENA_SHIFT 15
530 #define WM8400_DC2_ENA_WIDTH 1
531 #define WM8400_DC2_ACTIVE 0x4000
532 #define WM8400_DC2_ACTIVE_MASK 0x4000
533 #define WM8400_DC2_ACTIVE_SHIFT 14
534 #define WM8400_DC2_ACTIVE_WIDTH 1
535 #define WM8400_DC2_SLEEP 0x2000
536 #define WM8400_DC2_SLEEP_MASK 0x2000
537 #define WM8400_DC2_SLEEP_SHIFT 13
538 #define WM8400_DC2_SLEEP_WIDTH 1
539 #define WM8400_DC2_OPFLT 0x1000
540 #define WM8400_DC2_OPFLT_MASK 0x1000
541 #define WM8400_DC2_OPFLT_SHIFT 12
542 #define WM8400_DC2_OPFLT_WIDTH 1
543 #define WM8400_DC2_ERRACT 0x0800
544 #define WM8400_DC2_ERRACT_MASK 0x0800
545 #define WM8400_DC2_ERRACT_SHIFT 11
546 #define WM8400_DC2_ERRACT_WIDTH 1
547 #define WM8400_DC2_HIB_MODE 0x0400
548 #define WM8400_DC2_HIB_MODE_MASK 0x0400
549 #define WM8400_DC2_HIB_MODE_SHIFT 10
550 #define WM8400_DC2_HIB_MODE_WIDTH 1
551 #define WM8400_DC2_SOFTST_MASK 0x0300
552 #define WM8400_DC2_SOFTST_SHIFT 8
553 #define WM8400_DC2_SOFTST_WIDTH 2
554 #define WM8400_DC2_OV_PROT 0x0080
555 #define WM8400_DC2_OV_PROT_MASK 0x0080
556 #define WM8400_DC2_OV_PROT_SHIFT 7
557 #define WM8400_DC2_OV_PROT_WIDTH 1
558 #define WM8400_DC2_VSEL_MASK 0x007F
559 #define WM8400_DC2_VSEL_SHIFT 0
560 #define WM8400_DC2_VSEL_WIDTH 7
561
562
563
564
565 #define WM8400_DC2_FRC_PWM 0x2000
566 #define WM8400_DC2_FRC_PWM_MASK 0x2000
567 #define WM8400_DC2_FRC_PWM_SHIFT 13
568 #define WM8400_DC2_FRC_PWM_WIDTH 1
569 #define WM8400_DC2_STBY_LIM_MASK 0x0300
570 #define WM8400_DC2_STBY_LIM_SHIFT 8
571 #define WM8400_DC2_STBY_LIM_WIDTH 2
572 #define WM8400_DC2_ACT_LIM 0x0080
573 #define WM8400_DC2_ACT_LIM_MASK 0x0080
574 #define WM8400_DC2_ACT_LIM_SHIFT 7
575 #define WM8400_DC2_ACT_LIM_WIDTH 1
576 #define WM8400_DC2_VIMG_MASK 0x007F
577 #define WM8400_DC2_VIMG_SHIFT 0
578 #define WM8400_DC2_VIMG_WIDTH 7
579
580
581
582
583 #define WM8400_AUTOINC 0x0008
584 #define WM8400_AUTOINC_MASK 0x0008
585 #define WM8400_AUTOINC_SHIFT 3
586 #define WM8400_AUTOINC_WIDTH 1
587 #define WM8400_ARA_ENA 0x0004
588 #define WM8400_ARA_ENA_MASK 0x0004
589 #define WM8400_ARA_ENA_SHIFT 2
590 #define WM8400_ARA_ENA_WIDTH 1
591 #define WM8400_SPI_CFG 0x0002
592 #define WM8400_SPI_CFG_MASK 0x0002
593 #define WM8400_SPI_CFG_SHIFT 1
594 #define WM8400_SPI_CFG_WIDTH 1
595
596
597
598
599 #define WM8400_CODEC_SOFTST 0x8000
600 #define WM8400_CODEC_SOFTST_MASK 0x8000
601 #define WM8400_CODEC_SOFTST_SHIFT 15
602 #define WM8400_CODEC_SOFTST_WIDTH 1
603 #define WM8400_CODEC_SOFTSD 0x4000
604 #define WM8400_CODEC_SOFTSD_MASK 0x4000
605 #define WM8400_CODEC_SOFTSD_SHIFT 14
606 #define WM8400_CODEC_SOFTSD_WIDTH 1
607 #define WM8400_CHIP_SOFTSD 0x2000
608 #define WM8400_CHIP_SOFTSD_MASK 0x2000
609 #define WM8400_CHIP_SOFTSD_SHIFT 13
610 #define WM8400_CHIP_SOFTSD_WIDTH 1
611 #define WM8400_DSLEEP1_POL 0x0008
612 #define WM8400_DSLEEP1_POL_MASK 0x0008
613 #define WM8400_DSLEEP1_POL_SHIFT 3
614 #define WM8400_DSLEEP1_POL_WIDTH 1
615 #define WM8400_DSLEEP2_POL 0x0004
616 #define WM8400_DSLEEP2_POL_MASK 0x0004
617 #define WM8400_DSLEEP2_POL_SHIFT 2
618 #define WM8400_DSLEEP2_POL_WIDTH 1
619 #define WM8400_PWR_STATE_MASK 0x0003
620 #define WM8400_PWR_STATE_SHIFT 0
621 #define WM8400_PWR_STATE_WIDTH 2
622
623
624
625
626 #define WM8400_CHIP_GT150_ERRACT 0x0200
627 #define WM8400_CHIP_GT150_ERRACT_MASK 0x0200
628 #define WM8400_CHIP_GT150_ERRACT_SHIFT 9
629 #define WM8400_CHIP_GT150_ERRACT_WIDTH 1
630 #define WM8400_CHIP_GT115_ERRACT 0x0100
631 #define WM8400_CHIP_GT115_ERRACT_MASK 0x0100
632 #define WM8400_CHIP_GT115_ERRACT_SHIFT 8
633 #define WM8400_CHIP_GT115_ERRACT_WIDTH 1
634 #define WM8400_LINE_CMP_ERRACT 0x0080
635 #define WM8400_LINE_CMP_ERRACT_MASK 0x0080
636 #define WM8400_LINE_CMP_ERRACT_SHIFT 7
637 #define WM8400_LINE_CMP_ERRACT_WIDTH 1
638 #define WM8400_UVLO_ERRACT 0x0040
639 #define WM8400_UVLO_ERRACT_MASK 0x0040
640 #define WM8400_UVLO_ERRACT_SHIFT 6
641 #define WM8400_UVLO_ERRACT_WIDTH 1
642
643
644
645
646 #define WM8400_MICD_CINT 0x8000
647 #define WM8400_MICD_CINT_MASK 0x8000
648 #define WM8400_MICD_CINT_SHIFT 15
649 #define WM8400_MICD_CINT_WIDTH 1
650 #define WM8400_MICSCD_CINT 0x4000
651 #define WM8400_MICSCD_CINT_MASK 0x4000
652 #define WM8400_MICSCD_CINT_SHIFT 14
653 #define WM8400_MICSCD_CINT_WIDTH 1
654 #define WM8400_JDL_CINT 0x2000
655 #define WM8400_JDL_CINT_MASK 0x2000
656 #define WM8400_JDL_CINT_SHIFT 13
657 #define WM8400_JDL_CINT_WIDTH 1
658 #define WM8400_JDR_CINT 0x1000
659 #define WM8400_JDR_CINT_MASK 0x1000
660 #define WM8400_JDR_CINT_SHIFT 12
661 #define WM8400_JDR_CINT_WIDTH 1
662 #define WM8400_CODEC_SEQ_END_EINT 0x0800
663 #define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800
664 #define WM8400_CODEC_SEQ_END_EINT_SHIFT 11
665 #define WM8400_CODEC_SEQ_END_EINT_WIDTH 1
666 #define WM8400_CDEL_TO_EINT 0x0400
667 #define WM8400_CDEL_TO_EINT_MASK 0x0400
668 #define WM8400_CDEL_TO_EINT_SHIFT 10
669 #define WM8400_CDEL_TO_EINT_WIDTH 1
670 #define WM8400_CHIP_GT150_EINT 0x0200
671 #define WM8400_CHIP_GT150_EINT_MASK 0x0200
672 #define WM8400_CHIP_GT150_EINT_SHIFT 9
673 #define WM8400_CHIP_GT150_EINT_WIDTH 1
674 #define WM8400_CHIP_GT115_EINT 0x0100
675 #define WM8400_CHIP_GT115_EINT_MASK 0x0100
676 #define WM8400_CHIP_GT115_EINT_SHIFT 8
677 #define WM8400_CHIP_GT115_EINT_WIDTH 1
678 #define WM8400_LINE_CMP_EINT 0x0080
679 #define WM8400_LINE_CMP_EINT_MASK 0x0080
680 #define WM8400_LINE_CMP_EINT_SHIFT 7
681 #define WM8400_LINE_CMP_EINT_WIDTH 1
682 #define WM8400_UVLO_EINT 0x0040
683 #define WM8400_UVLO_EINT_MASK 0x0040
684 #define WM8400_UVLO_EINT_SHIFT 6
685 #define WM8400_UVLO_EINT_WIDTH 1
686 #define WM8400_DC2_UV_EINT 0x0020
687 #define WM8400_DC2_UV_EINT_MASK 0x0020
688 #define WM8400_DC2_UV_EINT_SHIFT 5
689 #define WM8400_DC2_UV_EINT_WIDTH 1
690 #define WM8400_DC1_UV_EINT 0x0010
691 #define WM8400_DC1_UV_EINT_MASK 0x0010
692 #define WM8400_DC1_UV_EINT_SHIFT 4
693 #define WM8400_DC1_UV_EINT_WIDTH 1
694 #define WM8400_LDO4_UV_EINT 0x0008
695 #define WM8400_LDO4_UV_EINT_MASK 0x0008
696 #define WM8400_LDO4_UV_EINT_SHIFT 3
697 #define WM8400_LDO4_UV_EINT_WIDTH 1
698 #define WM8400_LDO3_UV_EINT 0x0004
699 #define WM8400_LDO3_UV_EINT_MASK 0x0004
700 #define WM8400_LDO3_UV_EINT_SHIFT 2
701 #define WM8400_LDO3_UV_EINT_WIDTH 1
702 #define WM8400_LDO2_UV_EINT 0x0002
703 #define WM8400_LDO2_UV_EINT_MASK 0x0002
704 #define WM8400_LDO2_UV_EINT_SHIFT 1
705 #define WM8400_LDO2_UV_EINT_WIDTH 1
706 #define WM8400_LDO1_UV_EINT 0x0001
707 #define WM8400_LDO1_UV_EINT_MASK 0x0001
708 #define WM8400_LDO1_UV_EINT_SHIFT 0
709 #define WM8400_LDO1_UV_EINT_WIDTH 1
710
711
712
713
714 #define WM8400_IM_MICD_CINT 0x8000
715 #define WM8400_IM_MICD_CINT_MASK 0x8000
716 #define WM8400_IM_MICD_CINT_SHIFT 15
717 #define WM8400_IM_MICD_CINT_WIDTH 1
718 #define WM8400_IM_MICSCD_CINT 0x4000
719 #define WM8400_IM_MICSCD_CINT_MASK 0x4000
720 #define WM8400_IM_MICSCD_CINT_SHIFT 14
721 #define WM8400_IM_MICSCD_CINT_WIDTH 1
722 #define WM8400_IM_JDL_CINT 0x2000
723 #define WM8400_IM_JDL_CINT_MASK 0x2000
724 #define WM8400_IM_JDL_CINT_SHIFT 13
725 #define WM8400_IM_JDL_CINT_WIDTH 1
726 #define WM8400_IM_JDR_CINT 0x1000
727 #define WM8400_IM_JDR_CINT_MASK 0x1000
728 #define WM8400_IM_JDR_CINT_SHIFT 12
729 #define WM8400_IM_JDR_CINT_WIDTH 1
730 #define WM8400_IM_CODEC_SEQ_END_EINT 0x0800
731 #define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800
732 #define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11
733 #define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1
734 #define WM8400_IM_CDEL_TO_EINT 0x0400
735 #define WM8400_IM_CDEL_TO_EINT_MASK 0x0400
736 #define WM8400_IM_CDEL_TO_EINT_SHIFT 10
737 #define WM8400_IM_CDEL_TO_EINT_WIDTH 1
738 #define WM8400_IM_CHIP_GT150_EINT 0x0200
739 #define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200
740 #define WM8400_IM_CHIP_GT150_EINT_SHIFT 9
741 #define WM8400_IM_CHIP_GT150_EINT_WIDTH 1
742 #define WM8400_IM_CHIP_GT115_EINT 0x0100
743 #define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100
744 #define WM8400_IM_CHIP_GT115_EINT_SHIFT 8
745 #define WM8400_IM_CHIP_GT115_EINT_WIDTH 1
746 #define WM8400_IM_LINE_CMP_EINT 0x0080
747 #define WM8400_IM_LINE_CMP_EINT_MASK 0x0080
748 #define WM8400_IM_LINE_CMP_EINT_SHIFT 7
749 #define WM8400_IM_LINE_CMP_EINT_WIDTH 1
750 #define WM8400_IM_UVLO_EINT 0x0040
751 #define WM8400_IM_UVLO_EINT_MASK 0x0040
752 #define WM8400_IM_UVLO_EINT_SHIFT 6
753 #define WM8400_IM_UVLO_EINT_WIDTH 1
754 #define WM8400_IM_DC2_UV_EINT 0x0020
755 #define WM8400_IM_DC2_UV_EINT_MASK 0x0020
756 #define WM8400_IM_DC2_UV_EINT_SHIFT 5
757 #define WM8400_IM_DC2_UV_EINT_WIDTH 1
758 #define WM8400_IM_DC1_UV_EINT 0x0010
759 #define WM8400_IM_DC1_UV_EINT_MASK 0x0010
760 #define WM8400_IM_DC1_UV_EINT_SHIFT 4
761 #define WM8400_IM_DC1_UV_EINT_WIDTH 1
762 #define WM8400_IM_LDO4_UV_EINT 0x0008
763 #define WM8400_IM_LDO4_UV_EINT_MASK 0x0008
764 #define WM8400_IM_LDO4_UV_EINT_SHIFT 3
765 #define WM8400_IM_LDO4_UV_EINT_WIDTH 1
766 #define WM8400_IM_LDO3_UV_EINT 0x0004
767 #define WM8400_IM_LDO3_UV_EINT_MASK 0x0004
768 #define WM8400_IM_LDO3_UV_EINT_SHIFT 2
769 #define WM8400_IM_LDO3_UV_EINT_WIDTH 1
770 #define WM8400_IM_LDO2_UV_EINT 0x0002
771 #define WM8400_IM_LDO2_UV_EINT_MASK 0x0002
772 #define WM8400_IM_LDO2_UV_EINT_SHIFT 1
773 #define WM8400_IM_LDO2_UV_EINT_WIDTH 1
774 #define WM8400_IM_LDO1_UV_EINT 0x0001
775 #define WM8400_IM_LDO1_UV_EINT_MASK 0x0001
776 #define WM8400_IM_LDO1_UV_EINT_SHIFT 0
777 #define WM8400_IM_LDO1_UV_EINT_WIDTH 1
778
779
780
781
782 #define WM8400_MICD_LVL 0x8000
783 #define WM8400_MICD_LVL_MASK 0x8000
784 #define WM8400_MICD_LVL_SHIFT 15
785 #define WM8400_MICD_LVL_WIDTH 1
786 #define WM8400_MICSCD_LVL 0x4000
787 #define WM8400_MICSCD_LVL_MASK 0x4000
788 #define WM8400_MICSCD_LVL_SHIFT 14
789 #define WM8400_MICSCD_LVL_WIDTH 1
790 #define WM8400_JDL_LVL 0x2000
791 #define WM8400_JDL_LVL_MASK 0x2000
792 #define WM8400_JDL_LVL_SHIFT 13
793 #define WM8400_JDL_LVL_WIDTH 1
794 #define WM8400_JDR_LVL 0x1000
795 #define WM8400_JDR_LVL_MASK 0x1000
796 #define WM8400_JDR_LVL_SHIFT 12
797 #define WM8400_JDR_LVL_WIDTH 1
798 #define WM8400_CODEC_SEQ_END_LVL 0x0800
799 #define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800
800 #define WM8400_CODEC_SEQ_END_LVL_SHIFT 11
801 #define WM8400_CODEC_SEQ_END_LVL_WIDTH 1
802 #define WM8400_CDEL_TO_LVL 0x0400
803 #define WM8400_CDEL_TO_LVL_MASK 0x0400
804 #define WM8400_CDEL_TO_LVL_SHIFT 10
805 #define WM8400_CDEL_TO_LVL_WIDTH 1
806 #define WM8400_CHIP_GT150_LVL 0x0200
807 #define WM8400_CHIP_GT150_LVL_MASK 0x0200
808 #define WM8400_CHIP_GT150_LVL_SHIFT 9
809 #define WM8400_CHIP_GT150_LVL_WIDTH 1
810 #define WM8400_CHIP_GT115_LVL 0x0100
811 #define WM8400_CHIP_GT115_LVL_MASK 0x0100
812 #define WM8400_CHIP_GT115_LVL_SHIFT 8
813 #define WM8400_CHIP_GT115_LVL_WIDTH 1
814 #define WM8400_LINE_CMP_LVL 0x0080
815 #define WM8400_LINE_CMP_LVL_MASK 0x0080
816 #define WM8400_LINE_CMP_LVL_SHIFT 7
817 #define WM8400_LINE_CMP_LVL_WIDTH 1
818 #define WM8400_UVLO_LVL 0x0040
819 #define WM8400_UVLO_LVL_MASK 0x0040
820 #define WM8400_UVLO_LVL_SHIFT 6
821 #define WM8400_UVLO_LVL_WIDTH 1
822 #define WM8400_DC2_UV_LVL 0x0020
823 #define WM8400_DC2_UV_LVL_MASK 0x0020
824 #define WM8400_DC2_UV_LVL_SHIFT 5
825 #define WM8400_DC2_UV_LVL_WIDTH 1
826 #define WM8400_DC1_UV_LVL 0x0010
827 #define WM8400_DC1_UV_LVL_MASK 0x0010
828 #define WM8400_DC1_UV_LVL_SHIFT 4
829 #define WM8400_DC1_UV_LVL_WIDTH 1
830 #define WM8400_LDO4_UV_LVL 0x0008
831 #define WM8400_LDO4_UV_LVL_MASK 0x0008
832 #define WM8400_LDO4_UV_LVL_SHIFT 3
833 #define WM8400_LDO4_UV_LVL_WIDTH 1
834 #define WM8400_LDO3_UV_LVL 0x0004
835 #define WM8400_LDO3_UV_LVL_MASK 0x0004
836 #define WM8400_LDO3_UV_LVL_SHIFT 2
837 #define WM8400_LDO3_UV_LVL_WIDTH 1
838 #define WM8400_LDO2_UV_LVL 0x0002
839 #define WM8400_LDO2_UV_LVL_MASK 0x0002
840 #define WM8400_LDO2_UV_LVL_SHIFT 1
841 #define WM8400_LDO2_UV_LVL_WIDTH 1
842 #define WM8400_LDO1_UV_LVL 0x0001
843 #define WM8400_LDO1_UV_LVL_MASK 0x0001
844 #define WM8400_LDO1_UV_LVL_SHIFT 0
845 #define WM8400_LDO1_UV_LVL_WIDTH 1
846
847
848
849
850 #define WM8400_SDR_CHIP_SOFTSD 0x2000
851 #define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000
852 #define WM8400_SDR_CHIP_SOFTSD_SHIFT 13
853 #define WM8400_SDR_CHIP_SOFTSD_WIDTH 1
854 #define WM8400_SDR_NPDN 0x0800
855 #define WM8400_SDR_NPDN_MASK 0x0800
856 #define WM8400_SDR_NPDN_SHIFT 11
857 #define WM8400_SDR_NPDN_WIDTH 1
858 #define WM8400_SDR_CHIP_GT150 0x0200
859 #define WM8400_SDR_CHIP_GT150_MASK 0x0200
860 #define WM8400_SDR_CHIP_GT150_SHIFT 9
861 #define WM8400_SDR_CHIP_GT150_WIDTH 1
862 #define WM8400_SDR_CHIP_GT115 0x0100
863 #define WM8400_SDR_CHIP_GT115_MASK 0x0100
864 #define WM8400_SDR_CHIP_GT115_SHIFT 8
865 #define WM8400_SDR_CHIP_GT115_WIDTH 1
866 #define WM8400_SDR_LINE_CMP 0x0080
867 #define WM8400_SDR_LINE_CMP_MASK 0x0080
868 #define WM8400_SDR_LINE_CMP_SHIFT 7
869 #define WM8400_SDR_LINE_CMP_WIDTH 1
870 #define WM8400_SDR_UVLO 0x0040
871 #define WM8400_SDR_UVLO_MASK 0x0040
872 #define WM8400_SDR_UVLO_SHIFT 6
873 #define WM8400_SDR_UVLO_WIDTH 1
874 #define WM8400_SDR_DC2_UV 0x0020
875 #define WM8400_SDR_DC2_UV_MASK 0x0020
876 #define WM8400_SDR_DC2_UV_SHIFT 5
877 #define WM8400_SDR_DC2_UV_WIDTH 1
878 #define WM8400_SDR_DC1_UV 0x0010
879 #define WM8400_SDR_DC1_UV_MASK 0x0010
880 #define WM8400_SDR_DC1_UV_SHIFT 4
881 #define WM8400_SDR_DC1_UV_WIDTH 1
882 #define WM8400_SDR_LDO4_UV 0x0008
883 #define WM8400_SDR_LDO4_UV_MASK 0x0008
884 #define WM8400_SDR_LDO4_UV_SHIFT 3
885 #define WM8400_SDR_LDO4_UV_WIDTH 1
886 #define WM8400_SDR_LDO3_UV 0x0004
887 #define WM8400_SDR_LDO3_UV_MASK 0x0004
888 #define WM8400_SDR_LDO3_UV_SHIFT 2
889 #define WM8400_SDR_LDO3_UV_WIDTH 1
890 #define WM8400_SDR_LDO2_UV 0x0002
891 #define WM8400_SDR_LDO2_UV_MASK 0x0002
892 #define WM8400_SDR_LDO2_UV_SHIFT 1
893 #define WM8400_SDR_LDO2_UV_WIDTH 1
894 #define WM8400_SDR_LDO1_UV 0x0001
895 #define WM8400_SDR_LDO1_UV_MASK 0x0001
896 #define WM8400_SDR_LDO1_UV_SHIFT 0
897 #define WM8400_SDR_LDO1_UV_WIDTH 1
898
899
900
901
902 #define WM8400_BG_LINE_COMP 0x8000
903 #define WM8400_BG_LINE_COMP_MASK 0x8000
904 #define WM8400_BG_LINE_COMP_SHIFT 15
905 #define WM8400_BG_LINE_COMP_WIDTH 1
906 #define WM8400_LINE_CMP_VTHI_MASK 0x00F0
907 #define WM8400_LINE_CMP_VTHI_SHIFT 4
908 #define WM8400_LINE_CMP_VTHI_WIDTH 4
909 #define WM8400_LINE_CMP_VTHD_MASK 0x000F
910 #define WM8400_LINE_CMP_VTHD_SHIFT 0
911 #define WM8400_LINE_CMP_VTHD_WIDTH 4
912
913 #endif