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13 #ifndef __CROS_EC_COMMANDS_H
14 #define __CROS_EC_COMMANDS_H
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18
19 #define BUILD_ASSERT(_cond)
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27
28 #define EC_PROTO_VERSION 0x00000002
29
30
31 #define EC_VER_MASK(version) BIT(version)
32
33
34 #define EC_LPC_ADDR_ACPI_DATA 0x62
35 #define EC_LPC_ADDR_ACPI_CMD 0x66
36
37
38 #define EC_LPC_ADDR_HOST_DATA 0x200
39 #define EC_LPC_ADDR_HOST_CMD 0x204
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41
42
43 #define EC_LPC_ADDR_HOST_ARGS 0x800
44 #define EC_LPC_ADDR_HOST_PARAM 0x804
45
46
47
48 #define EC_LPC_ADDR_HOST_PACKET 0x800
49 #define EC_LPC_HOST_PACKET_SIZE 0x100
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53
54
55 #define EC_HOST_CMD_REGION0 0x800
56 #define EC_HOST_CMD_REGION1 0x880
57 #define EC_HOST_CMD_REGION_SIZE 0x80
58
59
60 #define EC_LPC_CMDR_DATA BIT(0)
61 #define EC_LPC_CMDR_PENDING BIT(1)
62 #define EC_LPC_CMDR_BUSY BIT(2)
63 #define EC_LPC_CMDR_CMD BIT(3)
64 #define EC_LPC_CMDR_ACPI_BRST BIT(4)
65 #define EC_LPC_CMDR_SCI BIT(5)
66 #define EC_LPC_CMDR_SMI BIT(6)
67
68 #define EC_LPC_ADDR_MEMMAP 0x900
69 #define EC_MEMMAP_SIZE 255
70 #define EC_MEMMAP_TEXT_MAX 8
71
72
73 #define EC_MEMMAP_TEMP_SENSOR 0x00
74 #define EC_MEMMAP_FAN 0x10
75 #define EC_MEMMAP_TEMP_SENSOR_B 0x18
76 #define EC_MEMMAP_ID 0x20
77 #define EC_MEMMAP_ID_VERSION 0x22
78 #define EC_MEMMAP_THERMAL_VERSION 0x23
79 #define EC_MEMMAP_BATTERY_VERSION 0x24
80 #define EC_MEMMAP_SWITCHES_VERSION 0x25
81 #define EC_MEMMAP_EVENTS_VERSION 0x26
82 #define EC_MEMMAP_HOST_CMD_FLAGS 0x27
83
84 #define EC_MEMMAP_SWITCHES 0x30
85
86 #define EC_MEMMAP_HOST_EVENTS 0x34
87
88 #define EC_MEMMAP_BATT_VOLT 0x40
89 #define EC_MEMMAP_BATT_RATE 0x44
90 #define EC_MEMMAP_BATT_CAP 0x48
91 #define EC_MEMMAP_BATT_FLAG 0x4c
92 #define EC_MEMMAP_BATT_COUNT 0x4d
93 #define EC_MEMMAP_BATT_INDEX 0x4e
94
95 #define EC_MEMMAP_BATT_DCAP 0x50
96 #define EC_MEMMAP_BATT_DVLT 0x54
97 #define EC_MEMMAP_BATT_LFCC 0x58
98 #define EC_MEMMAP_BATT_CCNT 0x5c
99
100 #define EC_MEMMAP_BATT_MFGR 0x60
101 #define EC_MEMMAP_BATT_MODEL 0x68
102 #define EC_MEMMAP_BATT_SERIAL 0x70
103 #define EC_MEMMAP_BATT_TYPE 0x78
104 #define EC_MEMMAP_ALS 0x80
105
106 #define EC_MEMMAP_ACC_STATUS 0x90
107
108 #define EC_MEMMAP_ACC_DATA 0x92
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110
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112 #define EC_MEMMAP_GYRO_DATA 0xa0
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120 #define EC_MEMMAP_NO_ACPI 0xe0
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123 #define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
124 #define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
125 #define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
126
127
128 #define EC_TEMP_SENSOR_ENTRIES 16
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134 #define EC_TEMP_SENSOR_B_ENTRIES 8
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137 #define EC_TEMP_SENSOR_NOT_PRESENT 0xff
138 #define EC_TEMP_SENSOR_ERROR 0xfe
139 #define EC_TEMP_SENSOR_NOT_POWERED 0xfd
140 #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
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145 #define EC_TEMP_SENSOR_OFFSET 200
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150 #define EC_ALS_ENTRIES 2
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157 #define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
158
159 #define EC_FAN_SPEED_ENTRIES 4
160 #define EC_FAN_SPEED_NOT_PRESENT 0xffff
161 #define EC_FAN_SPEED_STALLED 0xfffe
162
163
164 #define EC_BATT_FLAG_AC_PRESENT 0x01
165 #define EC_BATT_FLAG_BATT_PRESENT 0x02
166 #define EC_BATT_FLAG_DISCHARGING 0x04
167 #define EC_BATT_FLAG_CHARGING 0x08
168 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
169
170 #define EC_BATT_FLAG_INVALID_DATA 0x20
171
172
173 #define EC_SWITCH_LID_OPEN 0x01
174 #define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
175 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
176
177 #define EC_SWITCH_IGNORE1 0x08
178
179 #define EC_SWITCH_DEDICATED_RECOVERY 0x10
180
181 #define EC_SWITCH_IGNORE0 0x20
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185 #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
186
187 #define EC_HOST_CMD_FLAG_VERSION_3 0x02
188
189
190 #define EC_WIRELESS_SWITCH_ALL ~0x00
191 #define EC_WIRELESS_SWITCH_WLAN 0x01
192 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
193 #define EC_WIRELESS_SWITCH_WWAN 0x04
194 #define EC_WIRELESS_SWITCH_WLAN_POWER 0x08
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216 #define EC_CMD_ACPI_READ 0x0080
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231 #define EC_CMD_ACPI_WRITE 0x0081
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240 #define EC_CMD_ACPI_BURST_ENABLE 0x0082
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248 #define EC_CMD_ACPI_BURST_DISABLE 0x0083
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257 #define EC_CMD_ACPI_QUERY_EVENT 0x0084
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262 #define EC_ACPI_MEM_VERSION 0x00
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267 #define EC_ACPI_MEM_TEST 0x01
268
269 #define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
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272 #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
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274 #define EC_ACPI_MEM_FAN_DUTY 0x04
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291 #define EC_ACPI_MEM_TEMP_ID 0x05
292 #define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
293 #define EC_ACPI_MEM_TEMP_COMMIT 0x07
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300 #define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0)
301 #define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1)
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318 #define EC_ACPI_MEM_CHARGING_LIMIT 0x08
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321 #define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
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323 #define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
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335 #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
336 #define EC_ACPI_MEM_TBMD_SHIFT 0
337 #define EC_ACPI_MEM_TBMD_MASK 0x1
338 #define EC_ACPI_MEM_DDPN_SHIFT 1
339 #define EC_ACPI_MEM_DDPN_MASK 0x7
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353 #define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a
354 #define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b
355 #define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c
356 #define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d
357 #define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e
358 #define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f
359 #define EC_ACPI_MEM_DEVICE_FEATURES6 0x10
360 #define EC_ACPI_MEM_DEVICE_FEATURES7 0x11
361
362 #define EC_ACPI_MEM_BATTERY_INDEX 0x12
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371 #define EC_ACPI_MEM_USB_PORT_POWER 0x13
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377 #define EC_ACPI_MEM_MAPPED_BEGIN 0x20
378 #define EC_ACPI_MEM_MAPPED_SIZE 0xe0
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381 #define EC_ACPI_MEM_VERSION_CURRENT 2
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423 #define __ec_align1 __packed
424 #define __ec_align2 __packed
425 #define __ec_align4 __packed
426 #define __ec_align_size1 __packed
427 #define __ec_align_offset1 __packed
428 #define __ec_align_offset2 __packed
429 #define __ec_todo_packed __packed
430 #define __ec_todo_unpacked
431
432
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434
435 #define EC_LPC_STATUS_TO_HOST 0x01
436
437 #define EC_LPC_STATUS_FROM_HOST 0x02
438
439 #define EC_LPC_STATUS_PROCESSING 0x04
440
441 #define EC_LPC_STATUS_LAST_CMD 0x08
442
443 #define EC_LPC_STATUS_BURST_MODE 0x10
444
445 #define EC_LPC_STATUS_SCI_PENDING 0x20
446
447 #define EC_LPC_STATUS_SMI_PENDING 0x40
448
449 #define EC_LPC_STATUS_RESERVED 0x80
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455 #define EC_LPC_STATUS_BUSY_MASK \
456 (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
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461
462 enum ec_status {
463 EC_RES_SUCCESS = 0,
464 EC_RES_INVALID_COMMAND = 1,
465 EC_RES_ERROR = 2,
466 EC_RES_INVALID_PARAM = 3,
467 EC_RES_ACCESS_DENIED = 4,
468 EC_RES_INVALID_RESPONSE = 5,
469 EC_RES_INVALID_VERSION = 6,
470 EC_RES_INVALID_CHECKSUM = 7,
471 EC_RES_IN_PROGRESS = 8,
472 EC_RES_UNAVAILABLE = 9,
473 EC_RES_TIMEOUT = 10,
474 EC_RES_OVERFLOW = 11,
475 EC_RES_INVALID_HEADER = 12,
476 EC_RES_REQUEST_TRUNCATED = 13,
477 EC_RES_RESPONSE_TOO_BIG = 14,
478 EC_RES_BUS_ERROR = 15,
479 EC_RES_BUSY = 16,
480 EC_RES_INVALID_HEADER_VERSION = 17,
481 EC_RES_INVALID_HEADER_CRC = 18,
482 EC_RES_INVALID_DATA_CRC = 19,
483 EC_RES_DUP_UNAVAILABLE = 20,
484 };
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493 enum host_event_code {
494 EC_HOST_EVENT_LID_CLOSED = 1,
495 EC_HOST_EVENT_LID_OPEN = 2,
496 EC_HOST_EVENT_POWER_BUTTON = 3,
497 EC_HOST_EVENT_AC_CONNECTED = 4,
498 EC_HOST_EVENT_AC_DISCONNECTED = 5,
499 EC_HOST_EVENT_BATTERY_LOW = 6,
500 EC_HOST_EVENT_BATTERY_CRITICAL = 7,
501 EC_HOST_EVENT_BATTERY = 8,
502 EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
503
504 EC_HOST_EVENT_DEVICE = 10,
505 EC_HOST_EVENT_THERMAL = 11,
506 EC_HOST_EVENT_USB_CHARGER = 12,
507 EC_HOST_EVENT_KEY_PRESSED = 13,
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513 EC_HOST_EVENT_INTERFACE_READY = 14,
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515 EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
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518 EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
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520 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
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523 EC_HOST_EVENT_THROTTLE_START = 18,
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525 EC_HOST_EVENT_THROTTLE_STOP = 19,
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528 EC_HOST_EVENT_HANG_DETECT = 20,
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530 EC_HOST_EVENT_HANG_REBOOT = 21,
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533 EC_HOST_EVENT_PD_MCU = 22,
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536 EC_HOST_EVENT_BATTERY_STATUS = 23,
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539 EC_HOST_EVENT_PANIC = 24,
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542 EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25,
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545 EC_HOST_EVENT_RTC = 26,
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548 EC_HOST_EVENT_MKBP = 27,
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551 EC_HOST_EVENT_USB_MUX = 28,
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554 EC_HOST_EVENT_MODE_CHANGE = 29,
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557 EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30,
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566 EC_HOST_EVENT_INVALID = 32
567 };
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569 #define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
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579 struct ec_lpc_host_args {
580 uint8_t flags;
581 uint8_t command_version;
582 uint8_t data_size;
583 uint8_t checksum;
584 } __ec_align4;
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596 #define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
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604 #define EC_HOST_ARGS_FLAG_TO_HOST 0x02
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646 #define EC_SPI_FRAME_START 0xec
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651 #define EC_SPI_PAST_END 0xed
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658 #define EC_SPI_RX_READY 0xf8
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664 #define EC_SPI_RECEIVING 0xf9
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667 #define EC_SPI_PROCESSING 0xfa
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673 #define EC_SPI_RX_BAD_DATA 0xfb
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680 #define EC_SPI_NOT_READY 0xfc
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687 #define EC_SPI_OLD_READY 0xfd
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707 #define EC_PROTO2_REQUEST_HEADER_BYTES 3
708 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1
709 #define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
710 EC_PROTO2_REQUEST_TRAILER_BYTES)
711
712 #define EC_PROTO2_RESPONSE_HEADER_BYTES 2
713 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
714 #define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
715 EC_PROTO2_RESPONSE_TRAILER_BYTES)
716
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718 #define EC_PROTO2_MAX_PARAM_SIZE 0xfc
719
720
721 #define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
722 EC_PROTO2_MAX_PARAM_SIZE)
723 #define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
724 EC_PROTO2_MAX_PARAM_SIZE)
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732 #define EC_COMMAND_PROTOCOL_3 0xda
733
734 #define EC_HOST_REQUEST_VERSION 3
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748 struct ec_host_request {
749 uint8_t struct_version;
750 uint8_t checksum;
751 uint16_t command;
752 uint8_t command_version;
753 uint8_t reserved;
754 uint16_t data_len;
755 } __ec_align4;
756
757 #define EC_HOST_RESPONSE_VERSION 3
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768 struct ec_host_response {
769 uint8_t struct_version;
770 uint8_t checksum;
771 uint16_t result;
772 uint16_t data_len;
773 uint16_t reserved;
774 } __ec_align4;
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837 struct ec_host_request4 {
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844 uint8_t fields0;
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851 uint8_t fields1;
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854 uint16_t command;
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857 uint16_t data_len;
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860 uint8_t reserved;
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863 uint8_t header_crc;
864 } __ec_align4;
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867 struct ec_host_response4 {
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874 uint8_t fields0;
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880 uint8_t fields1;
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883 uint16_t result;
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886 uint16_t data_len;
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889 uint8_t reserved;
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892 uint8_t header_crc;
893 } __ec_align4;
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896 #define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
897 #define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
898 #define EC_PACKET4_0_SEQ_NUM_SHIFT 5
899 #define EC_PACKET4_0_SEQ_NUM_MASK 0x60
900 #define EC_PACKET4_0_SEQ_DUP_MASK 0x80
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903 #define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f
904 #define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
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928 #define EC_CMD_PROTO_VERSION 0x0000
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934 struct ec_response_proto_version {
935 uint32_t version;
936 } __ec_align4;
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942 #define EC_CMD_HELLO 0x0001
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948 struct ec_params_hello {
949 uint32_t in_data;
950 } __ec_align4;
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956 struct ec_response_hello {
957 uint32_t out_data;
958 } __ec_align4;
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961 #define EC_CMD_GET_VERSION 0x0002
962
963 enum ec_current_image {
964 EC_IMAGE_UNKNOWN = 0,
965 EC_IMAGE_RO,
966 EC_IMAGE_RW
967 };
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976 struct ec_response_get_version {
977 char version_string_ro[32];
978 char version_string_rw[32];
979 char reserved[32];
980 uint32_t current_image;
981 } __ec_align4;
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984 #define EC_CMD_READ_TEST 0x0003
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991 struct ec_params_read_test {
992 uint32_t offset;
993 uint32_t size;
994 } __ec_align4;
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1000 struct ec_response_read_test {
1001 uint32_t data[32];
1002 } __ec_align4;
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1009 #define EC_CMD_GET_BUILD_INFO 0x0004
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1012 #define EC_CMD_GET_CHIP_INFO 0x0005
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1020 struct ec_response_get_chip_info {
1021 char vendor[32];
1022 char name[32];
1023 char revision[32];
1024 } __ec_align4;
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1027 #define EC_CMD_GET_BOARD_VERSION 0x0006
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1033 struct ec_response_board_version {
1034 uint16_t board_version;
1035 } __ec_align2;
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1045 #define EC_CMD_READ_MEMMAP 0x0007
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1052 struct ec_params_read_memmap {
1053 uint8_t offset;
1054 uint8_t size;
1055 } __ec_align1;
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1058 #define EC_CMD_GET_CMD_VERSIONS 0x0008
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1064 struct ec_params_get_cmd_versions {
1065 uint8_t cmd;
1066 } __ec_align1;
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1073 struct ec_params_get_cmd_versions_v1 {
1074 uint16_t cmd;
1075 } __ec_align2;
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1082 struct ec_response_get_cmd_versions {
1083 uint32_t version_mask;
1084 } __ec_align4;
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1093 #define EC_CMD_GET_COMMS_STATUS 0x0009
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1096 enum ec_comms_status {
1097 EC_COMMS_STATUS_PROCESSING = BIT(0),
1098 };
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1105 struct ec_response_get_comms_status {
1106 uint32_t flags;
1107 } __ec_align4;
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1110 #define EC_CMD_TEST_PROTOCOL 0x000A
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1113 struct ec_params_test_protocol {
1114 uint32_t ec_result;
1115 uint32_t ret_len;
1116 uint8_t buf[32];
1117 } __ec_align4;
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1120 struct ec_response_test_protocol {
1121 uint8_t buf[32];
1122 } __ec_align4;
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1125 #define EC_CMD_GET_PROTOCOL_INFO 0x000B
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1129 #define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0)
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1139 struct ec_response_get_protocol_info {
1140
1141 uint32_t protocol_versions;
1142 uint16_t max_request_packet_size;
1143 uint16_t max_response_packet_size;
1144 uint32_t flags;
1145 } __ec_align4;
1146
1147
1148
1149
1150
1151
1152 #define EC_GSV_SET 0x80000000
1153
1154
1155
1156
1157
1158 #define EC_GSV_PARAM_MASK 0x00ffffff
1159
1160 struct ec_params_get_set_value {
1161 uint32_t flags;
1162 uint32_t value;
1163 } __ec_align4;
1164
1165 struct ec_response_get_set_value {
1166 uint32_t flags;
1167 uint32_t value;
1168 } __ec_align4;
1169
1170
1171 #define EC_CMD_GSV_PAUSE_IN_S5 0x000C
1172
1173
1174
1175 #define EC_CMD_GET_FEATURES 0x000D
1176
1177
1178 enum ec_feature_code {
1179
1180
1181
1182
1183 EC_FEATURE_LIMITED = 0,
1184
1185
1186
1187
1188 EC_FEATURE_FLASH = 1,
1189
1190
1191
1192 EC_FEATURE_PWM_FAN = 2,
1193
1194
1195
1196 EC_FEATURE_PWM_KEYB = 3,
1197
1198
1199
1200 EC_FEATURE_LIGHTBAR = 4,
1201
1202 EC_FEATURE_LED = 5,
1203
1204
1205
1206
1207 EC_FEATURE_MOTION_SENSE = 6,
1208
1209 EC_FEATURE_KEYB = 7,
1210
1211 EC_FEATURE_PSTORE = 8,
1212
1213 EC_FEATURE_PORT80 = 9,
1214
1215
1216
1217
1218 EC_FEATURE_THERMAL = 10,
1219
1220 EC_FEATURE_BKLIGHT_SWITCH = 11,
1221
1222 EC_FEATURE_WIFI_SWITCH = 12,
1223
1224 EC_FEATURE_HOST_EVENTS = 13,
1225
1226 EC_FEATURE_GPIO = 14,
1227
1228 EC_FEATURE_I2C = 15,
1229
1230 EC_FEATURE_CHARGER = 16,
1231
1232 EC_FEATURE_BATTERY = 17,
1233
1234
1235
1236
1237 EC_FEATURE_SMART_BATTERY = 18,
1238
1239 EC_FEATURE_HANG_DETECT = 19,
1240
1241 EC_FEATURE_PMU = 20,
1242
1243 EC_FEATURE_SUB_MCU = 21,
1244
1245 EC_FEATURE_USB_PD = 22,
1246
1247 EC_FEATURE_USB_MUX = 23,
1248
1249 EC_FEATURE_MOTION_SENSE_FIFO = 24,
1250
1251 EC_FEATURE_VSTORE = 25,
1252
1253 EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26,
1254
1255 EC_FEATURE_RTC = 27,
1256
1257 EC_FEATURE_FINGERPRINT = 28,
1258
1259 EC_FEATURE_TOUCHPAD = 29,
1260
1261 EC_FEATURE_RWSIG = 30,
1262
1263 EC_FEATURE_DEVICE_EVENT = 31,
1264
1265 EC_FEATURE_UNIFIED_WAKE_MASKS = 32,
1266
1267 EC_FEATURE_HOST_EVENT64 = 33,
1268
1269 EC_FEATURE_EXEC_IN_RAM = 34,
1270
1271 EC_FEATURE_CEC = 35,
1272
1273 EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36,
1274
1275
1276
1277
1278
1279 EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37,
1280
1281 EC_FEATURE_AUDIO_CODEC = 38,
1282
1283 EC_FEATURE_SCP = 39,
1284
1285 EC_FEATURE_ISH = 40,
1286 };
1287
1288 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
1289 #define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32)
1290
1291 struct ec_response_get_features {
1292 uint32_t flags[2];
1293 } __ec_align4;
1294
1295
1296
1297 #define EC_CMD_GET_SKU_ID 0x000E
1298
1299
1300 #define EC_CMD_SET_SKU_ID 0x000F
1301
1302 struct ec_sku_id_info {
1303 uint32_t sku_id;
1304 } __ec_align4;
1305
1306
1307
1308
1309
1310 #define EC_CMD_FLASH_INFO 0x0010
1311 #define EC_VER_FLASH_INFO 2
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325 struct ec_response_flash_info {
1326 uint32_t flash_size;
1327 uint32_t write_block_size;
1328 uint32_t erase_block_size;
1329 uint32_t protect_block_size;
1330 } __ec_align4;
1331
1332
1333
1334
1335
1336 #define EC_FLASH_INFO_ERASE_TO_0 BIT(0)
1337
1338
1339
1340
1341
1342
1343
1344
1345 #define EC_FLASH_INFO_SELECT_REQUIRED BIT(1)
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376 struct ec_response_flash_info_1 {
1377
1378 uint32_t flash_size;
1379 uint32_t write_block_size;
1380 uint32_t erase_block_size;
1381 uint32_t protect_block_size;
1382
1383
1384 uint32_t write_ideal_size;
1385 uint32_t flags;
1386 } __ec_align4;
1387
1388 struct ec_params_flash_info_2 {
1389
1390 uint16_t num_banks_desc;
1391
1392 uint8_t reserved[2];
1393 } __ec_align4;
1394
1395 struct ec_flash_bank {
1396
1397 uint16_t count;
1398
1399 uint8_t size_exp;
1400
1401 uint8_t write_size_exp;
1402
1403 uint8_t erase_size_exp;
1404
1405 uint8_t protect_size_exp;
1406
1407 uint8_t reserved[2];
1408 };
1409
1410 struct ec_response_flash_info_2 {
1411
1412 uint32_t flash_size;
1413
1414 uint32_t flags;
1415
1416 uint32_t write_ideal_size;
1417
1418 uint16_t num_banks_total;
1419
1420 uint16_t num_banks_desc;
1421 struct ec_flash_bank banks[0];
1422 } __ec_align4;
1423
1424
1425
1426
1427
1428
1429 #define EC_CMD_FLASH_READ 0x0011
1430
1431
1432
1433
1434
1435
1436 struct ec_params_flash_read {
1437 uint32_t offset;
1438 uint32_t size;
1439 } __ec_align4;
1440
1441
1442 #define EC_CMD_FLASH_WRITE 0x0012
1443 #define EC_VER_FLASH_WRITE 1
1444
1445
1446 #define EC_FLASH_WRITE_VER0_SIZE 64
1447
1448
1449
1450
1451
1452
1453 struct ec_params_flash_write {
1454 uint32_t offset;
1455 uint32_t size;
1456
1457 } __ec_align4;
1458
1459
1460 #define EC_CMD_FLASH_ERASE 0x0013
1461
1462
1463
1464
1465
1466
1467 struct ec_params_flash_erase {
1468 uint32_t offset;
1469 uint32_t size;
1470 } __ec_align4;
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489 enum ec_flash_erase_cmd {
1490 FLASH_ERASE_SECTOR,
1491 FLASH_ERASE_SECTOR_ASYNC,
1492 FLASH_ERASE_GET_RESULT,
1493 };
1494
1495
1496
1497
1498
1499
1500
1501
1502 struct ec_params_flash_erase_v1 {
1503 uint8_t cmd;
1504 uint8_t reserved;
1505 uint16_t flag;
1506 struct ec_params_flash_erase params;
1507 } __ec_align4;
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519 #define EC_CMD_FLASH_PROTECT 0x0015
1520 #define EC_VER_FLASH_PROTECT 1
1521
1522
1523
1524 #define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
1525
1526
1527
1528
1529 #define EC_FLASH_PROTECT_RO_NOW BIT(1)
1530
1531 #define EC_FLASH_PROTECT_ALL_NOW BIT(2)
1532
1533 #define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
1534
1535 #define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
1536
1537
1538
1539
1540
1541 #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5)
1542
1543 #define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
1544
1545 #define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
1546
1547 #define EC_FLASH_PROTECT_RW_NOW BIT(8)
1548
1549 #define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
1550
1551 #define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
1552
1553
1554
1555
1556
1557
1558
1559 struct ec_params_flash_protect {
1560 uint32_t mask;
1561 uint32_t flags;
1562 } __ec_align4;
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573 struct ec_response_flash_protect {
1574 uint32_t flags;
1575 uint32_t valid_flags;
1576 uint32_t writable_flags;
1577 } __ec_align4;
1578
1579
1580
1581
1582
1583
1584
1585 #define EC_CMD_FLASH_REGION_INFO 0x0016
1586 #define EC_VER_FLASH_REGION_INFO 1
1587
1588 enum ec_flash_region {
1589
1590 EC_FLASH_REGION_RO = 0,
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600 EC_FLASH_REGION_ACTIVE,
1601
1602
1603
1604
1605 EC_FLASH_REGION_WP_RO,
1606
1607 EC_FLASH_REGION_UPDATE,
1608
1609 EC_FLASH_REGION_COUNT,
1610 };
1611
1612
1613
1614
1615 #define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE
1616
1617
1618
1619
1620
1621
1622 struct ec_params_flash_region_info {
1623 uint32_t region;
1624 } __ec_align4;
1625
1626 struct ec_response_flash_region_info {
1627 uint32_t offset;
1628 uint32_t size;
1629 } __ec_align4;
1630
1631
1632 #define EC_CMD_VBNV_CONTEXT 0x0017
1633 #define EC_VER_VBNV_CONTEXT 1
1634 #define EC_VBNV_BLOCK_SIZE 16
1635
1636 enum ec_vbnvcontext_op {
1637 EC_VBNV_CONTEXT_OP_READ,
1638 EC_VBNV_CONTEXT_OP_WRITE,
1639 };
1640
1641 struct ec_params_vbnvcontext {
1642 uint32_t op;
1643 uint8_t block[EC_VBNV_BLOCK_SIZE];
1644 } __ec_align4;
1645
1646 struct ec_response_vbnvcontext {
1647 uint8_t block[EC_VBNV_BLOCK_SIZE];
1648 } __ec_align4;
1649
1650
1651
1652 #define EC_CMD_FLASH_SPI_INFO 0x0018
1653
1654 struct ec_response_flash_spi_info {
1655
1656 uint8_t jedec[3];
1657
1658
1659 uint8_t reserved0;
1660
1661
1662 uint8_t mfr_dev_id[2];
1663
1664
1665 uint8_t sr1, sr2;
1666 } __ec_align1;
1667
1668
1669
1670 #define EC_CMD_FLASH_SELECT 0x0019
1671
1672
1673
1674
1675
1676 struct ec_params_flash_select {
1677 uint8_t select;
1678 } __ec_align4;
1679
1680
1681
1682
1683
1684
1685 #define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020
1686
1687 struct ec_response_pwm_get_fan_rpm {
1688 uint32_t rpm;
1689 } __ec_align4;
1690
1691
1692 #define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021
1693
1694
1695 struct ec_params_pwm_set_fan_target_rpm_v0 {
1696 uint32_t rpm;
1697 } __ec_align4;
1698
1699
1700 struct ec_params_pwm_set_fan_target_rpm_v1 {
1701 uint32_t rpm;
1702 uint8_t fan_idx;
1703 } __ec_align_size1;
1704
1705
1706
1707 #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022
1708
1709 struct ec_response_pwm_get_keyboard_backlight {
1710 uint8_t percent;
1711 uint8_t enabled;
1712 } __ec_align1;
1713
1714
1715
1716 #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023
1717
1718 struct ec_params_pwm_set_keyboard_backlight {
1719 uint8_t percent;
1720 } __ec_align1;
1721
1722
1723 #define EC_CMD_PWM_SET_FAN_DUTY 0x0024
1724
1725
1726 struct ec_params_pwm_set_fan_duty_v0 {
1727 uint32_t percent;
1728 } __ec_align4;
1729
1730
1731 struct ec_params_pwm_set_fan_duty_v1 {
1732 uint32_t percent;
1733 uint8_t fan_idx;
1734 } __ec_align_size1;
1735
1736 #define EC_CMD_PWM_SET_DUTY 0x0025
1737
1738 #define EC_PWM_MAX_DUTY 0xffff
1739
1740 enum ec_pwm_type {
1741
1742 EC_PWM_TYPE_GENERIC = 0,
1743
1744 EC_PWM_TYPE_KB_LIGHT,
1745
1746 EC_PWM_TYPE_DISPLAY_LIGHT,
1747 EC_PWM_TYPE_COUNT,
1748 };
1749
1750 struct ec_params_pwm_set_duty {
1751 uint16_t duty;
1752 uint8_t pwm_type;
1753 uint8_t index;
1754 } __ec_align4;
1755
1756 #define EC_CMD_PWM_GET_DUTY 0x0026
1757
1758 struct ec_params_pwm_get_duty {
1759 uint8_t pwm_type;
1760 uint8_t index;
1761 } __ec_align1;
1762
1763 struct ec_response_pwm_get_duty {
1764 uint16_t duty;
1765 } __ec_align2;
1766
1767
1768
1769
1770
1771
1772
1773
1774 #define EC_CMD_LIGHTBAR_CMD 0x0028
1775
1776 struct rgb_s {
1777 uint8_t r, g, b;
1778 } __ec_todo_unpacked;
1779
1780 #define LB_BATTERY_LEVELS 4
1781
1782
1783
1784
1785
1786 struct lightbar_params_v0 {
1787
1788 int32_t google_ramp_up;
1789 int32_t google_ramp_down;
1790 int32_t s3s0_ramp_up;
1791 int32_t s0_tick_delay[2];
1792 int32_t s0a_tick_delay[2];
1793 int32_t s0s3_ramp_down;
1794 int32_t s3_sleep_for;
1795 int32_t s3_ramp_up;
1796 int32_t s3_ramp_down;
1797
1798
1799 uint8_t new_s0;
1800 uint8_t osc_min[2];
1801 uint8_t osc_max[2];
1802 uint8_t w_ofs[2];
1803
1804
1805 uint8_t bright_bl_off_fixed[2];
1806 uint8_t bright_bl_on_min[2];
1807 uint8_t bright_bl_on_max[2];
1808
1809
1810 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1811
1812
1813 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1814 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1815
1816
1817 struct rgb_s color[8];
1818 } __ec_todo_packed;
1819
1820 struct lightbar_params_v1 {
1821
1822 int32_t google_ramp_up;
1823 int32_t google_ramp_down;
1824 int32_t s3s0_ramp_up;
1825 int32_t s0_tick_delay[2];
1826 int32_t s0a_tick_delay[2];
1827 int32_t s0s3_ramp_down;
1828 int32_t s3_sleep_for;
1829 int32_t s3_ramp_up;
1830 int32_t s3_ramp_down;
1831 int32_t s5_ramp_up;
1832 int32_t s5_ramp_down;
1833 int32_t tap_tick_delay;
1834 int32_t tap_gate_delay;
1835 int32_t tap_display_time;
1836
1837
1838 uint8_t tap_pct_red;
1839 uint8_t tap_pct_green;
1840 uint8_t tap_seg_min_on;
1841 uint8_t tap_seg_max_on;
1842 uint8_t tap_seg_osc;
1843 uint8_t tap_idx[3];
1844
1845
1846 uint8_t osc_min[2];
1847 uint8_t osc_max[2];
1848 uint8_t w_ofs[2];
1849
1850
1851 uint8_t bright_bl_off_fixed[2];
1852 uint8_t bright_bl_on_min[2];
1853 uint8_t bright_bl_on_max[2];
1854
1855
1856 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1857
1858
1859 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1860 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1861
1862
1863 uint8_t s5_idx;
1864
1865
1866 struct rgb_s color[8];
1867 } __ec_todo_packed;
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878 struct lightbar_params_v2_timing {
1879
1880 int32_t google_ramp_up;
1881 int32_t google_ramp_down;
1882 int32_t s3s0_ramp_up;
1883 int32_t s0_tick_delay[2];
1884 int32_t s0a_tick_delay[2];
1885 int32_t s0s3_ramp_down;
1886 int32_t s3_sleep_for;
1887 int32_t s3_ramp_up;
1888 int32_t s3_ramp_down;
1889 int32_t s5_ramp_up;
1890 int32_t s5_ramp_down;
1891 int32_t tap_tick_delay;
1892 int32_t tap_gate_delay;
1893 int32_t tap_display_time;
1894 } __ec_todo_packed;
1895
1896 struct lightbar_params_v2_tap {
1897
1898 uint8_t tap_pct_red;
1899 uint8_t tap_pct_green;
1900 uint8_t tap_seg_min_on;
1901 uint8_t tap_seg_max_on;
1902 uint8_t tap_seg_osc;
1903 uint8_t tap_idx[3];
1904 } __ec_todo_packed;
1905
1906 struct lightbar_params_v2_oscillation {
1907
1908 uint8_t osc_min[2];
1909 uint8_t osc_max[2];
1910 uint8_t w_ofs[2];
1911 } __ec_todo_packed;
1912
1913 struct lightbar_params_v2_brightness {
1914
1915 uint8_t bright_bl_off_fixed[2];
1916 uint8_t bright_bl_on_min[2];
1917 uint8_t bright_bl_on_max[2];
1918 } __ec_todo_packed;
1919
1920 struct lightbar_params_v2_thresholds {
1921
1922 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1923 } __ec_todo_packed;
1924
1925 struct lightbar_params_v2_colors {
1926
1927 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1928 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1929
1930
1931 uint8_t s5_idx;
1932
1933
1934 struct rgb_s color[8];
1935 } __ec_todo_packed;
1936
1937
1938 #define EC_LB_PROG_LEN 192
1939 struct lightbar_program {
1940 uint8_t size;
1941 uint8_t data[EC_LB_PROG_LEN];
1942 } __ec_todo_unpacked;
1943
1944 struct ec_params_lightbar {
1945 uint8_t cmd;
1946 union {
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959 struct __ec_todo_unpacked {
1960 uint8_t num;
1961 } set_brightness, seq, demo;
1962
1963 struct __ec_todo_unpacked {
1964 uint8_t ctrl, reg, value;
1965 } reg;
1966
1967 struct __ec_todo_unpacked {
1968 uint8_t led, red, green, blue;
1969 } set_rgb;
1970
1971 struct __ec_todo_unpacked {
1972 uint8_t led;
1973 } get_rgb;
1974
1975 struct __ec_todo_unpacked {
1976 uint8_t enable;
1977 } manual_suspend_ctrl;
1978
1979 struct lightbar_params_v0 set_params_v0;
1980 struct lightbar_params_v1 set_params_v1;
1981
1982 struct lightbar_params_v2_timing set_v2par_timing;
1983 struct lightbar_params_v2_tap set_v2par_tap;
1984 struct lightbar_params_v2_oscillation set_v2par_osc;
1985 struct lightbar_params_v2_brightness set_v2par_bright;
1986 struct lightbar_params_v2_thresholds set_v2par_thlds;
1987 struct lightbar_params_v2_colors set_v2par_colors;
1988
1989 struct lightbar_program set_program;
1990 };
1991 } __ec_todo_packed;
1992
1993 struct ec_response_lightbar {
1994 union {
1995 struct __ec_todo_unpacked {
1996 struct __ec_todo_unpacked {
1997 uint8_t reg;
1998 uint8_t ic0;
1999 uint8_t ic1;
2000 } vals[23];
2001 } dump;
2002
2003 struct __ec_todo_unpacked {
2004 uint8_t num;
2005 } get_seq, get_brightness, get_demo;
2006
2007 struct lightbar_params_v0 get_params_v0;
2008 struct lightbar_params_v1 get_params_v1;
2009
2010
2011 struct lightbar_params_v2_timing get_params_v2_timing;
2012 struct lightbar_params_v2_tap get_params_v2_tap;
2013 struct lightbar_params_v2_oscillation get_params_v2_osc;
2014 struct lightbar_params_v2_brightness get_params_v2_bright;
2015 struct lightbar_params_v2_thresholds get_params_v2_thlds;
2016 struct lightbar_params_v2_colors get_params_v2_colors;
2017
2018 struct __ec_todo_unpacked {
2019 uint32_t num;
2020 uint32_t flags;
2021 } version;
2022
2023 struct __ec_todo_unpacked {
2024 uint8_t red, green, blue;
2025 } get_rgb;
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036 };
2037 } __ec_todo_packed;
2038
2039
2040 enum lightbar_command {
2041 LIGHTBAR_CMD_DUMP = 0,
2042 LIGHTBAR_CMD_OFF = 1,
2043 LIGHTBAR_CMD_ON = 2,
2044 LIGHTBAR_CMD_INIT = 3,
2045 LIGHTBAR_CMD_SET_BRIGHTNESS = 4,
2046 LIGHTBAR_CMD_SEQ = 5,
2047 LIGHTBAR_CMD_REG = 6,
2048 LIGHTBAR_CMD_SET_RGB = 7,
2049 LIGHTBAR_CMD_GET_SEQ = 8,
2050 LIGHTBAR_CMD_DEMO = 9,
2051 LIGHTBAR_CMD_GET_PARAMS_V0 = 10,
2052 LIGHTBAR_CMD_SET_PARAMS_V0 = 11,
2053 LIGHTBAR_CMD_VERSION = 12,
2054 LIGHTBAR_CMD_GET_BRIGHTNESS = 13,
2055 LIGHTBAR_CMD_GET_RGB = 14,
2056 LIGHTBAR_CMD_GET_DEMO = 15,
2057 LIGHTBAR_CMD_GET_PARAMS_V1 = 16,
2058 LIGHTBAR_CMD_SET_PARAMS_V1 = 17,
2059 LIGHTBAR_CMD_SET_PROGRAM = 18,
2060 LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19,
2061 LIGHTBAR_CMD_SUSPEND = 20,
2062 LIGHTBAR_CMD_RESUME = 21,
2063 LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22,
2064 LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23,
2065 LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24,
2066 LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25,
2067 LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26,
2068 LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27,
2069 LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28,
2070 LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29,
2071 LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30,
2072 LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,
2073 LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,
2074 LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,
2075 LIGHTBAR_NUM_CMDS
2076 };
2077
2078
2079
2080
2081 #define EC_CMD_LED_CONTROL 0x0029
2082
2083 enum ec_led_id {
2084
2085 EC_LED_ID_BATTERY_LED = 0,
2086
2087
2088
2089
2090 EC_LED_ID_POWER_LED,
2091
2092 EC_LED_ID_ADAPTER_LED,
2093
2094 EC_LED_ID_LEFT_LED,
2095
2096 EC_LED_ID_RIGHT_LED,
2097
2098 EC_LED_ID_RECOVERY_HW_REINIT_LED,
2099
2100 EC_LED_ID_SYSRQ_DEBUG_LED,
2101
2102 EC_LED_ID_COUNT
2103 };
2104
2105
2106 #define EC_LED_FLAGS_QUERY BIT(0)
2107 #define EC_LED_FLAGS_AUTO BIT(1)
2108
2109 enum ec_led_colors {
2110 EC_LED_COLOR_RED = 0,
2111 EC_LED_COLOR_GREEN,
2112 EC_LED_COLOR_BLUE,
2113 EC_LED_COLOR_YELLOW,
2114 EC_LED_COLOR_WHITE,
2115 EC_LED_COLOR_AMBER,
2116
2117 EC_LED_COLOR_COUNT
2118 };
2119
2120 struct ec_params_led_control {
2121 uint8_t led_id;
2122 uint8_t flags;
2123
2124 uint8_t brightness[EC_LED_COLOR_COUNT];
2125 } __ec_align1;
2126
2127 struct ec_response_led_control {
2128
2129
2130
2131
2132
2133
2134
2135 uint8_t brightness_range[EC_LED_COLOR_COUNT];
2136 } __ec_align1;
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147 #define EC_CMD_VBOOT_HASH 0x002A
2148
2149 struct ec_params_vboot_hash {
2150 uint8_t cmd;
2151 uint8_t hash_type;
2152 uint8_t nonce_size;
2153 uint8_t reserved0;
2154 uint32_t offset;
2155 uint32_t size;
2156 uint8_t nonce_data[64];
2157 } __ec_align4;
2158
2159 struct ec_response_vboot_hash {
2160 uint8_t status;
2161 uint8_t hash_type;
2162 uint8_t digest_size;
2163 uint8_t reserved0;
2164 uint32_t offset;
2165 uint32_t size;
2166 uint8_t hash_digest[64];
2167 } __ec_align4;
2168
2169 enum ec_vboot_hash_cmd {
2170 EC_VBOOT_HASH_GET = 0,
2171 EC_VBOOT_HASH_ABORT = 1,
2172 EC_VBOOT_HASH_START = 2,
2173 EC_VBOOT_HASH_RECALC = 3,
2174 };
2175
2176 enum ec_vboot_hash_type {
2177 EC_VBOOT_HASH_TYPE_SHA256 = 0,
2178 };
2179
2180 enum ec_vboot_hash_status {
2181 EC_VBOOT_HASH_STATUS_NONE = 0,
2182 EC_VBOOT_HASH_STATUS_DONE = 1,
2183 EC_VBOOT_HASH_STATUS_BUSY = 2,
2184 };
2185
2186
2187
2188
2189
2190
2191 #define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
2192 #define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
2193 #define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
2194
2195
2196
2197
2198
2199 #define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE
2200
2201
2202
2203
2204
2205
2206 #define EC_CMD_MOTION_SENSE_CMD 0x002B
2207
2208
2209 enum motionsense_command {
2210
2211
2212
2213
2214 MOTIONSENSE_CMD_DUMP = 0,
2215
2216
2217
2218
2219
2220
2221 MOTIONSENSE_CMD_INFO = 1,
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233 MOTIONSENSE_CMD_EC_RATE = 2,
2234
2235
2236
2237
2238
2239 MOTIONSENSE_CMD_SENSOR_ODR = 3,
2240
2241
2242
2243
2244
2245 MOTIONSENSE_CMD_SENSOR_RANGE = 4,
2246
2247
2248
2249
2250
2251
2252
2253
2254 MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,
2255
2256
2257
2258
2259 MOTIONSENSE_CMD_DATA = 6,
2260
2261
2262
2263
2264 MOTIONSENSE_CMD_FIFO_INFO = 7,
2265
2266
2267
2268
2269
2270 MOTIONSENSE_CMD_FIFO_FLUSH = 8,
2271
2272
2273
2274
2275 MOTIONSENSE_CMD_FIFO_READ = 9,
2276
2277
2278
2279
2280
2281 MOTIONSENSE_CMD_PERFORM_CALIB = 10,
2282
2283
2284
2285
2286
2287
2288
2289 MOTIONSENSE_CMD_SENSOR_OFFSET = 11,
2290
2291
2292
2293
2294
2295 MOTIONSENSE_CMD_LIST_ACTIVITIES = 12,
2296
2297
2298
2299
2300
2301 MOTIONSENSE_CMD_SET_ACTIVITY = 13,
2302
2303
2304
2305
2306 MOTIONSENSE_CMD_LID_ANGLE = 14,
2307
2308
2309
2310
2311
2312
2313 MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15,
2314
2315
2316
2317
2318
2319 MOTIONSENSE_CMD_SPOOF = 16,
2320
2321
2322 MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17,
2323
2324
2325
2326
2327
2328 MOTIONSENSE_CMD_SENSOR_SCALE = 18,
2329
2330
2331 MOTIONSENSE_NUM_CMDS
2332 };
2333
2334
2335 enum motionsensor_type {
2336 MOTIONSENSE_TYPE_ACCEL = 0,
2337 MOTIONSENSE_TYPE_GYRO = 1,
2338 MOTIONSENSE_TYPE_MAG = 2,
2339 MOTIONSENSE_TYPE_PROX = 3,
2340 MOTIONSENSE_TYPE_LIGHT = 4,
2341 MOTIONSENSE_TYPE_ACTIVITY = 5,
2342 MOTIONSENSE_TYPE_BARO = 6,
2343 MOTIONSENSE_TYPE_SYNC = 7,
2344 MOTIONSENSE_TYPE_MAX,
2345 };
2346
2347
2348 enum motionsensor_location {
2349 MOTIONSENSE_LOC_BASE = 0,
2350 MOTIONSENSE_LOC_LID = 1,
2351 MOTIONSENSE_LOC_CAMERA = 2,
2352 MOTIONSENSE_LOC_MAX,
2353 };
2354
2355
2356 enum motionsensor_chip {
2357 MOTIONSENSE_CHIP_KXCJ9 = 0,
2358 MOTIONSENSE_CHIP_LSM6DS0 = 1,
2359 MOTIONSENSE_CHIP_BMI160 = 2,
2360 MOTIONSENSE_CHIP_SI1141 = 3,
2361 MOTIONSENSE_CHIP_SI1142 = 4,
2362 MOTIONSENSE_CHIP_SI1143 = 5,
2363 MOTIONSENSE_CHIP_KX022 = 6,
2364 MOTIONSENSE_CHIP_L3GD20H = 7,
2365 MOTIONSENSE_CHIP_BMA255 = 8,
2366 MOTIONSENSE_CHIP_BMP280 = 9,
2367 MOTIONSENSE_CHIP_OPT3001 = 10,
2368 MOTIONSENSE_CHIP_BH1730 = 11,
2369 MOTIONSENSE_CHIP_GPIO = 12,
2370 MOTIONSENSE_CHIP_LIS2DH = 13,
2371 MOTIONSENSE_CHIP_LSM6DSM = 14,
2372 MOTIONSENSE_CHIP_LIS2DE = 15,
2373 MOTIONSENSE_CHIP_LIS2MDL = 16,
2374 MOTIONSENSE_CHIP_LSM6DS3 = 17,
2375 MOTIONSENSE_CHIP_LSM6DSO = 18,
2376 MOTIONSENSE_CHIP_LNG2DM = 19,
2377 MOTIONSENSE_CHIP_MAX,
2378 };
2379
2380
2381 enum motionsensor_orientation {
2382 MOTIONSENSE_ORIENTATION_LANDSCAPE = 0,
2383 MOTIONSENSE_ORIENTATION_PORTRAIT = 1,
2384 MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2,
2385 MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3,
2386 MOTIONSENSE_ORIENTATION_UNKNOWN = 4,
2387 };
2388
2389 struct ec_response_motion_sensor_data {
2390
2391 uint8_t flags;
2392
2393 uint8_t sensor_num;
2394
2395 union {
2396 int16_t data[3];
2397 struct __ec_todo_packed {
2398 uint16_t reserved;
2399 uint32_t timestamp;
2400 };
2401 struct __ec_todo_unpacked {
2402 uint8_t activity;
2403 uint8_t state;
2404 int16_t add_info[2];
2405 };
2406 };
2407 } __ec_todo_packed;
2408
2409
2410 struct ec_response_motion_sense_fifo_info {
2411
2412 uint16_t size;
2413
2414 uint16_t count;
2415
2416
2417
2418 uint32_t timestamp;
2419
2420 uint16_t total_lost;
2421
2422 uint16_t lost[0];
2423 } __ec_todo_packed;
2424
2425 struct ec_response_motion_sense_fifo_data {
2426 uint32_t number_data;
2427 struct ec_response_motion_sensor_data data[0];
2428 } __ec_todo_packed;
2429
2430
2431 enum motionsensor_activity {
2432 MOTIONSENSE_ACTIVITY_RESERVED = 0,
2433 MOTIONSENSE_ACTIVITY_SIG_MOTION = 1,
2434 MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2,
2435 MOTIONSENSE_ACTIVITY_ORIENTATION = 3,
2436 };
2437
2438 struct ec_motion_sense_activity {
2439 uint8_t sensor_num;
2440 uint8_t activity;
2441 uint8_t enable;
2442 uint8_t reserved;
2443 uint16_t parameters[3];
2444 } __ec_todo_unpacked;
2445
2446
2447 #define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0)
2448
2449
2450 #define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0)
2451
2452
2453
2454
2455
2456 #define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0)
2457 #define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1)
2458 #define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2)
2459 #define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3)
2460 #define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4)
2461
2462
2463
2464
2465
2466
2467 #define EC_MOTION_SENSE_NO_VALUE -1
2468
2469 #define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000
2470
2471
2472
2473 #define MOTION_SENSE_SET_OFFSET BIT(0)
2474
2475
2476 #define MOTION_SENSE_DEFAULT_SCALE BIT(15)
2477
2478 #define LID_ANGLE_UNRELIABLE 500
2479
2480 enum motionsense_spoof_mode {
2481
2482 MOTIONSENSE_SPOOF_MODE_DISABLE = 0,
2483
2484
2485 MOTIONSENSE_SPOOF_MODE_CUSTOM,
2486
2487
2488 MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT,
2489
2490
2491 MOTIONSENSE_SPOOF_MODE_QUERY,
2492 };
2493
2494 struct ec_params_motion_sense {
2495 uint8_t cmd;
2496 union {
2497
2498 struct __ec_todo_unpacked {
2499
2500
2501
2502
2503
2504 uint8_t max_sensor_count;
2505 } dump;
2506
2507
2508
2509
2510 struct __ec_todo_unpacked {
2511
2512
2513
2514 int16_t data;
2515 } kb_wake_angle;
2516
2517
2518
2519
2520
2521 struct __ec_todo_unpacked {
2522 uint8_t sensor_num;
2523 } info, info_3, data, fifo_flush, perform_calib,
2524 list_activities;
2525
2526
2527
2528
2529
2530 struct __ec_todo_unpacked {
2531 uint8_t sensor_num;
2532
2533
2534 uint8_t roundup;
2535
2536 uint16_t reserved;
2537
2538
2539 int32_t data;
2540 } ec_rate, sensor_odr, sensor_range;
2541
2542
2543 struct __ec_todo_packed {
2544 uint8_t sensor_num;
2545
2546
2547
2548
2549
2550
2551 uint16_t flags;
2552
2553
2554
2555
2556
2557
2558
2559 int16_t temp;
2560
2561
2562
2563
2564
2565
2566
2567
2568 int16_t offset[3];
2569 } sensor_offset;
2570
2571
2572 struct __ec_todo_packed {
2573 uint8_t sensor_num;
2574
2575
2576
2577
2578
2579
2580 uint16_t flags;
2581
2582
2583
2584
2585
2586
2587
2588 int16_t temp;
2589
2590
2591
2592
2593
2594
2595
2596
2597 uint16_t scale[3];
2598 } sensor_scale;
2599
2600
2601
2602
2603
2604
2605 struct __ec_todo_unpacked {
2606
2607
2608
2609
2610 uint32_t max_data_vector;
2611 } fifo_read;
2612
2613 struct ec_motion_sense_activity set_activity;
2614
2615
2616
2617
2618
2619 struct __ec_todo_unpacked {
2620
2621
2622
2623
2624 int8_t enable;
2625 } fifo_int_enable;
2626
2627
2628 struct __ec_todo_packed {
2629 uint8_t sensor_id;
2630
2631
2632 uint8_t spoof_enable;
2633
2634
2635 uint8_t reserved;
2636
2637
2638 int16_t components[3];
2639 } spoof;
2640
2641
2642 struct __ec_todo_unpacked {
2643
2644
2645
2646
2647 int16_t lid_angle;
2648
2649
2650
2651
2652
2653
2654
2655
2656 int16_t hys_degree;
2657 } tablet_mode_threshold;
2658 };
2659 } __ec_todo_packed;
2660
2661 struct ec_response_motion_sense {
2662 union {
2663
2664 struct __ec_todo_unpacked {
2665
2666 uint8_t module_flags;
2667
2668
2669 uint8_t sensor_count;
2670
2671
2672
2673
2674
2675 struct ec_response_motion_sensor_data sensor[0];
2676 } dump;
2677
2678
2679 struct __ec_todo_unpacked {
2680
2681 uint8_t type;
2682
2683
2684 uint8_t location;
2685
2686
2687 uint8_t chip;
2688 } info;
2689
2690
2691 struct __ec_todo_unpacked {
2692
2693 uint8_t type;
2694
2695
2696 uint8_t location;
2697
2698
2699 uint8_t chip;
2700
2701
2702 uint32_t min_frequency;
2703
2704
2705 uint32_t max_frequency;
2706
2707
2708 uint32_t fifo_max_event_count;
2709 } info_3;
2710
2711
2712 struct ec_response_motion_sensor_data data;
2713
2714
2715
2716
2717
2718
2719
2720
2721 struct __ec_todo_unpacked {
2722
2723 int32_t ret;
2724 } ec_rate, sensor_odr, sensor_range, kb_wake_angle,
2725 fifo_int_enable, spoof;
2726
2727
2728
2729
2730
2731 struct __ec_todo_unpacked {
2732 int16_t temp;
2733 int16_t offset[3];
2734 } sensor_offset, perform_calib;
2735
2736
2737 struct __ec_todo_unpacked {
2738 int16_t temp;
2739 uint16_t scale[3];
2740 } sensor_scale;
2741
2742 struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush;
2743
2744 struct ec_response_motion_sense_fifo_data fifo_read;
2745
2746 struct __ec_todo_packed {
2747 uint16_t reserved;
2748 uint32_t enabled;
2749 uint32_t disabled;
2750 } list_activities;
2751
2752
2753
2754
2755 struct __ec_todo_unpacked {
2756
2757
2758
2759
2760 uint16_t value;
2761 } lid_angle;
2762
2763
2764 struct __ec_todo_unpacked {
2765
2766
2767
2768
2769 uint16_t lid_angle;
2770
2771
2772 uint16_t hys_degree;
2773 } tablet_mode_threshold;
2774
2775 };
2776 } __ec_todo_packed;
2777
2778
2779
2780
2781
2782 #define EC_CMD_FORCE_LID_OPEN 0x002C
2783
2784 struct ec_params_force_lid_open {
2785 uint8_t enabled;
2786 } __ec_align1;
2787
2788
2789
2790 #define EC_CMD_CONFIG_POWER_BUTTON 0x002D
2791
2792 enum ec_config_power_button_flags {
2793
2794 EC_POWER_BUTTON_ENABLE_PULSE = BIT(0),
2795 };
2796
2797 struct ec_params_config_power_button {
2798
2799 uint8_t flags;
2800 } __ec_align1;
2801
2802
2803
2804
2805
2806 #define EC_CMD_USB_CHARGE_SET_MODE 0x0030
2807
2808 struct ec_params_usb_charge_set_mode {
2809 uint8_t usb_port_id;
2810 uint8_t mode:7;
2811 uint8_t inhibit_charge:1;
2812 } __ec_align1;
2813
2814
2815
2816
2817
2818 #define EC_PSTORE_SIZE_MAX 64
2819
2820
2821 #define EC_CMD_PSTORE_INFO 0x0040
2822
2823 struct ec_response_pstore_info {
2824
2825 uint32_t pstore_size;
2826
2827 uint32_t access_size;
2828 } __ec_align4;
2829
2830
2831
2832
2833
2834
2835 #define EC_CMD_PSTORE_READ 0x0041
2836
2837 struct ec_params_pstore_read {
2838 uint32_t offset;
2839 uint32_t size;
2840 } __ec_align4;
2841
2842
2843 #define EC_CMD_PSTORE_WRITE 0x0042
2844
2845 struct ec_params_pstore_write {
2846 uint32_t offset;
2847 uint32_t size;
2848 uint8_t data[EC_PSTORE_SIZE_MAX];
2849 } __ec_align4;
2850
2851
2852
2853
2854
2855 struct ec_params_rtc {
2856 uint32_t time;
2857 } __ec_align4;
2858
2859 struct ec_response_rtc {
2860 uint32_t time;
2861 } __ec_align4;
2862
2863
2864 #define EC_CMD_RTC_GET_VALUE 0x0044
2865 #define EC_CMD_RTC_GET_ALARM 0x0045
2866
2867
2868 #define EC_CMD_RTC_SET_VALUE 0x0046
2869 #define EC_CMD_RTC_SET_ALARM 0x0047
2870
2871
2872 #define EC_RTC_ALARM_CLEAR 0
2873
2874
2875
2876
2877
2878 #define EC_PORT80_SIZE_MAX 32
2879
2880
2881 #define EC_CMD_PORT80_LAST_BOOT 0x0048
2882 #define EC_CMD_PORT80_READ 0x0048
2883
2884 enum ec_port80_subcmd {
2885 EC_PORT80_GET_INFO = 0,
2886 EC_PORT80_READ_BUFFER,
2887 };
2888
2889 struct ec_params_port80_read {
2890 uint16_t subcmd;
2891 union {
2892 struct __ec_todo_unpacked {
2893 uint32_t offset;
2894 uint32_t num_entries;
2895 } read_buffer;
2896 };
2897 } __ec_todo_packed;
2898
2899 struct ec_response_port80_read {
2900 union {
2901 struct __ec_todo_unpacked {
2902 uint32_t writes;
2903 uint32_t history_size;
2904 uint32_t last_boot;
2905 } get_info;
2906 struct __ec_todo_unpacked {
2907 uint16_t codes[EC_PORT80_SIZE_MAX];
2908 } data;
2909 };
2910 } __ec_todo_packed;
2911
2912 struct ec_response_port80_last_boot {
2913 uint16_t code;
2914 } __ec_align2;
2915
2916
2917
2918
2919
2920 #define EC_VSTORE_SLOT_SIZE 64
2921
2922
2923 #define EC_VSTORE_SLOT_MAX 32
2924
2925
2926 #define EC_CMD_VSTORE_INFO 0x0049
2927 struct ec_response_vstore_info {
2928
2929 uint32_t slot_locked;
2930
2931 uint8_t slot_count;
2932 } __ec_align_size1;
2933
2934
2935
2936
2937
2938
2939 #define EC_CMD_VSTORE_READ 0x004A
2940
2941 struct ec_params_vstore_read {
2942 uint8_t slot;
2943 } __ec_align1;
2944
2945 struct ec_response_vstore_read {
2946 uint8_t data[EC_VSTORE_SLOT_SIZE];
2947 } __ec_align1;
2948
2949
2950
2951
2952 #define EC_CMD_VSTORE_WRITE 0x004B
2953
2954 struct ec_params_vstore_write {
2955 uint8_t slot;
2956 uint8_t data[EC_VSTORE_SLOT_SIZE];
2957 } __ec_align1;
2958
2959
2960
2961
2962
2963
2964
2965
2966 #define EC_CMD_THERMAL_SET_THRESHOLD 0x0050
2967 #define EC_CMD_THERMAL_GET_THRESHOLD 0x0051
2968
2969
2970
2971
2972
2973
2974 struct ec_params_thermal_set_threshold {
2975 uint8_t sensor_type;
2976 uint8_t threshold_id;
2977 uint16_t value;
2978 } __ec_align2;
2979
2980
2981 struct ec_params_thermal_get_threshold {
2982 uint8_t sensor_type;
2983 uint8_t threshold_id;
2984 } __ec_align1;
2985
2986 struct ec_response_thermal_get_threshold {
2987 uint16_t value;
2988 } __ec_align2;
2989
2990
2991
2992 enum ec_temp_thresholds {
2993 EC_TEMP_THRESH_WARN = 0,
2994 EC_TEMP_THRESH_HIGH,
2995 EC_TEMP_THRESH_HALT,
2996
2997 EC_TEMP_THRESH_COUNT
2998 };
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022 struct ec_thermal_config {
3023 uint32_t temp_host[EC_TEMP_THRESH_COUNT];
3024 uint32_t temp_host_release[EC_TEMP_THRESH_COUNT];
3025 uint32_t temp_fan_off;
3026 uint32_t temp_fan_max;
3027 } __ec_align4;
3028
3029
3030 struct ec_params_thermal_get_threshold_v1 {
3031 uint32_t sensor_num;
3032 } __ec_align4;
3033
3034
3035
3036
3037
3038
3039 struct ec_params_thermal_set_threshold_v1 {
3040 uint32_t sensor_num;
3041 struct ec_thermal_config cfg;
3042 } __ec_align4;
3043
3044
3045
3046
3047
3048 #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052
3049
3050
3051 struct ec_params_auto_fan_ctrl_v1 {
3052 uint8_t fan_idx;
3053 } __ec_align1;
3054
3055
3056 #define EC_CMD_TMP006_GET_CALIBRATION 0x0053
3057 #define EC_CMD_TMP006_SET_CALIBRATION 0x0054
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069 struct ec_params_tmp006_get_calibration {
3070 uint8_t index;
3071 } __ec_align1;
3072
3073
3074 struct ec_response_tmp006_get_calibration_v0 {
3075 float s0;
3076 float b0;
3077 float b1;
3078 float b2;
3079 } __ec_align4;
3080
3081 struct ec_params_tmp006_set_calibration_v0 {
3082 uint8_t index;
3083 uint8_t reserved[3];
3084 float s0;
3085 float b0;
3086 float b1;
3087 float b2;
3088 } __ec_align4;
3089
3090
3091 struct ec_response_tmp006_get_calibration_v1 {
3092 uint8_t algorithm;
3093 uint8_t num_params;
3094 uint8_t reserved[2];
3095 float val[0];
3096 } __ec_align4;
3097
3098 struct ec_params_tmp006_set_calibration_v1 {
3099 uint8_t index;
3100 uint8_t algorithm;
3101 uint8_t num_params;
3102 uint8_t reserved;
3103 float val[0];
3104 } __ec_align4;
3105
3106
3107
3108 #define EC_CMD_TMP006_GET_RAW 0x0055
3109
3110 struct ec_params_tmp006_get_raw {
3111 uint8_t index;
3112 } __ec_align1;
3113
3114 struct ec_response_tmp006_get_raw {
3115 int32_t t;
3116 int32_t v;
3117 } __ec_align4;
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132 #define EC_CMD_MKBP_STATE 0x0060
3133
3134
3135
3136
3137 #define EC_CMD_MKBP_INFO 0x0061
3138
3139 struct ec_response_mkbp_info {
3140 uint32_t rows;
3141 uint32_t cols;
3142
3143 uint8_t reserved;
3144 } __ec_align_size1;
3145
3146 struct ec_params_mkbp_info {
3147 uint8_t info_type;
3148 uint8_t event_type;
3149 } __ec_align1;
3150
3151 enum ec_mkbp_info_type {
3152
3153
3154
3155
3156
3157 EC_MKBP_INFO_KBD = 0,
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168 EC_MKBP_INFO_SUPPORTED = 1,
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187 EC_MKBP_INFO_CURRENT = 2,
3188 };
3189
3190
3191 #define EC_CMD_MKBP_SIMULATE_KEY 0x0062
3192
3193 struct ec_params_mkbp_simulate_key {
3194 uint8_t col;
3195 uint8_t row;
3196 uint8_t pressed;
3197 } __ec_align1;
3198
3199 #define EC_CMD_GET_KEYBOARD_ID 0x0063
3200
3201 struct ec_response_keyboard_id {
3202 uint32_t keyboard_id;
3203 } __ec_align4;
3204
3205 enum keyboard_id {
3206 KEYBOARD_ID_UNSUPPORTED = 0,
3207 KEYBOARD_ID_UNREADABLE = 0xffffffff,
3208 };
3209
3210
3211 #define EC_CMD_MKBP_SET_CONFIG 0x0064
3212 #define EC_CMD_MKBP_GET_CONFIG 0x0065
3213
3214
3215 enum mkbp_config_flags {
3216 EC_MKBP_FLAGS_ENABLE = 1,
3217 };
3218
3219 enum mkbp_config_valid {
3220 EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
3221 EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
3222 EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
3223 EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
3224 EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
3225 EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
3226 EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
3227 };
3228
3229
3230
3231
3232
3233
3234
3235 struct ec_mkbp_config {
3236 uint32_t valid_mask;
3237 uint8_t flags;
3238 uint8_t valid_flags;
3239 uint16_t scan_period_us;
3240
3241 uint32_t poll_timeout_us;
3242
3243
3244
3245
3246
3247 uint16_t min_post_scan_delay_us;
3248
3249 uint16_t output_settle_us;
3250 uint16_t debounce_down_us;
3251 uint16_t debounce_up_us;
3252
3253 uint8_t fifo_max_depth;
3254 } __ec_align_size1;
3255
3256 struct ec_params_mkbp_set_config {
3257 struct ec_mkbp_config config;
3258 } __ec_align_size1;
3259
3260 struct ec_response_mkbp_get_config {
3261 struct ec_mkbp_config config;
3262 } __ec_align_size1;
3263
3264
3265 #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
3266
3267 enum ec_keyscan_seq_cmd {
3268 EC_KEYSCAN_SEQ_STATUS = 0,
3269 EC_KEYSCAN_SEQ_CLEAR = 1,
3270 EC_KEYSCAN_SEQ_ADD = 2,
3271 EC_KEYSCAN_SEQ_START = 3,
3272 EC_KEYSCAN_SEQ_COLLECT = 4,
3273 };
3274
3275 enum ec_collect_flags {
3276
3277
3278
3279
3280 EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
3281 };
3282
3283 struct ec_collect_item {
3284 uint8_t flags;
3285 } __ec_align1;
3286
3287 struct ec_params_keyscan_seq_ctrl {
3288 uint8_t cmd;
3289 union {
3290 struct __ec_align1 {
3291 uint8_t active;
3292 uint8_t num_items;
3293
3294 uint8_t cur_item;
3295 } status;
3296 struct __ec_todo_unpacked {
3297
3298
3299
3300
3301 uint32_t time_us;
3302 uint8_t scan[0];
3303 } add;
3304 struct __ec_align1 {
3305 uint8_t start_item;
3306 uint8_t num_items;
3307 } collect;
3308 };
3309 } __ec_todo_packed;
3310
3311 struct ec_result_keyscan_seq_ctrl {
3312 union {
3313 struct __ec_todo_unpacked {
3314 uint8_t num_items;
3315
3316 struct ec_collect_item item[0];
3317 } collect;
3318 };
3319 } __ec_todo_packed;
3320
3321
3322
3323
3324
3325
3326 #define EC_CMD_GET_NEXT_EVENT 0x0067
3327
3328 #define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7
3329
3330
3331
3332
3333
3334 #define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT)
3335
3336
3337 #define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1)
3338
3339 enum ec_mkbp_event {
3340
3341 EC_MKBP_EVENT_KEY_MATRIX = 0,
3342
3343
3344 EC_MKBP_EVENT_HOST_EVENT = 1,
3345
3346
3347 EC_MKBP_EVENT_SENSOR_FIFO = 2,
3348
3349
3350 EC_MKBP_EVENT_BUTTON = 3,
3351
3352
3353 EC_MKBP_EVENT_SWITCH = 4,
3354
3355
3356 EC_MKBP_EVENT_FINGERPRINT = 5,
3357
3358
3359
3360
3361
3362 EC_MKBP_EVENT_SYSRQ = 6,
3363
3364
3365
3366
3367
3368 EC_MKBP_EVENT_HOST_EVENT64 = 7,
3369
3370
3371 EC_MKBP_EVENT_CEC_EVENT = 8,
3372
3373
3374 EC_MKBP_EVENT_CEC_MESSAGE = 9,
3375
3376
3377 EC_MKBP_EVENT_COUNT,
3378 };
3379 BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK);
3380
3381 union __ec_align_offset1 ec_response_get_next_data {
3382 uint8_t key_matrix[13];
3383
3384
3385 uint32_t host_event;
3386 uint64_t host_event64;
3387
3388 struct __ec_todo_unpacked {
3389
3390 uint8_t reserved[3];
3391 struct ec_response_motion_sense_fifo_info info;
3392 } sensor_fifo;
3393
3394 uint32_t buttons;
3395
3396 uint32_t switches;
3397
3398 uint32_t fp_events;
3399
3400 uint32_t sysrq;
3401
3402
3403 uint32_t cec_events;
3404 };
3405
3406 union __ec_align_offset1 ec_response_get_next_data_v1 {
3407 uint8_t key_matrix[16];
3408
3409
3410 uint32_t host_event;
3411 uint64_t host_event64;
3412
3413 struct __ec_todo_unpacked {
3414
3415 uint8_t reserved[3];
3416 struct ec_response_motion_sense_fifo_info info;
3417 } sensor_fifo;
3418
3419 uint32_t buttons;
3420
3421 uint32_t switches;
3422
3423 uint32_t fp_events;
3424
3425 uint32_t sysrq;
3426
3427
3428 uint32_t cec_events;
3429
3430 uint8_t cec_message[16];
3431 };
3432 BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16);
3433
3434 struct ec_response_get_next_event {
3435 uint8_t event_type;
3436
3437 union ec_response_get_next_data data;
3438 } __ec_align1;
3439
3440 struct ec_response_get_next_event_v1 {
3441 uint8_t event_type;
3442
3443 union ec_response_get_next_data_v1 data;
3444 } __ec_align1;
3445
3446
3447
3448 #define EC_MKBP_POWER_BUTTON 0
3449 #define EC_MKBP_VOL_UP 1
3450 #define EC_MKBP_VOL_DOWN 2
3451 #define EC_MKBP_RECOVERY 3
3452
3453
3454 #define EC_MKBP_LID_OPEN 0
3455 #define EC_MKBP_TABLET_MODE 1
3456 #define EC_MKBP_BASE_ATTACHED 2
3457
3458
3459 #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
3460
3461 struct ec_response_keyboard_factory_test {
3462 uint16_t shorted;
3463 } __ec_align2;
3464
3465
3466 #define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
3467 #define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F)
3468 #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4
3469 #define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \
3470 >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
3471 #define EC_MKBP_FP_MATCH_IDX_OFFSET 12
3472 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000
3473 #define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \
3474 >> EC_MKBP_FP_MATCH_IDX_OFFSET)
3475 #define EC_MKBP_FP_ENROLL BIT(27)
3476 #define EC_MKBP_FP_MATCH BIT(28)
3477 #define EC_MKBP_FP_FINGER_DOWN BIT(29)
3478 #define EC_MKBP_FP_FINGER_UP BIT(30)
3479 #define EC_MKBP_FP_IMAGE_READY BIT(31)
3480
3481 #define EC_MKBP_FP_ERR_ENROLL_OK 0
3482 #define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
3483 #define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
3484 #define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
3485 #define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
3486
3487 #define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
3488
3489 #define EC_MKBP_FP_ERR_MATCH_NO 0
3490 #define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
3491 #define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
3492 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
3493 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
3494 #define EC_MKBP_FP_ERR_MATCH_YES 1
3495 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
3496 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5
3497
3498
3499
3500
3501
3502
3503 #define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070
3504
3505 struct ec_params_temp_sensor_get_info {
3506 uint8_t id;
3507 } __ec_align1;
3508
3509 struct ec_response_temp_sensor_get_info {
3510 char sensor_name[32];
3511 uint8_t sensor_type;
3512 } __ec_align1;
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531 struct ec_params_host_event_mask {
3532 uint32_t mask;
3533 } __ec_align4;
3534
3535 struct ec_response_host_event_mask {
3536 uint32_t mask;
3537 } __ec_align4;
3538
3539
3540 #define EC_CMD_HOST_EVENT_GET_B 0x0087
3541 #define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
3542 #define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
3543 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
3544
3545
3546 #define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
3547 #define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
3548 #define EC_CMD_HOST_EVENT_CLEAR 0x008C
3549 #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
3550 #define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
3551
3552
3553
3554
3555
3556
3557 struct ec_params_host_event {
3558
3559
3560 uint8_t action;
3561
3562
3563
3564
3565
3566 uint8_t mask_type;
3567
3568
3569 uint16_t reserved;
3570
3571
3572 uint64_t value;
3573 } __ec_align4;
3574
3575
3576
3577
3578
3579
3580 struct ec_response_host_event {
3581
3582
3583 uint64_t value;
3584 } __ec_align4;
3585
3586 enum ec_host_event_action {
3587
3588
3589
3590
3591 EC_HOST_EVENT_GET,
3592
3593
3594 EC_HOST_EVENT_SET,
3595
3596
3597 EC_HOST_EVENT_CLEAR,
3598 };
3599
3600 enum ec_host_event_mask_type {
3601
3602
3603 EC_HOST_EVENT_MAIN,
3604
3605
3606 EC_HOST_EVENT_B,
3607
3608
3609 EC_HOST_EVENT_SCI_MASK,
3610
3611
3612 EC_HOST_EVENT_SMI_MASK,
3613
3614
3615 EC_HOST_EVENT_ALWAYS_REPORT_MASK,
3616
3617
3618 EC_HOST_EVENT_ACTIVE_WAKE_MASK,
3619
3620
3621 EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX,
3622
3623
3624 EC_HOST_EVENT_LAZY_WAKE_MASK_S3,
3625
3626
3627 EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
3628 };
3629
3630 #define EC_CMD_HOST_EVENT 0x00A4
3631
3632
3633
3634
3635
3636 #define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090
3637
3638 struct ec_params_switch_enable_backlight {
3639 uint8_t enabled;
3640 } __ec_align1;
3641
3642
3643 #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091
3644 #define EC_VER_SWITCH_ENABLE_WIRELESS 1
3645
3646
3647 struct ec_params_switch_enable_wireless_v0 {
3648 uint8_t enabled;
3649 } __ec_align1;
3650
3651
3652 struct ec_params_switch_enable_wireless_v1 {
3653
3654 uint8_t now_flags;
3655
3656
3657 uint8_t now_mask;
3658
3659
3660
3661
3662
3663
3664 uint8_t suspend_flags;
3665
3666
3667 uint8_t suspend_mask;
3668 } __ec_align1;
3669
3670
3671 struct ec_response_switch_enable_wireless_v1 {
3672
3673 uint8_t now_flags;
3674
3675
3676 uint8_t suspend_flags;
3677 } __ec_align1;
3678
3679
3680
3681
3682
3683 #define EC_CMD_GPIO_SET 0x0092
3684
3685 struct ec_params_gpio_set {
3686 char name[32];
3687 uint8_t val;
3688 } __ec_align1;
3689
3690
3691 #define EC_CMD_GPIO_GET 0x0093
3692
3693
3694 struct ec_params_gpio_get {
3695 char name[32];
3696 } __ec_align1;
3697
3698 struct ec_response_gpio_get {
3699 uint8_t val;
3700 } __ec_align1;
3701
3702
3703 struct ec_params_gpio_get_v1 {
3704 uint8_t subcmd;
3705 union {
3706 struct __ec_align1 {
3707 char name[32];
3708 } get_value_by_name;
3709 struct __ec_align1 {
3710 uint8_t index;
3711 } get_info;
3712 };
3713 } __ec_align1;
3714
3715 struct ec_response_gpio_get_v1 {
3716 union {
3717 struct __ec_align1 {
3718 uint8_t val;
3719 } get_value_by_name, get_count;
3720 struct __ec_todo_unpacked {
3721 uint8_t val;
3722 char name[32];
3723 uint32_t flags;
3724 } get_info;
3725 };
3726 } __ec_todo_packed;
3727
3728 enum gpio_get_subcmd {
3729 EC_GPIO_GET_BY_NAME = 0,
3730 EC_GPIO_GET_COUNT = 1,
3731 EC_GPIO_GET_INFO = 2,
3732 };
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745 #define EC_CMD_I2C_READ 0x0094
3746
3747 struct ec_params_i2c_read {
3748 uint16_t addr;
3749 uint8_t read_size;
3750 uint8_t port;
3751 uint8_t offset;
3752 } __ec_align_size1;
3753
3754 struct ec_response_i2c_read {
3755 uint16_t data;
3756 } __ec_align2;
3757
3758
3759 #define EC_CMD_I2C_WRITE 0x0095
3760
3761 struct ec_params_i2c_write {
3762 uint16_t data;
3763 uint16_t addr;
3764 uint8_t write_size;
3765 uint8_t port;
3766 uint8_t offset;
3767 } __ec_align_size1;
3768
3769
3770
3771
3772
3773
3774
3775 #define EC_CMD_CHARGE_CONTROL 0x0096
3776 #define EC_VER_CHARGE_CONTROL 1
3777
3778 enum ec_charge_control_mode {
3779 CHARGE_CONTROL_NORMAL = 0,
3780 CHARGE_CONTROL_IDLE,
3781 CHARGE_CONTROL_DISCHARGE,
3782 };
3783
3784 struct ec_params_charge_control {
3785 uint32_t mode;
3786 } __ec_align4;
3787
3788
3789
3790
3791 #define EC_CMD_CONSOLE_SNAPSHOT 0x0097
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805 #define EC_CMD_CONSOLE_READ 0x0098
3806
3807 enum ec_console_read_subcmd {
3808 CONSOLE_READ_NEXT = 0,
3809 CONSOLE_READ_RECENT
3810 };
3811
3812 struct ec_params_console_read_v1 {
3813 uint8_t subcmd;
3814 } __ec_align1;
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825 #define EC_CMD_BATTERY_CUT_OFF 0x0099
3826
3827 #define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
3828
3829 struct ec_params_battery_cutoff {
3830 uint8_t flags;
3831 } __ec_align1;
3832
3833
3834
3835
3836
3837
3838
3839 #define EC_CMD_USB_MUX 0x009A
3840
3841 struct ec_params_usb_mux {
3842 uint8_t mux;
3843 } __ec_align1;
3844
3845
3846
3847
3848 enum ec_ldo_state {
3849 EC_LDO_STATE_OFF = 0,
3850 EC_LDO_STATE_ON = 1,
3851 };
3852
3853
3854
3855
3856 #define EC_CMD_LDO_SET 0x009B
3857
3858 struct ec_params_ldo_set {
3859 uint8_t index;
3860 uint8_t state;
3861 } __ec_align1;
3862
3863
3864
3865
3866 #define EC_CMD_LDO_GET 0x009C
3867
3868 struct ec_params_ldo_get {
3869 uint8_t index;
3870 } __ec_align1;
3871
3872 struct ec_response_ldo_get {
3873 uint8_t state;
3874 } __ec_align1;
3875
3876
3877
3878
3879
3880
3881
3882 #define EC_CMD_POWER_INFO 0x009D
3883
3884 struct ec_response_power_info {
3885 uint32_t usb_dev_type;
3886 uint16_t voltage_ac;
3887 uint16_t voltage_system;
3888 uint16_t current_system;
3889 uint16_t usb_current_limit;
3890 } __ec_align4;
3891
3892
3893
3894
3895 #define EC_CMD_I2C_PASSTHRU 0x009E
3896
3897
3898 #define EC_I2C_FLAG_READ BIT(15)
3899
3900
3901 #define EC_I2C_ADDR_MASK 0x3ff
3902
3903 #define EC_I2C_STATUS_NAK BIT(0)
3904 #define EC_I2C_STATUS_TIMEOUT BIT(1)
3905
3906
3907 #define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
3908
3909 struct ec_params_i2c_passthru_msg {
3910 uint16_t addr_flags;
3911 uint16_t len;
3912 } __ec_align2;
3913
3914 struct ec_params_i2c_passthru {
3915 uint8_t port;
3916 uint8_t num_msgs;
3917 struct ec_params_i2c_passthru_msg msg[];
3918
3919 } __ec_align2;
3920
3921 struct ec_response_i2c_passthru {
3922 uint8_t i2c_status;
3923 uint8_t num_msgs;
3924 uint8_t data[];
3925 } __ec_align1;
3926
3927
3928
3929
3930 #define EC_CMD_HANG_DETECT 0x009F
3931
3932
3933
3934 #define EC_HANG_START_ON_POWER_PRESS BIT(0)
3935
3936
3937 #define EC_HANG_START_ON_LID_CLOSE BIT(1)
3938
3939
3940 #define EC_HANG_START_ON_LID_OPEN BIT(2)
3941
3942
3943 #define EC_HANG_START_ON_RESUME BIT(3)
3944
3945
3946
3947
3948 #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8)
3949
3950
3951 #define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
3952
3953
3954 #define EC_HANG_STOP_ON_SUSPEND BIT(10)
3955
3956
3957
3958
3959
3960
3961
3962 #define EC_HANG_START_NOW BIT(30)
3963
3964
3965
3966
3967
3968
3969 #define EC_HANG_STOP_NOW BIT(31)
3970
3971 struct ec_params_hang_detect {
3972
3973 uint32_t flags;
3974
3975
3976 uint16_t host_event_timeout_msec;
3977
3978
3979 uint16_t warm_reboot_timeout_msec;
3980 } __ec_align4;
3981
3982
3983
3984
3985
3986
3987
3988
3989 #define EC_CMD_CHARGE_STATE 0x00A0
3990
3991
3992 enum charge_state_command {
3993 CHARGE_STATE_CMD_GET_STATE,
3994 CHARGE_STATE_CMD_GET_PARAM,
3995 CHARGE_STATE_CMD_SET_PARAM,
3996 CHARGE_STATE_NUM_CMDS
3997 };
3998
3999
4000
4001
4002
4003 enum charge_state_params {
4004 CS_PARAM_CHG_VOLTAGE,
4005 CS_PARAM_CHG_CURRENT,
4006 CS_PARAM_CHG_INPUT_CURRENT,
4007 CS_PARAM_CHG_STATUS,
4008 CS_PARAM_CHG_OPTION,
4009 CS_PARAM_LIMIT_POWER,
4010
4011
4012
4013
4014
4015 CS_NUM_BASE_PARAMS,
4016
4017
4018 CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000,
4019 CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff,
4020
4021
4022 CS_PARAM_DEBUG_MIN = 0x20000,
4023 CS_PARAM_DEBUG_CTL_MODE = 0x20000,
4024 CS_PARAM_DEBUG_MANUAL_MODE,
4025 CS_PARAM_DEBUG_SEEMS_DEAD,
4026 CS_PARAM_DEBUG_SEEMS_DISCONNECTED,
4027 CS_PARAM_DEBUG_BATT_REMOVED,
4028 CS_PARAM_DEBUG_MANUAL_CURRENT,
4029 CS_PARAM_DEBUG_MANUAL_VOLTAGE,
4030 CS_PARAM_DEBUG_MAX = 0x2ffff,
4031
4032
4033 };
4034
4035 struct ec_params_charge_state {
4036 uint8_t cmd;
4037 union {
4038
4039
4040 struct __ec_todo_unpacked {
4041 uint32_t param;
4042 } get_param;
4043
4044 struct __ec_todo_unpacked {
4045 uint32_t param;
4046 uint32_t value;
4047 } set_param;
4048 };
4049 } __ec_todo_packed;
4050
4051 struct ec_response_charge_state {
4052 union {
4053 struct __ec_align4 {
4054 int ac;
4055 int chg_voltage;
4056 int chg_current;
4057 int chg_input_current;
4058 int batt_state_of_charge;
4059 } get_state;
4060
4061 struct __ec_align4 {
4062 uint32_t value;
4063 } get_param;
4064
4065
4066 };
4067 } __ec_align4;
4068
4069
4070
4071
4072
4073 #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1
4074
4075 struct ec_params_current_limit {
4076 uint32_t limit;
4077 } __ec_align4;
4078
4079
4080
4081
4082 #define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2
4083
4084
4085 struct ec_params_external_power_limit_v1 {
4086 uint16_t current_lim;
4087 uint16_t voltage_lim;
4088 } __ec_align2;
4089
4090 #define EC_POWER_LIMIT_NONE 0xffff
4091
4092
4093
4094
4095 #define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3
4096
4097 struct ec_params_dedicated_charger_limit {
4098 uint16_t current_lim;
4099 uint16_t voltage_lim;
4100 } __ec_align2;
4101
4102
4103
4104
4105
4106 #define EC_CMD_HIBERNATION_DELAY 0x00A8
4107
4108 struct ec_params_hibernation_delay {
4109
4110
4111
4112
4113 uint32_t seconds;
4114 } __ec_align4;
4115
4116 struct ec_response_hibernation_delay {
4117
4118
4119
4120
4121 uint32_t time_g3;
4122
4123
4124
4125
4126
4127 uint32_t time_remaining;
4128
4129
4130
4131
4132
4133 uint32_t hibernate_delay;
4134 } __ec_align4;
4135
4136
4137 #define EC_CMD_HOST_SLEEP_EVENT 0x00A9
4138
4139 enum host_sleep_event {
4140 HOST_SLEEP_EVENT_S3_SUSPEND = 1,
4141 HOST_SLEEP_EVENT_S3_RESUME = 2,
4142 HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
4143 HOST_SLEEP_EVENT_S0IX_RESUME = 4,
4144
4145 HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,
4146 };
4147
4148 struct ec_params_host_sleep_event {
4149 uint8_t sleep_event;
4150 } __ec_align1;
4151
4152
4153
4154
4155
4156 #define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0
4157
4158
4159 #define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF
4160
4161 struct ec_params_host_sleep_event_v1 {
4162
4163 uint8_t sleep_event;
4164
4165
4166 uint8_t reserved;
4167 union {
4168
4169 struct {
4170
4171
4172
4173
4174
4175
4176 uint16_t sleep_timeout_ms;
4177 } suspend_params;
4178
4179
4180 };
4181 } __ec_align2;
4182
4183
4184 #define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000
4185
4186
4187
4188
4189
4190
4191 #define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF
4192
4193 struct ec_response_host_sleep_event_v1 {
4194 union {
4195
4196 struct {
4197
4198
4199
4200
4201
4202 uint32_t sleep_transitions;
4203 } resume_response;
4204
4205
4206 };
4207 } __ec_align4;
4208
4209
4210
4211 #define EC_CMD_DEVICE_EVENT 0x00AA
4212
4213 enum ec_device_event {
4214 EC_DEVICE_EVENT_TRACKPAD,
4215 EC_DEVICE_EVENT_DSP,
4216 EC_DEVICE_EVENT_WIFI,
4217 };
4218
4219 enum ec_device_event_param {
4220
4221 EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS,
4222
4223 EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS,
4224
4225 EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS,
4226 };
4227
4228 #define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32)
4229
4230 struct ec_params_device_event {
4231 uint32_t event_mask;
4232 uint8_t param;
4233 } __ec_align_size1;
4234
4235 struct ec_response_device_event {
4236 uint32_t event_mask;
4237 } __ec_align4;
4238
4239
4240
4241
4242
4243 #define EC_CMD_SB_READ_WORD 0x00B0
4244 #define EC_CMD_SB_WRITE_WORD 0x00B1
4245
4246
4247
4248
4249 #define EC_CMD_SB_READ_BLOCK 0x00B2
4250 #define EC_CMD_SB_WRITE_BLOCK 0x00B3
4251
4252 struct ec_params_sb_rd {
4253 uint8_t reg;
4254 } __ec_align1;
4255
4256 struct ec_response_sb_rd_word {
4257 uint16_t value;
4258 } __ec_align2;
4259
4260 struct ec_params_sb_wr_word {
4261 uint8_t reg;
4262 uint16_t value;
4263 } __ec_align1;
4264
4265 struct ec_response_sb_rd_block {
4266 uint8_t data[32];
4267 } __ec_align1;
4268
4269 struct ec_params_sb_wr_block {
4270 uint8_t reg;
4271 uint16_t data[32];
4272 } __ec_align1;
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283 #define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4
4284
4285 enum ec_battery_vendor_param_mode {
4286 BATTERY_VENDOR_PARAM_MODE_GET = 0,
4287 BATTERY_VENDOR_PARAM_MODE_SET,
4288 };
4289
4290 struct ec_params_battery_vendor_param {
4291 uint32_t param;
4292 uint32_t value;
4293 uint8_t mode;
4294 } __ec_align_size1;
4295
4296 struct ec_response_battery_vendor_param {
4297 uint32_t value;
4298 } __ec_align4;
4299
4300
4301
4302
4303
4304 #define EC_CMD_SB_FW_UPDATE 0x00B5
4305
4306 enum ec_sb_fw_update_subcmd {
4307 EC_SB_FW_UPDATE_PREPARE = 0x0,
4308 EC_SB_FW_UPDATE_INFO = 0x1,
4309 EC_SB_FW_UPDATE_BEGIN = 0x2,
4310 EC_SB_FW_UPDATE_WRITE = 0x3,
4311 EC_SB_FW_UPDATE_END = 0x4,
4312 EC_SB_FW_UPDATE_STATUS = 0x5,
4313 EC_SB_FW_UPDATE_PROTECT = 0x6,
4314 EC_SB_FW_UPDATE_MAX = 0x7,
4315 };
4316
4317 #define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
4318 #define SB_FW_UPDATE_CMD_STATUS_SIZE 2
4319 #define SB_FW_UPDATE_CMD_INFO_SIZE 8
4320
4321 struct ec_sb_fw_update_header {
4322 uint16_t subcmd;
4323 uint16_t fw_id;
4324 } __ec_align4;
4325
4326 struct ec_params_sb_fw_update {
4327 struct ec_sb_fw_update_header hdr;
4328 union {
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338 struct __ec_align4 {
4339 uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
4340 } write;
4341 };
4342 } __ec_align4;
4343
4344 struct ec_response_sb_fw_update {
4345 union {
4346
4347 struct __ec_align1 {
4348 uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE];
4349 } info;
4350
4351
4352 struct __ec_align1 {
4353 uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE];
4354 } status;
4355 };
4356 } __ec_align1;
4357
4358
4359
4360
4361
4362
4363 #define EC_CMD_ENTERING_MODE 0x00B6
4364
4365 struct ec_params_entering_mode {
4366 int vboot_mode;
4367 } __ec_align4;
4368
4369 #define VBOOT_MODE_NORMAL 0
4370 #define VBOOT_MODE_DEVELOPER 1
4371 #define VBOOT_MODE_RECOVERY 2
4372
4373
4374
4375
4376
4377
4378 #define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7
4379
4380 enum ec_i2c_passthru_protect_subcmd {
4381 EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0,
4382 EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1,
4383 };
4384
4385 struct ec_params_i2c_passthru_protect {
4386 uint8_t subcmd;
4387 uint8_t port;
4388 } __ec_align1;
4389
4390 struct ec_response_i2c_passthru_protect {
4391 uint8_t status;
4392 } __ec_align1;
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402 #define MAX_CEC_MSG_LEN 16
4403
4404
4405 #define EC_CMD_CEC_WRITE_MSG 0x00B8
4406
4407
4408
4409
4410
4411 struct ec_params_cec_write {
4412 uint8_t msg[MAX_CEC_MSG_LEN];
4413 } __ec_align1;
4414
4415
4416 #define EC_CMD_CEC_SET 0x00BA
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426 struct ec_params_cec_set {
4427 uint8_t cmd;
4428 uint8_t val;
4429 } __ec_align1;
4430
4431
4432 #define EC_CMD_CEC_GET 0x00BB
4433
4434
4435
4436
4437
4438 struct ec_params_cec_get {
4439 uint8_t cmd;
4440 } __ec_align1;
4441
4442
4443
4444
4445
4446
4447
4448
4449 struct ec_response_cec_get {
4450 uint8_t val;
4451 } __ec_align1;
4452
4453
4454 enum cec_command {
4455
4456 CEC_CMD_ENABLE,
4457
4458 CEC_CMD_LOGICAL_ADDRESS,
4459 };
4460
4461
4462 enum mkbp_cec_event {
4463
4464 EC_MKBP_CEC_SEND_OK = BIT(0),
4465
4466 EC_MKBP_CEC_SEND_FAILED = BIT(1),
4467 };
4468
4469
4470
4471
4472
4473 #define EC_CMD_CODEC_I2S 0x00BC
4474 #define EC_WOV_I2S_SAMPLE_RATE 48000
4475
4476 enum ec_codec_i2s_subcmd {
4477 EC_CODEC_SET_SAMPLE_DEPTH = 0x0,
4478 EC_CODEC_SET_GAIN = 0x1,
4479 EC_CODEC_GET_GAIN = 0x2,
4480 EC_CODEC_I2S_ENABLE = 0x3,
4481 EC_CODEC_I2S_SET_CONFIG = 0x4,
4482 EC_CODEC_I2S_SET_TDM_CONFIG = 0x5,
4483 EC_CODEC_I2S_SET_BCLK = 0x6,
4484 EC_CODEC_I2S_SUBCMD_COUNT = 0x7,
4485 };
4486
4487 enum ec_sample_depth_value {
4488 EC_CODEC_SAMPLE_DEPTH_16 = 0,
4489 EC_CODEC_SAMPLE_DEPTH_24 = 1,
4490 };
4491
4492 enum ec_i2s_config {
4493 EC_DAI_FMT_I2S = 0,
4494 EC_DAI_FMT_RIGHT_J = 1,
4495 EC_DAI_FMT_LEFT_J = 2,
4496 EC_DAI_FMT_PCM_A = 3,
4497 EC_DAI_FMT_PCM_B = 4,
4498 EC_DAI_FMT_PCM_TDM = 5,
4499 };
4500
4501
4502
4503
4504 struct __ec_align1 ec_codec_i2s_gain {
4505 uint8_t left;
4506 uint8_t right;
4507 };
4508
4509 struct __ec_todo_unpacked ec_param_codec_i2s_tdm {
4510 int16_t ch0_delay;
4511 int16_t ch1_delay;
4512 uint8_t adjacent_to_ch0;
4513 uint8_t adjacent_to_ch1;
4514 };
4515
4516 struct __ec_todo_packed ec_param_codec_i2s {
4517
4518 uint8_t cmd;
4519 union {
4520
4521
4522
4523
4524 uint8_t depth;
4525
4526
4527
4528
4529
4530 struct ec_codec_i2s_gain gain;
4531
4532
4533
4534
4535
4536 uint8_t i2s_enable;
4537
4538
4539
4540
4541
4542 uint8_t i2s_config;
4543
4544
4545
4546
4547
4548 struct ec_param_codec_i2s_tdm tdm_param;
4549
4550
4551
4552
4553 uint32_t bclk;
4554 };
4555 };
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565 #define EC_CMD_REBOOT_EC 0x00D2
4566
4567
4568 enum ec_reboot_cmd {
4569 EC_REBOOT_CANCEL = 0,
4570 EC_REBOOT_JUMP_RO = 1,
4571 EC_REBOOT_JUMP_RW = 2,
4572
4573 EC_REBOOT_COLD = 4,
4574 EC_REBOOT_DISABLE_JUMP = 5,
4575 EC_REBOOT_HIBERNATE = 6,
4576 EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7,
4577 };
4578
4579
4580 #define EC_REBOOT_FLAG_RESERVED0 BIT(0)
4581 #define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1)
4582 #define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2)
4583
4584 struct ec_params_reboot_ec {
4585 uint8_t cmd;
4586 uint8_t flags;
4587 } __ec_align1;
4588
4589
4590
4591
4592
4593
4594
4595 #define EC_CMD_GET_PANIC_INFO 0x00D3
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614 #define EC_CMD_REBOOT 0x00D1
4615
4616
4617
4618
4619
4620
4621
4622
4623 #define EC_CMD_RESEND_RESPONSE 0x00DB
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635 #define EC_CMD_VERSION0 0x00DC
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645 #define EC_CMD_PD_EXCHANGE_STATUS 0x0100
4646 #define EC_VER_PD_EXCHANGE_STATUS 2
4647
4648 enum pd_charge_state {
4649 PD_CHARGE_NO_CHANGE = 0,
4650 PD_CHARGE_NONE,
4651 PD_CHARGE_5V,
4652 PD_CHARGE_MAX
4653 };
4654
4655
4656 #define EC_STATUS_HIBERNATING BIT(0)
4657
4658 struct ec_params_pd_status {
4659 uint8_t status;
4660 int8_t batt_soc;
4661 uint8_t charge_state;
4662 } __ec_align1;
4663
4664
4665 #define PD_STATUS_HOST_EVENT BIT(0)
4666 #define PD_STATUS_IN_RW BIT(1)
4667 #define PD_STATUS_JUMPED_TO_IMAGE BIT(2)
4668 #define PD_STATUS_TCPC_ALERT_0 BIT(3)
4669 #define PD_STATUS_TCPC_ALERT_1 BIT(4)
4670 #define PD_STATUS_TCPC_ALERT_2 BIT(5)
4671 #define PD_STATUS_TCPC_ALERT_3 BIT(6)
4672 #define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \
4673 PD_STATUS_TCPC_ALERT_1 | \
4674 PD_STATUS_HOST_EVENT)
4675 struct ec_response_pd_status {
4676 uint32_t curr_lim_ma;
4677 uint16_t status;
4678 int8_t active_charge_port;
4679 } __ec_align_size1;
4680
4681
4682 #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
4683
4684
4685 #define PD_EVENT_UPDATE_DEVICE BIT(0)
4686 #define PD_EVENT_POWER_CHANGE BIT(1)
4687 #define PD_EVENT_IDENTITY_RECEIVED BIT(2)
4688 #define PD_EVENT_DATA_SWAP BIT(3)
4689 struct ec_response_host_event_status {
4690 uint32_t status;
4691 } __ec_align4;
4692
4693
4694 #define EC_CMD_USB_PD_CONTROL 0x0101
4695
4696 enum usb_pd_control_role {
4697 USB_PD_CTRL_ROLE_NO_CHANGE = 0,
4698 USB_PD_CTRL_ROLE_TOGGLE_ON = 1,
4699 USB_PD_CTRL_ROLE_TOGGLE_OFF = 2,
4700 USB_PD_CTRL_ROLE_FORCE_SINK = 3,
4701 USB_PD_CTRL_ROLE_FORCE_SOURCE = 4,
4702 USB_PD_CTRL_ROLE_FREEZE = 5,
4703 USB_PD_CTRL_ROLE_COUNT
4704 };
4705
4706 enum usb_pd_control_mux {
4707 USB_PD_CTRL_MUX_NO_CHANGE = 0,
4708 USB_PD_CTRL_MUX_NONE = 1,
4709 USB_PD_CTRL_MUX_USB = 2,
4710 USB_PD_CTRL_MUX_DP = 3,
4711 USB_PD_CTRL_MUX_DOCK = 4,
4712 USB_PD_CTRL_MUX_AUTO = 5,
4713 USB_PD_CTRL_MUX_COUNT
4714 };
4715
4716 enum usb_pd_control_swap {
4717 USB_PD_CTRL_SWAP_NONE = 0,
4718 USB_PD_CTRL_SWAP_DATA = 1,
4719 USB_PD_CTRL_SWAP_POWER = 2,
4720 USB_PD_CTRL_SWAP_VCONN = 3,
4721 USB_PD_CTRL_SWAP_COUNT
4722 };
4723
4724 struct ec_params_usb_pd_control {
4725 uint8_t port;
4726 uint8_t role;
4727 uint8_t mux;
4728 uint8_t swap;
4729 } __ec_align1;
4730
4731 #define PD_CTRL_RESP_ENABLED_COMMS BIT(0)
4732 #define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1)
4733 #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2)
4734
4735 #define PD_CTRL_RESP_ROLE_POWER BIT(0)
4736 #define PD_CTRL_RESP_ROLE_DATA BIT(1)
4737 #define PD_CTRL_RESP_ROLE_VCONN BIT(2)
4738 #define PD_CTRL_RESP_ROLE_DR_POWER BIT(3)
4739 #define PD_CTRL_RESP_ROLE_DR_DATA BIT(4)
4740 #define PD_CTRL_RESP_ROLE_USB_COMM BIT(5)
4741 #define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6)
4742
4743 struct ec_response_usb_pd_control {
4744 uint8_t enabled;
4745 uint8_t role;
4746 uint8_t polarity;
4747 uint8_t state;
4748 } __ec_align1;
4749
4750 struct ec_response_usb_pd_control_v1 {
4751 uint8_t enabled;
4752 uint8_t role;
4753 uint8_t polarity;
4754 char state[32];
4755 } __ec_align1;
4756
4757
4758 #define USBC_PD_CC_NONE 0
4759 #define USBC_PD_CC_NO_UFP 1
4760 #define USBC_PD_CC_AUDIO_ACC 2
4761 #define USBC_PD_CC_DEBUG_ACC 3
4762 #define USBC_PD_CC_UFP_ATTACHED 4
4763 #define USBC_PD_CC_DFP_ATTACHED 5
4764
4765 struct ec_response_usb_pd_control_v2 {
4766 uint8_t enabled;
4767 uint8_t role;
4768 uint8_t polarity;
4769 char state[32];
4770 uint8_t cc_state;
4771 uint8_t dp_mode;
4772
4773 uint8_t reserved_cable_type;
4774 } __ec_align1;
4775
4776 #define EC_CMD_USB_PD_PORTS 0x0102
4777
4778
4779 #define EC_USB_PD_MAX_PORTS 8
4780
4781 struct ec_response_usb_pd_ports {
4782 uint8_t num_ports;
4783 } __ec_align1;
4784
4785 #define EC_CMD_USB_PD_POWER_INFO 0x0103
4786
4787 #define PD_POWER_CHARGING_PORT 0xff
4788 struct ec_params_usb_pd_power_info {
4789 uint8_t port;
4790 } __ec_align1;
4791
4792 enum usb_chg_type {
4793 USB_CHG_TYPE_NONE,
4794 USB_CHG_TYPE_PD,
4795 USB_CHG_TYPE_C,
4796 USB_CHG_TYPE_PROPRIETARY,
4797 USB_CHG_TYPE_BC12_DCP,
4798 USB_CHG_TYPE_BC12_CDP,
4799 USB_CHG_TYPE_BC12_SDP,
4800 USB_CHG_TYPE_OTHER,
4801 USB_CHG_TYPE_VBUS,
4802 USB_CHG_TYPE_UNKNOWN,
4803 USB_CHG_TYPE_DEDICATED,
4804 };
4805 enum usb_power_roles {
4806 USB_PD_PORT_POWER_DISCONNECTED,
4807 USB_PD_PORT_POWER_SOURCE,
4808 USB_PD_PORT_POWER_SINK,
4809 USB_PD_PORT_POWER_SINK_NOT_CHARGING,
4810 };
4811
4812 struct usb_chg_measures {
4813 uint16_t voltage_max;
4814 uint16_t voltage_now;
4815 uint16_t current_max;
4816 uint16_t current_lim;
4817 } __ec_align2;
4818
4819 struct ec_response_usb_pd_power_info {
4820 uint8_t role;
4821 uint8_t type;
4822 uint8_t dualrole;
4823 uint8_t reserved1;
4824 struct usb_chg_measures meas;
4825 uint32_t max_power;
4826 } __ec_align4;
4827
4828
4829
4830
4831
4832
4833
4834 #define EC_CMD_CHARGE_PORT_COUNT 0x0105
4835 struct ec_response_charge_port_count {
4836 uint8_t port_count;
4837 } __ec_align1;
4838
4839
4840 #define EC_CMD_USB_PD_FW_UPDATE 0x0110
4841
4842 enum usb_pd_fw_update_cmds {
4843 USB_PD_FW_REBOOT,
4844 USB_PD_FW_FLASH_ERASE,
4845 USB_PD_FW_FLASH_WRITE,
4846 USB_PD_FW_ERASE_SIG,
4847 };
4848
4849 struct ec_params_usb_pd_fw_update {
4850 uint16_t dev_id;
4851 uint8_t cmd;
4852 uint8_t port;
4853 uint32_t size;
4854
4855 } __ec_align4;
4856
4857
4858 #define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111
4859
4860 #define PD_RW_HASH_SIZE 20
4861 struct ec_params_usb_pd_rw_hash_entry {
4862 uint16_t dev_id;
4863 uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
4864 uint8_t reserved;
4865
4866
4867
4868
4869 uint32_t current_image;
4870 } __ec_align1;
4871
4872
4873 #define EC_CMD_USB_PD_DEV_INFO 0x0112
4874
4875 struct ec_params_usb_pd_info_request {
4876 uint8_t port;
4877 } __ec_align1;
4878
4879
4880 #define EC_CMD_USB_PD_DISCOVERY 0x0113
4881 struct ec_params_usb_pd_discovery_entry {
4882 uint16_t vid;
4883 uint16_t pid;
4884 uint8_t ptype;
4885 } __ec_align_size1;
4886
4887
4888 #define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114
4889
4890
4891 enum usb_pd_override_ports {
4892 OVERRIDE_DONT_CHARGE = -2,
4893 OVERRIDE_OFF = -1,
4894
4895 };
4896
4897 struct ec_params_charge_port_override {
4898 int16_t override_port;
4899 } __ec_align2;
4900
4901
4902
4903
4904
4905
4906 #define EC_CMD_PD_GET_LOG_ENTRY 0x0115
4907
4908 struct ec_response_pd_log {
4909 uint32_t timestamp;
4910 uint8_t type;
4911 uint8_t size_port;
4912 uint16_t data;
4913 uint8_t payload[0];
4914 } __ec_align4;
4915
4916
4917 #define PD_LOG_TIMESTAMP_SHIFT 10
4918
4919 #define PD_LOG_SIZE_MASK 0x1f
4920 #define PD_LOG_PORT_MASK 0xe0
4921 #define PD_LOG_PORT_SHIFT 5
4922 #define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
4923 ((size) & PD_LOG_SIZE_MASK))
4924 #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
4925 #define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
4926
4927
4928
4929 #define PD_EVENT_MCU_BASE 0x00
4930 #define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0)
4931 #define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1)
4932
4933 #define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2)
4934
4935 #define PD_EVENT_ACC_BASE 0x20
4936 #define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0)
4937 #define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1)
4938
4939 #define PD_EVENT_PS_BASE 0x40
4940 #define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0)
4941
4942 #define PD_EVENT_VIDEO_BASE 0x60
4943 #define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
4944 #define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1)
4945
4946 #define PD_EVENT_NO_ENTRY 0xff
4947
4948
4949
4950
4951
4952
4953
4954 #define CHARGE_FLAGS_DUAL_ROLE BIT(15)
4955
4956 #define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
4957
4958 #define CHARGE_FLAGS_OVERRIDE BIT(13)
4959
4960 #define CHARGE_FLAGS_TYPE_SHIFT 3
4961 #define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
4962
4963 #define CHARGE_FLAGS_ROLE_MASK (7 << 0)
4964
4965
4966
4967
4968 #define PS_FAULT_OCP 1
4969 #define PS_FAULT_FAST_OCP 2
4970 #define PS_FAULT_OVP 3
4971 #define PS_FAULT_DISCH 4
4972
4973
4974
4975
4976 struct mcdp_version {
4977 uint8_t major;
4978 uint8_t minor;
4979 uint16_t build;
4980 } __ec_align4;
4981
4982 struct mcdp_info {
4983 uint8_t family[2];
4984 uint8_t chipid[2];
4985 struct mcdp_version irom;
4986 struct mcdp_version fw;
4987 } __ec_align4;
4988
4989
4990 #define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1])
4991 #define MCDP_FAMILY(family) ((family[0] << 8) | family[1])
4992
4993
4994 #define EC_CMD_USB_PD_GET_AMODE 0x0116
4995 struct ec_params_usb_pd_get_mode_request {
4996 uint16_t svid_idx;
4997 uint8_t port;
4998 } __ec_align_size1;
4999
5000 struct ec_params_usb_pd_get_mode_response {
5001 uint16_t svid;
5002 uint16_t opos;
5003 uint32_t vdo[6];
5004 } __ec_align4;
5005
5006 #define EC_CMD_USB_PD_SET_AMODE 0x0117
5007
5008 enum pd_mode_cmd {
5009 PD_EXIT_MODE = 0,
5010 PD_ENTER_MODE = 1,
5011
5012 PD_MODE_CMD_COUNT,
5013 };
5014
5015 struct ec_params_usb_pd_set_mode_request {
5016 uint32_t cmd;
5017 uint16_t svid;
5018 uint8_t opos;
5019 uint8_t port;
5020 } __ec_align4;
5021
5022
5023 #define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118
5024
5025 struct ec_params_pd_write_log_entry {
5026 uint8_t type;
5027 uint8_t port;
5028 } __ec_align1;
5029
5030
5031
5032 #define EC_CMD_PD_CONTROL 0x0119
5033
5034 enum ec_pd_control_cmd {
5035 PD_SUSPEND = 0,
5036 PD_RESUME,
5037 PD_RESET,
5038 PD_CONTROL_DISABLE,
5039 PD_CHIP_ON,
5040 };
5041
5042 struct ec_params_pd_control {
5043 uint8_t chip;
5044 uint8_t subcmd;
5045 } __ec_align1;
5046
5047
5048 #define EC_CMD_USB_PD_MUX_INFO 0x011A
5049
5050 struct ec_params_usb_pd_mux_info {
5051 uint8_t port;
5052 } __ec_align1;
5053
5054
5055 #define USB_PD_MUX_USB_ENABLED BIT(0)
5056 #define USB_PD_MUX_DP_ENABLED BIT(1)
5057 #define USB_PD_MUX_POLARITY_INVERTED BIT(2)
5058 #define USB_PD_MUX_HPD_IRQ BIT(3)
5059 #define USB_PD_MUX_HPD_LVL BIT(4)
5060
5061 struct ec_response_usb_pd_mux_info {
5062 uint8_t flags;
5063 } __ec_align1;
5064
5065 #define EC_CMD_PD_CHIP_INFO 0x011B
5066
5067 struct ec_params_pd_chip_info {
5068 uint8_t port;
5069 uint8_t renew;
5070 } __ec_align1;
5071
5072 struct ec_response_pd_chip_info {
5073 uint16_t vendor_id;
5074 uint16_t product_id;
5075 uint16_t device_id;
5076 union {
5077 uint8_t fw_version_string[8];
5078 uint64_t fw_version_number;
5079 };
5080 } __ec_align2;
5081
5082 struct ec_response_pd_chip_info_v1 {
5083 uint16_t vendor_id;
5084 uint16_t product_id;
5085 uint16_t device_id;
5086 union {
5087 uint8_t fw_version_string[8];
5088 uint64_t fw_version_number;
5089 };
5090 union {
5091 uint8_t min_req_fw_version_string[8];
5092 uint64_t min_req_fw_version_number;
5093 };
5094 } __ec_align2;
5095
5096
5097 #define EC_CMD_RWSIG_CHECK_STATUS 0x011C
5098
5099 struct ec_response_rwsig_check_status {
5100 uint32_t status;
5101 } __ec_align4;
5102
5103
5104 #define EC_CMD_RWSIG_ACTION 0x011D
5105
5106 enum rwsig_action {
5107 RWSIG_ACTION_ABORT = 0,
5108 RWSIG_ACTION_CONTINUE = 1,
5109 };
5110
5111 struct ec_params_rwsig_action {
5112 uint32_t action;
5113 } __ec_align4;
5114
5115
5116 #define EC_CMD_EFS_VERIFY 0x011E
5117
5118 struct ec_params_efs_verify {
5119 uint8_t region;
5120 } __ec_align1;
5121
5122
5123
5124
5125
5126
5127 #define EC_CMD_GET_CROS_BOARD_INFO 0x011F
5128
5129
5130
5131
5132 #define EC_CMD_SET_CROS_BOARD_INFO 0x0120
5133
5134 enum cbi_data_tag {
5135 CBI_TAG_BOARD_VERSION = 0,
5136 CBI_TAG_OEM_ID = 1,
5137 CBI_TAG_SKU_ID = 2,
5138 CBI_TAG_DRAM_PART_NUM = 3,
5139 CBI_TAG_OEM_NAME = 4,
5140 CBI_TAG_MODEL_ID = 5,
5141 CBI_TAG_COUNT,
5142 };
5143
5144
5145
5146
5147
5148
5149
5150 #define CBI_GET_RELOAD BIT(0)
5151
5152 struct ec_params_get_cbi {
5153 uint32_t tag;
5154 uint32_t flag;
5155 } __ec_align4;
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165 #define CBI_SET_NO_SYNC BIT(0)
5166 #define CBI_SET_INIT BIT(1)
5167
5168 struct ec_params_set_cbi {
5169 uint32_t tag;
5170 uint32_t flag;
5171 uint32_t size;
5172 uint8_t data[];
5173 } __ec_align1;
5174
5175
5176
5177
5178 #define EC_CMD_GET_UPTIME_INFO 0x0121
5179
5180 struct ec_response_uptime_info {
5181
5182
5183
5184
5185
5186
5187
5188
5189 uint32_t time_since_ec_boot_ms;
5190
5191
5192
5193
5194
5195
5196
5197 uint32_t ap_resets_since_ec_boot;
5198
5199
5200
5201
5202
5203 uint32_t ec_reset_flags;
5204
5205
5206 struct ap_reset_log_entry {
5207
5208
5209
5210
5211 uint16_t reset_cause;
5212
5213
5214 uint16_t reserved;
5215
5216
5217
5218
5219
5220
5221 uint32_t reset_time_ms;
5222 } recent_ap_reset[4];
5223 } __ec_align4;
5224
5225
5226
5227
5228
5229
5230
5231 #define EC_CMD_ADD_ENTROPY 0x0122
5232
5233 enum add_entropy_action {
5234
5235 ADD_ENTROPY_ASYNC = 0,
5236
5237
5238
5239
5240
5241 ADD_ENTROPY_RESET_ASYNC = 1,
5242
5243 ADD_ENTROPY_GET_RESULT = 2,
5244 };
5245
5246 struct ec_params_rollback_add_entropy {
5247 uint8_t action;
5248 } __ec_align1;
5249
5250
5251
5252
5253 #define EC_CMD_ADC_READ 0x0123
5254
5255 struct ec_params_adc_read {
5256 uint8_t adc_channel;
5257 } __ec_align1;
5258
5259 struct ec_response_adc_read {
5260 int32_t adc_value;
5261 } __ec_align4;
5262
5263
5264
5265
5266 #define EC_CMD_ROLLBACK_INFO 0x0124
5267
5268 struct ec_response_rollback_info {
5269 int32_t id;
5270 int32_t rollback_min_version;
5271 int32_t rw_rollback_version;
5272 } __ec_align4;
5273
5274
5275
5276 #define EC_CMD_AP_RESET 0x0125
5277
5278
5279
5280
5281
5282
5283
5284
5285 #define EC_CMD_CR51_BASE 0x0300
5286 #define EC_CMD_CR51_LAST 0x03FF
5287
5288
5289
5290
5291
5292 #define EC_CMD_FP_PASSTHRU 0x0400
5293
5294 #define EC_FP_FLAG_NOT_COMPLETE 0x1
5295
5296 struct ec_params_fp_passthru {
5297 uint16_t len;
5298 uint16_t flags;
5299 uint8_t data[];
5300 } __ec_align2;
5301
5302
5303 #define EC_CMD_FP_MODE 0x0402
5304
5305
5306 #define FP_MODE_DEEPSLEEP BIT(0)
5307
5308 #define FP_MODE_FINGER_DOWN BIT(1)
5309
5310 #define FP_MODE_FINGER_UP BIT(2)
5311
5312 #define FP_MODE_CAPTURE BIT(3)
5313
5314 #define FP_MODE_ENROLL_SESSION BIT(4)
5315
5316 #define FP_MODE_ENROLL_IMAGE BIT(5)
5317
5318 #define FP_MODE_MATCH BIT(6)
5319
5320 #define FP_MODE_RESET_SENSOR BIT(7)
5321
5322 #define FP_MODE_DONT_CHANGE BIT(31)
5323
5324 #define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \
5325 FP_MODE_FINGER_DOWN | \
5326 FP_MODE_FINGER_UP | \
5327 FP_MODE_CAPTURE | \
5328 FP_MODE_ENROLL_SESSION | \
5329 FP_MODE_ENROLL_IMAGE | \
5330 FP_MODE_MATCH | \
5331 FP_MODE_RESET_SENSOR | \
5332 FP_MODE_DONT_CHANGE)
5333
5334
5335 #define FP_MODE_CAPTURE_TYPE_SHIFT 28
5336 #define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
5337
5338
5339
5340
5341 enum fp_capture_type {
5342
5343 FP_CAPTURE_VENDOR_FORMAT = 0,
5344
5345 FP_CAPTURE_SIMPLE_IMAGE = 1,
5346
5347 FP_CAPTURE_PATTERN0 = 2,
5348
5349 FP_CAPTURE_PATTERN1 = 3,
5350
5351 FP_CAPTURE_QUALITY_TEST = 4,
5352
5353 FP_CAPTURE_RESET_TEST = 5,
5354 FP_CAPTURE_TYPE_MAX,
5355 };
5356
5357 #define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \
5358 >> FP_MODE_CAPTURE_TYPE_SHIFT)
5359
5360 struct ec_params_fp_mode {
5361 uint32_t mode;
5362 } __ec_align4;
5363
5364 struct ec_response_fp_mode {
5365 uint32_t mode;
5366 } __ec_align4;
5367
5368
5369 #define EC_CMD_FP_INFO 0x0403
5370
5371
5372 #define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
5373
5374 #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
5375
5376 #define FP_ERROR_NO_IRQ BIT(12)
5377
5378 #define FP_ERROR_SPI_COMM BIT(13)
5379
5380 #define FP_ERROR_BAD_HWID BIT(14)
5381
5382 #define FP_ERROR_INIT_FAIL BIT(15)
5383
5384 struct ec_response_fp_info_v0 {
5385
5386 uint32_t vendor_id;
5387 uint32_t product_id;
5388 uint32_t model_id;
5389 uint32_t version;
5390
5391 uint32_t frame_size;
5392 uint32_t pixel_format;
5393 uint16_t width;
5394 uint16_t height;
5395 uint16_t bpp;
5396 uint16_t errors;
5397 } __ec_align4;
5398
5399 struct ec_response_fp_info {
5400
5401 uint32_t vendor_id;
5402 uint32_t product_id;
5403 uint32_t model_id;
5404 uint32_t version;
5405
5406 uint32_t frame_size;
5407 uint32_t pixel_format;
5408 uint16_t width;
5409 uint16_t height;
5410 uint16_t bpp;
5411 uint16_t errors;
5412
5413 uint32_t template_size;
5414 uint16_t template_max;
5415 uint16_t template_valid;
5416 uint32_t template_dirty;
5417 uint32_t template_version;
5418 } __ec_align4;
5419
5420
5421 #define EC_CMD_FP_FRAME 0x0404
5422
5423
5424 #define FP_FRAME_INDEX_SHIFT 28
5425
5426 #define FP_FRAME_INDEX_RAW_IMAGE 0
5427
5428 #define FP_FRAME_INDEX_TEMPLATE 1
5429 #define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT)
5430 #define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
5431
5432
5433 #define FP_TEMPLATE_FORMAT_VERSION 3
5434
5435
5436 #define FP_CONTEXT_NONCE_BYTES 12
5437 #define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t))
5438 #define FP_CONTEXT_TAG_BYTES 16
5439 #define FP_CONTEXT_SALT_BYTES 16
5440 #define FP_CONTEXT_TPM_BYTES 32
5441
5442 struct ec_fp_template_encryption_metadata {
5443
5444
5445
5446 uint16_t struct_version;
5447
5448 uint16_t reserved;
5449
5450
5451
5452
5453 uint8_t nonce[FP_CONTEXT_NONCE_BYTES];
5454 uint8_t salt[FP_CONTEXT_SALT_BYTES];
5455 uint8_t tag[FP_CONTEXT_TAG_BYTES];
5456 };
5457
5458 struct ec_params_fp_frame {
5459
5460
5461
5462
5463
5464 uint32_t offset;
5465 uint32_t size;
5466 } __ec_align4;
5467
5468
5469 #define EC_CMD_FP_TEMPLATE 0x0405
5470
5471
5472 #define FP_TEMPLATE_COMMIT 0x80000000
5473
5474 struct ec_params_fp_template {
5475 uint32_t offset;
5476 uint32_t size;
5477 uint8_t data[];
5478 } __ec_align4;
5479
5480
5481 #define EC_CMD_FP_CONTEXT 0x0406
5482
5483 struct ec_params_fp_context {
5484 uint32_t userid[FP_CONTEXT_USERID_WORDS];
5485 } __ec_align4;
5486
5487 #define EC_CMD_FP_STATS 0x0407
5488
5489 #define FPSTATS_CAPTURE_INV BIT(0)
5490 #define FPSTATS_MATCHING_INV BIT(1)
5491
5492 struct ec_response_fp_stats {
5493 uint32_t capture_time_us;
5494 uint32_t matching_time_us;
5495 uint32_t overall_time_us;
5496 struct {
5497 uint32_t lo;
5498 uint32_t hi;
5499 } overall_t0;
5500 uint8_t timestamps_invalid;
5501 int8_t template_matched;
5502 } __ec_align2;
5503
5504 #define EC_CMD_FP_SEED 0x0408
5505 struct ec_params_fp_seed {
5506
5507
5508
5509 uint16_t struct_version;
5510
5511 uint16_t reserved;
5512
5513 uint8_t seed[FP_CONTEXT_TPM_BYTES];
5514 } __ec_align4;
5515
5516 #define EC_CMD_FP_ENC_STATUS 0x0409
5517
5518
5519 #define FP_ENC_STATUS_SEED_SET BIT(0)
5520
5521 struct ec_response_fp_encryption_status {
5522
5523 uint32_t valid_flags;
5524
5525 uint32_t status;
5526 } __ec_align4;
5527
5528
5529
5530
5531
5532 #define EC_CMD_TP_SELF_TEST 0x0500
5533
5534
5535 #define EC_CMD_TP_FRAME_INFO 0x0501
5536
5537 struct ec_response_tp_frame_info {
5538 uint32_t n_frames;
5539 uint32_t frame_sizes[0];
5540 } __ec_align4;
5541
5542
5543 #define EC_CMD_TP_FRAME_SNAPSHOT 0x0502
5544
5545
5546 #define EC_CMD_TP_FRAME_GET 0x0503
5547
5548 struct ec_params_tp_frame_get {
5549 uint32_t frame_index;
5550 uint32_t offset;
5551 uint32_t size;
5552 } __ec_align4;
5553
5554
5555
5556
5557 #define EC_COMM_TEXT_MAX 8
5558
5559
5560
5561
5562
5563 #define EC_CMD_BATTERY_GET_STATIC 0x0600
5564
5565
5566
5567
5568
5569 struct ec_params_battery_static_info {
5570 uint8_t index;
5571 } __ec_align_size1;
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583 struct ec_response_battery_static_info {
5584 uint16_t design_capacity;
5585 uint16_t design_voltage;
5586 char manufacturer[EC_COMM_TEXT_MAX];
5587 char model[EC_COMM_TEXT_MAX];
5588 char serial[EC_COMM_TEXT_MAX];
5589 char type[EC_COMM_TEXT_MAX];
5590
5591 uint32_t cycle_count;
5592 } __ec_align4;
5593
5594
5595
5596
5597
5598 #define EC_CMD_BATTERY_GET_DYNAMIC 0x0601
5599
5600
5601
5602
5603
5604 struct ec_params_battery_dynamic_info {
5605 uint8_t index;
5606 } __ec_align_size1;
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618 struct ec_response_battery_dynamic_info {
5619 int16_t actual_voltage;
5620 int16_t actual_current;
5621 int16_t remaining_capacity;
5622 int16_t full_capacity;
5623 int16_t flags;
5624 int16_t desired_voltage;
5625 int16_t desired_current;
5626 } __ec_align2;
5627
5628
5629
5630
5631 #define EC_CMD_CHARGER_CONTROL 0x0602
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643 struct ec_params_charger_control {
5644 int16_t max_current;
5645 uint16_t otg_voltage;
5646 uint8_t allow_charging;
5647 } __ec_align_size1;
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675 #define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00
5676 #define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF
5677
5678
5679
5680
5681
5682 #define EC_PRIVATE_HOST_COMMAND_VALUE(command) \
5683 (EC_CMD_BOARD_SPECIFIC_BASE + (command))
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709 #define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n))
5710 #define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff)
5711
5712
5713
5714
5715
5716
5717
5718
5719 #define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
5720 #define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
5721 #define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
5722
5723
5724
5725 #endif