1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2006, Intel Corporation.
4 */
5 #ifndef IOP_ADMA_H
6 #define IOP_ADMA_H
7 #include <linux/types.h>
8 #include <linux/dmaengine.h>
9 #include <linux/interrupt.h>
10
11 #define IOP_ADMA_SLOT_SIZE 32
12 #define IOP_ADMA_THRESHOLD 4
13 #ifdef DEBUG
14 #define IOP_PARANOIA 1
15 #else
16 #define IOP_PARANOIA 0
17 #endif
18 #define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x))
19
20 #define DMA0_ID 0
21 #define DMA1_ID 1
22 #define AAU_ID 2
23
24 /**
25 * struct iop_adma_device - internal representation of an ADMA device
26 * @pdev: Platform device
27 * @id: HW ADMA Device selector
28 * @dma_desc_pool: base of DMA descriptor region (DMA address)
29 * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
30 * @common: embedded struct dma_device
31 */
32 struct iop_adma_device {
33 struct platform_device *pdev;
34 int id;
35 dma_addr_t dma_desc_pool;
36 void *dma_desc_pool_virt;
37 struct dma_device common;
38 };
39
40 /**
41 * struct iop_adma_chan - internal representation of an ADMA device
42 * @pending: allows batching of hardware operations
43 * @lock: serializes enqueue/dequeue operations to the slot pool
44 * @mmr_base: memory mapped register base
45 * @chain: device chain view of the descriptors
46 * @device: parent device
47 * @common: common dmaengine channel object members
48 * @last_used: place holder for allocation to continue from where it left off
49 * @all_slots: complete domain of slots usable by the channel
50 * @slots_allocated: records the actual size of the descriptor slot pool
51 * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
52 */
53 struct iop_adma_chan {
54 int pending;
55 spinlock_t lock; /* protects the descriptor slot pool */
56 void __iomem *mmr_base;
57 struct list_head chain;
58 struct iop_adma_device *device;
59 struct dma_chan common;
60 struct iop_adma_desc_slot *last_used;
61 struct list_head all_slots;
62 int slots_allocated;
63 struct tasklet_struct irq_tasklet;
64 };
65
66 /**
67 * struct iop_adma_desc_slot - IOP-ADMA software descriptor
68 * @slot_node: node on the iop_adma_chan.all_slots list
69 * @chain_node: node on the op_adma_chan.chain list
70 * @hw_desc: virtual address of the hardware descriptor chain
71 * @phys: hardware address of the hardware descriptor chain
72 * @group_head: first operation in a transaction
73 * @slot_cnt: total slots used in an transaction (group of operations)
74 * @slots_per_op: number of slots per operation
75 * @idx: pool index
76 * @tx_list: list of descriptors that are associated with one operation
77 * @async_tx: support for the async_tx api
78 * @group_list: list of slots that make up a multi-descriptor transaction
79 * for example transfer lengths larger than the supported hw max
80 * @xor_check_result: result of zero sum
81 * @crc32_result: result crc calculation
82 */
83 struct iop_adma_desc_slot {
84 struct list_head slot_node;
85 struct list_head chain_node;
86 void *hw_desc;
87 struct iop_adma_desc_slot *group_head;
88 u16 slot_cnt;
89 u16 slots_per_op;
90 u16 idx;
91 struct list_head tx_list;
92 struct dma_async_tx_descriptor async_tx;
93 union {
94 u32 *xor_check_result;
95 u32 *crc32_result;
96 u32 *pq_check_result;
97 };
98 };
99
100 struct iop_adma_platform_data {
101 int hw_id;
102 dma_cap_mask_t cap_mask;
103 size_t pool_size;
104 };
105
106 #define to_iop_sw_desc(addr_hw_desc) \
107 container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
108 #define iop_hw_desc_slot_idx(hw_desc, idx) \
109 ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
110 #endif