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10 #ifndef __LINUX_MFD_AB8500_REGULATOR_H
11 #define __LINUX_MFD_AB8500_REGULATOR_H
12
13 #include <linux/platform_device.h>
14
15
16 enum ab8500_regulator_id {
17 AB8500_LDO_AUX1,
18 AB8500_LDO_AUX2,
19 AB8500_LDO_AUX3,
20 AB8500_LDO_INTCORE,
21 AB8500_LDO_TVOUT,
22 AB8500_LDO_AUDIO,
23 AB8500_LDO_ANAMIC1,
24 AB8500_LDO_ANAMIC2,
25 AB8500_LDO_DMIC,
26 AB8500_LDO_ANA,
27 AB8500_NUM_REGULATORS,
28 };
29
30
31 enum ab8505_regulator_id {
32 AB8505_LDO_AUX1,
33 AB8505_LDO_AUX2,
34 AB8505_LDO_AUX3,
35 AB8505_LDO_AUX4,
36 AB8505_LDO_AUX5,
37 AB8505_LDO_AUX6,
38 AB8505_LDO_INTCORE,
39 AB8505_LDO_ADC,
40 AB8505_LDO_AUDIO,
41 AB8505_LDO_ANAMIC1,
42 AB8505_LDO_ANAMIC2,
43 AB8505_LDO_AUX8,
44 AB8505_LDO_ANA,
45 AB8505_NUM_REGULATORS,
46 };
47
48
49 struct ab8500_regulator_reg_init {
50 int id;
51 u8 mask;
52 u8 value;
53 };
54
55 #define INIT_REGULATOR_REGISTER(_id, _mask, _value) \
56 { \
57 .id = _id, \
58 .mask = _mask, \
59 .value = _value, \
60 }
61
62
63 enum ab8500_regulator_reg {
64 AB8500_REGUREQUESTCTRL2,
65 AB8500_REGUREQUESTCTRL3,
66 AB8500_REGUREQUESTCTRL4,
67 AB8500_REGUSYSCLKREQ1HPVALID1,
68 AB8500_REGUSYSCLKREQ1HPVALID2,
69 AB8500_REGUHWHPREQ1VALID1,
70 AB8500_REGUHWHPREQ1VALID2,
71 AB8500_REGUHWHPREQ2VALID1,
72 AB8500_REGUHWHPREQ2VALID2,
73 AB8500_REGUSWHPREQVALID1,
74 AB8500_REGUSWHPREQVALID2,
75 AB8500_REGUSYSCLKREQVALID1,
76 AB8500_REGUSYSCLKREQVALID2,
77 AB8500_REGUMISC1,
78 AB8500_VAUDIOSUPPLY,
79 AB8500_REGUCTRL1VAMIC,
80 AB8500_VPLLVANAREGU,
81 AB8500_VREFDDR,
82 AB8500_EXTSUPPLYREGU,
83 AB8500_VAUX12REGU,
84 AB8500_VRF1VAUX3REGU,
85 AB8500_VAUX1SEL,
86 AB8500_VAUX2SEL,
87 AB8500_VRF1VAUX3SEL,
88 AB8500_REGUCTRL2SPARE,
89 AB8500_REGUCTRLDISCH,
90 AB8500_REGUCTRLDISCH2,
91 AB8500_NUM_REGULATOR_REGISTERS,
92 };
93
94
95 enum ab8505_regulator_reg {
96 AB8505_REGUREQUESTCTRL1,
97 AB8505_REGUREQUESTCTRL2,
98 AB8505_REGUREQUESTCTRL3,
99 AB8505_REGUREQUESTCTRL4,
100 AB8505_REGUSYSCLKREQ1HPVALID1,
101 AB8505_REGUSYSCLKREQ1HPVALID2,
102 AB8505_REGUHWHPREQ1VALID1,
103 AB8505_REGUHWHPREQ1VALID2,
104 AB8505_REGUHWHPREQ2VALID1,
105 AB8505_REGUHWHPREQ2VALID2,
106 AB8505_REGUSWHPREQVALID1,
107 AB8505_REGUSWHPREQVALID2,
108 AB8505_REGUSYSCLKREQVALID1,
109 AB8505_REGUSYSCLKREQVALID2,
110 AB8505_REGUVAUX4REQVALID,
111 AB8505_REGUMISC1,
112 AB8505_VAUDIOSUPPLY,
113 AB8505_REGUCTRL1VAMIC,
114 AB8505_VSMPSAREGU,
115 AB8505_VSMPSBREGU,
116 AB8505_VSAFEREGU,
117 AB8505_VPLLVANAREGU,
118 AB8505_EXTSUPPLYREGU,
119 AB8505_VAUX12REGU,
120 AB8505_VRF1VAUX3REGU,
121 AB8505_VSMPSASEL1,
122 AB8505_VSMPSASEL2,
123 AB8505_VSMPSASEL3,
124 AB8505_VSMPSBSEL1,
125 AB8505_VSMPSBSEL2,
126 AB8505_VSMPSBSEL3,
127 AB8505_VSAFESEL1,
128 AB8505_VSAFESEL2,
129 AB8505_VSAFESEL3,
130 AB8505_VAUX1SEL,
131 AB8505_VAUX2SEL,
132 AB8505_VRF1VAUX3SEL,
133 AB8505_VAUX4REQCTRL,
134 AB8505_VAUX4REGU,
135 AB8505_VAUX4SEL,
136 AB8505_REGUCTRLDISCH,
137 AB8505_REGUCTRLDISCH2,
138 AB8505_REGUCTRLDISCH3,
139 AB8505_CTRLVAUX5,
140 AB8505_CTRLVAUX6,
141 AB8505_NUM_REGULATOR_REGISTERS,
142 };
143
144
145 struct ab8500_ext_regulator_cfg {
146 bool hwreq;
147 };
148
149 enum ab8500_ext_regulator_id {
150 AB8500_EXT_SUPPLY1,
151 AB8500_EXT_SUPPLY2,
152 AB8500_EXT_SUPPLY3,
153 AB8500_NUM_EXT_REGULATORS,
154 };
155
156
157 struct ab8500_regulator_platform_data {
158 int num_reg_init;
159 struct ab8500_regulator_reg_init *reg_init;
160 int num_regulator;
161 struct regulator_init_data *regulator;
162 int num_ext_regulator;
163 struct regulator_init_data *ext_regulator;
164 };
165
166 #endif