1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * include/linux/amba/pl022.h
4 *
5 * Copyright (C) 2008-2009 ST-Ericsson AB
6 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
7 *
8 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 *
10 * Initial version inspired by:
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
12 * Initial adoption to PL022 by:
13 * Sachin Verma <sachin.verma@st.com>
14 */
15
16 #ifndef _SSP_PL022_H
17 #define _SSP_PL022_H
18
19 #include <linux/types.h>
20
21 /**
22 * whether SSP is in loopback mode or not
23 */
24 enum ssp_loopback {
25 LOOPBACK_DISABLED,
26 LOOPBACK_ENABLED
27 };
28
29 /**
30 * enum ssp_interface - interfaces allowed for this SSP Controller
31 * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
32 * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
33 * interface
34 * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
35 * interface
36 * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
37 * &STn8815 only)
38 */
39 enum ssp_interface {
40 SSP_INTERFACE_MOTOROLA_SPI,
41 SSP_INTERFACE_TI_SYNC_SERIAL,
42 SSP_INTERFACE_NATIONAL_MICROWIRE,
43 SSP_INTERFACE_UNIDIRECTIONAL
44 };
45
46 /**
47 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
48 */
49 enum ssp_hierarchy {
50 SSP_MASTER,
51 SSP_SLAVE
52 };
53
54 /**
55 * enum ssp_clock_params - clock parameters, to set SSP clock at a
56 * desired freq
57 */
58 struct ssp_clock_params {
59 u8 cpsdvsr; /* value from 2 to 254 (even only!) */
60 u8 scr; /* value from 0 to 255 */
61 };
62
63 /**
64 * enum ssp_rx_endian - endianess of Rx FIFO Data
65 * this feature is only available in ST versionf of PL022
66 */
67 enum ssp_rx_endian {
68 SSP_RX_MSB,
69 SSP_RX_LSB
70 };
71
72 /**
73 * enum ssp_tx_endian - endianess of Tx FIFO Data
74 */
75 enum ssp_tx_endian {
76 SSP_TX_MSB,
77 SSP_TX_LSB
78 };
79
80 /**
81 * enum ssp_data_size - number of bits in one data element
82 */
83 enum ssp_data_size {
84 SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
85 SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
86 SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
87 SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
88 SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
89 SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
90 SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
91 SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
92 SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
93 SSP_DATA_BITS_31, SSP_DATA_BITS_32
94 };
95
96 /**
97 * enum ssp_mode - SSP mode of operation (Communication modes)
98 */
99 enum ssp_mode {
100 INTERRUPT_TRANSFER,
101 POLLING_TRANSFER,
102 DMA_TRANSFER
103 };
104
105 /**
106 * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
107 * IT: Interrupt fires when _N_ or more elements in RX FIFO.
108 */
109 enum ssp_rx_level_trig {
110 SSP_RX_1_OR_MORE_ELEM,
111 SSP_RX_4_OR_MORE_ELEM,
112 SSP_RX_8_OR_MORE_ELEM,
113 SSP_RX_16_OR_MORE_ELEM,
114 SSP_RX_32_OR_MORE_ELEM
115 };
116
117 /**
118 * Transmit FIFO watermark level which triggers (IT Interrupt fires
119 * when _N_ or more empty locations in TX FIFO)
120 */
121 enum ssp_tx_level_trig {
122 SSP_TX_1_OR_MORE_EMPTY_LOC,
123 SSP_TX_4_OR_MORE_EMPTY_LOC,
124 SSP_TX_8_OR_MORE_EMPTY_LOC,
125 SSP_TX_16_OR_MORE_EMPTY_LOC,
126 SSP_TX_32_OR_MORE_EMPTY_LOC
127 };
128
129 /**
130 * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
131 * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
132 * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
133 */
134 enum ssp_spi_clk_phase {
135 SSP_CLK_FIRST_EDGE,
136 SSP_CLK_SECOND_EDGE
137 };
138
139 /**
140 * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
141 * @SSP_CLK_POL_IDLE_LOW: Low inactive level
142 * @SSP_CLK_POL_IDLE_HIGH: High inactive level
143 */
144 enum ssp_spi_clk_pol {
145 SSP_CLK_POL_IDLE_LOW,
146 SSP_CLK_POL_IDLE_HIGH
147 };
148
149 /**
150 * Microwire Conrol Lengths Command size in microwire format
151 */
152 enum ssp_microwire_ctrl_len {
153 SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
154 SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
155 SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
156 SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
157 SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
158 SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
159 SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
160 SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
161 SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
162 SSP_BITS_31, SSP_BITS_32
163 };
164
165 /**
166 * enum Microwire Wait State
167 * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
168 * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
169 */
170 enum ssp_microwire_wait_state {
171 SSP_MWIRE_WAIT_ZERO,
172 SSP_MWIRE_WAIT_ONE
173 };
174
175 /**
176 * enum ssp_duplex - whether Full/Half Duplex on microwire, only
177 * available in the ST Micro variant.
178 * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
179 * SSPRXD not used
180 * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
181 * an input.
182 */
183 enum ssp_duplex {
184 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
185 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
186 };
187
188 /**
189 * enum ssp_clkdelay - an optional clock delay on the feedback clock
190 * only available in the ST Micro PL023 variant.
191 * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
192 * slave is sampled directly
193 * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
194 * a delay of T-dt
195 * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
196 * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
197 * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
198 * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
199 * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
200 * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
201 */
202 enum ssp_clkdelay {
203 SSP_FEEDBACK_CLK_DELAY_NONE,
204 SSP_FEEDBACK_CLK_DELAY_1T,
205 SSP_FEEDBACK_CLK_DELAY_2T,
206 SSP_FEEDBACK_CLK_DELAY_3T,
207 SSP_FEEDBACK_CLK_DELAY_4T,
208 SSP_FEEDBACK_CLK_DELAY_5T,
209 SSP_FEEDBACK_CLK_DELAY_6T,
210 SSP_FEEDBACK_CLK_DELAY_7T
211 };
212
213 /**
214 * CHIP select/deselect commands
215 */
216 enum ssp_chip_select {
217 SSP_CHIP_SELECT,
218 SSP_CHIP_DESELECT
219 };
220
221
222 struct dma_chan;
223 /**
224 * struct pl022_ssp_master - device.platform_data for SPI controller devices.
225 * @bus_id: identifier for this bus
226 * @num_chipselect: chipselects are used to distinguish individual
227 * SPI slaves, and are numbered from zero to num_chipselects - 1.
228 * each slave has a chipselect signal, but it's common that not
229 * every chipselect is connected to a slave.
230 * @enable_dma: if true enables DMA driven transfers.
231 * @dma_rx_param: parameter to locate an RX DMA channel.
232 * @dma_tx_param: parameter to locate a TX DMA channel.
233 * @autosuspend_delay: delay in ms following transfer completion before the
234 * runtime power management system suspends the device. A setting of 0
235 * indicates no delay and the device will be suspended immediately.
236 * @rt: indicates the controller should run the message pump with realtime
237 * priority to minimise the transfer latency on the bus.
238 * @chipselects: list of <num_chipselects> chip select gpios
239 */
240 struct pl022_ssp_controller {
241 u16 bus_id;
242 u8 num_chipselect;
243 u8 enable_dma:1;
244 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
245 void *dma_rx_param;
246 void *dma_tx_param;
247 int autosuspend_delay;
248 bool rt;
249 int *chipselects;
250 };
251
252 /**
253 * struct ssp_config_chip - spi_board_info.controller_data for SPI
254 * slave devices, copied to spi_device.controller_data.
255 *
256 * @iface: Interface type(Motorola, TI, Microwire, Universal)
257 * @hierarchy: sets whether interface is master or slave
258 * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
259 * @clk_freq: Tune freq parameters of SSP(when in master mode)
260 * @com_mode: communication mode: polling, Interrupt or DMA
261 * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
262 * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
263 * @ctrl_len: Microwire interface: Control length
264 * @wait_state: Microwire interface: Wait state
265 * @duplex: Microwire interface: Full/Half duplex
266 * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
267 * before sampling the incoming line
268 * @cs_control: function pointer to board-specific function to
269 * assert/deassert I/O port to control HW generation of devices chip-select.
270 */
271 struct pl022_config_chip {
272 enum ssp_interface iface;
273 enum ssp_hierarchy hierarchy;
274 bool slave_tx_disable;
275 struct ssp_clock_params clk_freq;
276 enum ssp_mode com_mode;
277 enum ssp_rx_level_trig rx_lev_trig;
278 enum ssp_tx_level_trig tx_lev_trig;
279 enum ssp_microwire_ctrl_len ctrl_len;
280 enum ssp_microwire_wait_state wait_state;
281 enum ssp_duplex duplex;
282 enum ssp_clkdelay clkdelay;
283 void (*cs_control) (u32 control);
284 };
285
286 #endif /* _SSP_PL022_H */