root/include/linux/phy/omap_control_phy.h

INCLUDED FROM

DEFINITIONS

1. omap_control_phy_power
2. omap_control_usb_set_mode
3. omap_control_pcie_pcs

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * omap_control_phy.h - Header file for the PHY part of control module.
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7  */
   8 
   9 #ifndef __OMAP_CONTROL_PHY_H__
  10 #define __OMAP_CONTROL_PHY_H__
  11 
  12 enum omap_control_phy_type {
  13         OMAP_CTRL_TYPE_OTGHS = 1,       /* Mailbox OTGHS_CONTROL */
  14         OMAP_CTRL_TYPE_USB2,    /* USB2_PHY, power down in CONTROL_DEV_CONF */
  15         OMAP_CTRL_TYPE_PIPE3,   /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
  16         OMAP_CTRL_TYPE_PCIE,    /* RX TX control of ACSPCIE */
  17         OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
  18         OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
  19 };
  20 
  21 struct omap_control_phy {
  22         struct device *dev;
  23 
  24         u32 __iomem *otghs_control;
  25         u32 __iomem *power;
  26         u32 __iomem *power_aux;
  27         u32 __iomem *pcie_pcs;
  28 
  29         struct clk *sys_clk;
  30 
  31         enum omap_control_phy_type type;
  32 };
  33 
  34 enum omap_control_usb_mode {
  35         USB_MODE_UNDEFINED = 0,
  36         USB_MODE_HOST,
  37         USB_MODE_DEVICE,
  38         USB_MODE_DISCONNECT,
  39 };
  40 
  41 #define OMAP_CTRL_DEV_PHY_PD            BIT(0)
  42 
  43 #define OMAP_CTRL_DEV_AVALID            BIT(0)
  44 #define OMAP_CTRL_DEV_BVALID            BIT(1)
  45 #define OMAP_CTRL_DEV_VBUSVALID         BIT(2)
  46 #define OMAP_CTRL_DEV_SESSEND           BIT(3)
  47 #define OMAP_CTRL_DEV_IDDIG             BIT(4)
  48 
  49 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK         0x003FC000
  50 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT        0xE
  51 
  52 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK        0xFFC00000
  53 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT       0x16
  54 
  55 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON       0x3
  56 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF      0x0
  57 
  58 #define OMAP_CTRL_PCIE_PCS_MASK                 0xff
  59 #define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT    16
  60 
  61 #define OMAP_CTRL_USB2_PHY_PD           BIT(28)
  62 
  63 #define AM437X_CTRL_USB2_PHY_PD         BIT(0)
  64 #define AM437X_CTRL_USB2_OTG_PD         BIT(1)
  65 #define AM437X_CTRL_USB2_OTGVDET_EN     BIT(19)
  66 #define AM437X_CTRL_USB2_OTGSESSEND_EN  BIT(20)
  67 
  68 #if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
  69 void omap_control_phy_power(struct device *dev, int on);
  70 void omap_control_usb_set_mode(struct device *dev,
  71                                enum omap_control_usb_mode mode);
  72 void omap_control_pcie_pcs(struct device *dev, u8 delay);
  73 #else
  74 
  75 static inline void omap_control_phy_power(struct device *dev, int on)
  76 {
  77 }
  78 
  79 static inline void omap_control_usb_set_mode(struct device *dev,
  80         enum omap_control_usb_mode mode)
  81 {
  82 }
  83 
  84 static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
  85 {
  86 }
  87 #endif
  88 
  89 #endif  /* __OMAP_CONTROL_PHY_H__ */