root/include/linux/stmmac.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*******************************************************************************
   3 
   4   Header file for stmmac platform data
   5 
   6   Copyright (C) 2009  STMicroelectronics Ltd
   7 
   8 
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10 *******************************************************************************/
  11 
  12 #ifndef __STMMAC_PLATFORM_DATA
  13 #define __STMMAC_PLATFORM_DATA
  14 
  15 #include <linux/platform_device.h>
  16 
  17 #define MTL_MAX_RX_QUEUES       8
  18 #define MTL_MAX_TX_QUEUES       8
  19 #define STMMAC_CH_MAX           8
  20 
  21 #define STMMAC_RX_COE_NONE      0
  22 #define STMMAC_RX_COE_TYPE1     1
  23 #define STMMAC_RX_COE_TYPE2     2
  24 
  25 /* Define the macros for CSR clock range parameters to be passed by
  26  * platform code.
  27  * This could also be configured at run time using CPU freq framework. */
  28 
  29 /* MDC Clock Selection define*/
  30 #define STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
  31 #define STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
  32 #define STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
  33 #define STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
  34 #define STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
  35 #define STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/122 */
  36 
  37 /* MTL algorithms identifiers */
  38 #define MTL_TX_ALGORITHM_WRR    0x0
  39 #define MTL_TX_ALGORITHM_WFQ    0x1
  40 #define MTL_TX_ALGORITHM_DWRR   0x2
  41 #define MTL_TX_ALGORITHM_SP     0x3
  42 #define MTL_RX_ALGORITHM_SP     0x4
  43 #define MTL_RX_ALGORITHM_WSP    0x5
  44 
  45 /* RX/TX Queue Mode */
  46 #define MTL_QUEUE_AVB           0x0
  47 #define MTL_QUEUE_DCB           0x1
  48 
  49 /* The MDC clock could be set higher than the IEEE 802.3
  50  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  51  * of value different than the above defined values. The resultant MDIO
  52  * clock frequency of 12.5 MHz is applicable for the interfacing chips
  53  * supporting higher MDC clocks.
  54  * The MDC clock selection macros need to be defined for MDC clock rate
  55  * of 12.5 MHz, corresponding to the following selection.
  56  */
  57 #define STMMAC_CSR_I_4          0x8     /* clk_csr_i/4 */
  58 #define STMMAC_CSR_I_6          0x9     /* clk_csr_i/6 */
  59 #define STMMAC_CSR_I_8          0xA     /* clk_csr_i/8 */
  60 #define STMMAC_CSR_I_10         0xB     /* clk_csr_i/10 */
  61 #define STMMAC_CSR_I_12         0xC     /* clk_csr_i/12 */
  62 #define STMMAC_CSR_I_14         0xD     /* clk_csr_i/14 */
  63 #define STMMAC_CSR_I_16         0xE     /* clk_csr_i/16 */
  64 #define STMMAC_CSR_I_18         0xF     /* clk_csr_i/18 */
  65 
  66 /* AXI DMA Burst length supported */
  67 #define DMA_AXI_BLEN_4          (1 << 1)
  68 #define DMA_AXI_BLEN_8          (1 << 2)
  69 #define DMA_AXI_BLEN_16         (1 << 3)
  70 #define DMA_AXI_BLEN_32         (1 << 4)
  71 #define DMA_AXI_BLEN_64         (1 << 5)
  72 #define DMA_AXI_BLEN_128        (1 << 6)
  73 #define DMA_AXI_BLEN_256        (1 << 7)
  74 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
  75                         | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
  76                         | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
  77 
  78 /* Platfrom data for platform device structure's platform_data field */
  79 
  80 struct stmmac_mdio_bus_data {
  81         unsigned int phy_mask;
  82         int *irqs;
  83         int probed_phy_irq;
  84         bool needs_reset;
  85 };
  86 
  87 struct stmmac_dma_cfg {
  88         int pbl;
  89         int txpbl;
  90         int rxpbl;
  91         bool pblx8;
  92         int fixed_burst;
  93         int mixed_burst;
  94         bool aal;
  95 };
  96 
  97 #define AXI_BLEN        7
  98 struct stmmac_axi {
  99         bool axi_lpi_en;
 100         bool axi_xit_frm;
 101         u32 axi_wr_osr_lmt;
 102         u32 axi_rd_osr_lmt;
 103         bool axi_kbbe;
 104         u32 axi_blen[AXI_BLEN];
 105         bool axi_fb;
 106         bool axi_mb;
 107         bool axi_rb;
 108 };
 109 
 110 struct stmmac_rxq_cfg {
 111         u8 mode_to_use;
 112         u32 chan;
 113         u8 pkt_route;
 114         bool use_prio;
 115         u32 prio;
 116 };
 117 
 118 struct stmmac_txq_cfg {
 119         u32 weight;
 120         u8 mode_to_use;
 121         /* Credit Base Shaper parameters */
 122         u32 send_slope;
 123         u32 idle_slope;
 124         u32 high_credit;
 125         u32 low_credit;
 126         bool use_prio;
 127         u32 prio;
 128 };
 129 
 130 struct plat_stmmacenet_data {
 131         int bus_id;
 132         int phy_addr;
 133         int interface;
 134         int phy_interface;
 135         struct stmmac_mdio_bus_data *mdio_bus_data;
 136         struct device_node *phy_node;
 137         struct device_node *phylink_node;
 138         struct device_node *mdio_node;
 139         struct stmmac_dma_cfg *dma_cfg;
 140         int clk_csr;
 141         int has_gmac;
 142         int enh_desc;
 143         int tx_coe;
 144         int rx_coe;
 145         int bugged_jumbo;
 146         int pmt;
 147         int force_sf_dma_mode;
 148         int force_thresh_dma_mode;
 149         int riwt_off;
 150         int max_speed;
 151         int maxmtu;
 152         int multicast_filter_bins;
 153         int unicast_filter_entries;
 154         int tx_fifo_size;
 155         int rx_fifo_size;
 156         u32 rx_queues_to_use;
 157         u32 tx_queues_to_use;
 158         u8 rx_sched_algorithm;
 159         u8 tx_sched_algorithm;
 160         struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 161         struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 162         void (*fix_mac_speed)(void *priv, unsigned int speed);
 163         int (*init)(struct platform_device *pdev, void *priv);
 164         void (*exit)(struct platform_device *pdev, void *priv);
 165         struct mac_device_info *(*setup)(void *priv);
 166         void *bsp_priv;
 167         struct clk *stmmac_clk;
 168         struct clk *pclk;
 169         struct clk *clk_ptp_ref;
 170         unsigned int clk_ptp_rate;
 171         unsigned int clk_ref_rate;
 172         s32 ptp_max_adj;
 173         struct reset_control *stmmac_rst;
 174         struct stmmac_axi *axi;
 175         int has_gmac4;
 176         bool has_sun8i;
 177         bool tso_en;
 178         int rss_en;
 179         int mac_port_sel_speed;
 180         bool en_tx_lpi_clockgating;
 181         int has_xgmac;
 182 };
 183 #endif