root/include/linux/mlx5/accel.h

INCLUDED FROM

DEFINITIONS

1. mlx5_accel_ipsec_device_caps
2. mlx5_accel_esp_create_xfrm
3. mlx5_accel_esp_destroy_xfrm
4. mlx5_accel_esp_modify_xfrm

   1 /*
   2  * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33 
  34 #ifndef __MLX5_ACCEL_H__
  35 #define __MLX5_ACCEL_H__
  36 
  37 #include <linux/mlx5/driver.h>
  38 
  39 enum mlx5_accel_esp_aes_gcm_keymat_iv_algo {
  40         MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ,
  41 };
  42 
  43 enum mlx5_accel_esp_flags {
  44         MLX5_ACCEL_ESP_FLAGS_TUNNEL            = 0,    /* Default */
  45         MLX5_ACCEL_ESP_FLAGS_TRANSPORT         = 1UL << 0,
  46         MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED     = 1UL << 1,
  47         MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP = 1UL << 2,
  48 };
  49 
  50 enum mlx5_accel_esp_action {
  51         MLX5_ACCEL_ESP_ACTION_DECRYPT,
  52         MLX5_ACCEL_ESP_ACTION_ENCRYPT,
  53 };
  54 
  55 enum mlx5_accel_esp_keymats {
  56         MLX5_ACCEL_ESP_KEYMAT_AES_NONE,
  57         MLX5_ACCEL_ESP_KEYMAT_AES_GCM,
  58 };
  59 
  60 enum mlx5_accel_esp_replay {
  61         MLX5_ACCEL_ESP_REPLAY_NONE,
  62         MLX5_ACCEL_ESP_REPLAY_BMP,
  63 };
  64 
  65 struct aes_gcm_keymat {
  66         u64   seq_iv;
  67         enum mlx5_accel_esp_aes_gcm_keymat_iv_algo iv_algo;
  68 
  69         u32   salt;
  70         u32   icv_len;
  71 
  72         u32   key_len;
  73         u32   aes_key[256 / 32];
  74 };
  75 
  76 struct mlx5_accel_esp_xfrm_attrs {
  77         enum mlx5_accel_esp_action action;
  78         u32   esn;
  79         u32   spi;
  80         u32   seq;
  81         u32   tfc_pad;
  82         u32   flags;
  83         u32   sa_handle;
  84         enum mlx5_accel_esp_replay replay_type;
  85         union {
  86                 struct {
  87                         u32 size;
  88 
  89                 } bmp;
  90         } replay;
  91         enum mlx5_accel_esp_keymats keymat_type;
  92         union {
  93                 struct aes_gcm_keymat aes_gcm;
  94         } keymat;
  95 };
  96 
  97 struct mlx5_accel_esp_xfrm {
  98         struct mlx5_core_dev  *mdev;
  99         struct mlx5_accel_esp_xfrm_attrs attrs;
 100 };
 101 
 102 enum {
 103         MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA = 1UL << 0,
 104 };
 105 
 106 enum mlx5_accel_ipsec_cap {
 107         MLX5_ACCEL_IPSEC_CAP_DEVICE             = 1 << 0,
 108         MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA  = 1 << 1,
 109         MLX5_ACCEL_IPSEC_CAP_ESP                = 1 << 2,
 110         MLX5_ACCEL_IPSEC_CAP_IPV6               = 1 << 3,
 111         MLX5_ACCEL_IPSEC_CAP_LSO                = 1 << 4,
 112         MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER      = 1 << 5,
 113         MLX5_ACCEL_IPSEC_CAP_ESN                = 1 << 6,
 114         MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN       = 1 << 7,
 115 };
 116 
 117 #ifdef CONFIG_MLX5_FPGA_IPSEC
 118 
 119 u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
 120 
 121 struct mlx5_accel_esp_xfrm *
 122 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
 123                            const struct mlx5_accel_esp_xfrm_attrs *attrs,
 124                            u32 flags);
 125 void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm);
 126 int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
 127                                const struct mlx5_accel_esp_xfrm_attrs *attrs);
 128 
 129 #else
 130 
 131 static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
 132 
 133 static inline struct mlx5_accel_esp_xfrm *
 134 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
 135                            const struct mlx5_accel_esp_xfrm_attrs *attrs,
 136                            u32 flags) { return ERR_PTR(-EOPNOTSUPP); }
 137 static inline void
 138 mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) {}
 139 static inline int
 140 mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
 141                            const struct mlx5_accel_esp_xfrm_attrs *attrs) { return -EOPNOTSUPP; }
 142 
 143 #endif
 144 #endif