root/include/linux/mlx5/mlx5_ifc.h

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   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34 
  35 #include "mlx5_ifc_fpga.h"
  36 
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65 
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72 
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78 
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82 
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86 
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90 };
  91 
  92 enum {
  93         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  94         MLX5_OBJ_TYPE_MKEY = 0xff01,
  95         MLX5_OBJ_TYPE_QP = 0xff02,
  96         MLX5_OBJ_TYPE_PSV = 0xff03,
  97         MLX5_OBJ_TYPE_RMP = 0xff04,
  98         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  99         MLX5_OBJ_TYPE_RQ = 0xff06,
 100         MLX5_OBJ_TYPE_SQ = 0xff07,
 101         MLX5_OBJ_TYPE_TIR = 0xff08,
 102         MLX5_OBJ_TYPE_TIS = 0xff09,
 103         MLX5_OBJ_TYPE_DCT = 0xff0a,
 104         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 105         MLX5_OBJ_TYPE_RQT = 0xff0e,
 106         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 107         MLX5_OBJ_TYPE_CQ = 0xff10,
 108 };
 109 
 110 enum {
 111         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 112         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 113         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 114         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 115         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 116         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 117         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 118         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 119         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 120         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 121         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 122         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 123         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 124         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 125         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 126         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 127         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 128         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 129         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 130         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 131         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 132         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 133         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 134         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 135         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 136         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 137         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 138         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 139         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 140         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 141         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 142         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 143         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 144         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 145         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 146         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 147         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 148         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 149         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 150         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 151         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 152         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 153         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 154         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 155         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 156         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 157         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 158         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 159         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 160         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 161         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 162         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 163         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 164         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 165         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 166         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 167         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 168         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 169         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 170         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 171         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 172         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 173         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 174         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 175         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 176         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 177         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 178         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 179         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 180         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 181         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 182         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 183         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 184         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 185         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 186         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 187         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 188         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 189         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 190         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 191         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 192         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 193         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 194         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 195         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 196         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 197         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 198         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 199         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 200         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 201         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 202         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 203         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 204         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 205         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 206         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 207         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 208         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 209         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 210         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 211         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 212         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 213         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 214         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 215         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 216         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 217         MLX5_CMD_OP_NOP                           = 0x80d,
 218         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 219         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 220         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 221         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 222         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 223         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 224         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 225         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 226         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 227         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 228         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 229         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 230         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 231         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 232         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 233         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 234         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 235         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 236         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 237         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 238         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 239         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 240         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 241         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 242         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 243         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 244         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 245         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 246         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 247         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 248         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 249         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 250         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 251         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 252         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 253         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 254         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 255         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 256         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 257         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 258         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 259         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 260         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 261         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 262         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 263         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 264         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 265         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 266         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 267         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 268         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 269         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 270         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 271         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 272         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 273         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 274         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 275         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 276         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 277         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 278         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 279         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 280         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 281         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 282         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 283         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 284         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 285         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 286         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 287         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 288         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 289         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 290         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 291         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 292         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 293         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 294         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 295         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 296         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 297         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 298         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 299         MLX5_CMD_OP_MAX
 300 };
 301 
 302 /* Valid range for general commands that don't work over an object */
 303 enum {
 304         MLX5_CMD_OP_GENERAL_START = 0xb00,
 305         MLX5_CMD_OP_GENERAL_END = 0xd00,
 306 };
 307 
 308 struct mlx5_ifc_flow_table_fields_supported_bits {
 309         u8         outer_dmac[0x1];
 310         u8         outer_smac[0x1];
 311         u8         outer_ether_type[0x1];
 312         u8         outer_ip_version[0x1];
 313         u8         outer_first_prio[0x1];
 314         u8         outer_first_cfi[0x1];
 315         u8         outer_first_vid[0x1];
 316         u8         outer_ipv4_ttl[0x1];
 317         u8         outer_second_prio[0x1];
 318         u8         outer_second_cfi[0x1];
 319         u8         outer_second_vid[0x1];
 320         u8         reserved_at_b[0x1];
 321         u8         outer_sip[0x1];
 322         u8         outer_dip[0x1];
 323         u8         outer_frag[0x1];
 324         u8         outer_ip_protocol[0x1];
 325         u8         outer_ip_ecn[0x1];
 326         u8         outer_ip_dscp[0x1];
 327         u8         outer_udp_sport[0x1];
 328         u8         outer_udp_dport[0x1];
 329         u8         outer_tcp_sport[0x1];
 330         u8         outer_tcp_dport[0x1];
 331         u8         outer_tcp_flags[0x1];
 332         u8         outer_gre_protocol[0x1];
 333         u8         outer_gre_key[0x1];
 334         u8         outer_vxlan_vni[0x1];
 335         u8         outer_geneve_vni[0x1];
 336         u8         outer_geneve_oam[0x1];
 337         u8         outer_geneve_protocol_type[0x1];
 338         u8         outer_geneve_opt_len[0x1];
 339         u8         reserved_at_1e[0x1];
 340         u8         source_eswitch_port[0x1];
 341 
 342         u8         inner_dmac[0x1];
 343         u8         inner_smac[0x1];
 344         u8         inner_ether_type[0x1];
 345         u8         inner_ip_version[0x1];
 346         u8         inner_first_prio[0x1];
 347         u8         inner_first_cfi[0x1];
 348         u8         inner_first_vid[0x1];
 349         u8         reserved_at_27[0x1];
 350         u8         inner_second_prio[0x1];
 351         u8         inner_second_cfi[0x1];
 352         u8         inner_second_vid[0x1];
 353         u8         reserved_at_2b[0x1];
 354         u8         inner_sip[0x1];
 355         u8         inner_dip[0x1];
 356         u8         inner_frag[0x1];
 357         u8         inner_ip_protocol[0x1];
 358         u8         inner_ip_ecn[0x1];
 359         u8         inner_ip_dscp[0x1];
 360         u8         inner_udp_sport[0x1];
 361         u8         inner_udp_dport[0x1];
 362         u8         inner_tcp_sport[0x1];
 363         u8         inner_tcp_dport[0x1];
 364         u8         inner_tcp_flags[0x1];
 365         u8         reserved_at_37[0x9];
 366 
 367         u8         geneve_tlv_option_0_data[0x1];
 368         u8         reserved_at_41[0x4];
 369         u8         outer_first_mpls_over_udp[0x4];
 370         u8         outer_first_mpls_over_gre[0x4];
 371         u8         inner_first_mpls[0x4];
 372         u8         outer_first_mpls[0x4];
 373         u8         reserved_at_55[0x2];
 374         u8         outer_esp_spi[0x1];
 375         u8         reserved_at_58[0x2];
 376         u8         bth_dst_qp[0x1];
 377 
 378         u8         reserved_at_5b[0x25];
 379 };
 380 
 381 struct mlx5_ifc_flow_table_prop_layout_bits {
 382         u8         ft_support[0x1];
 383         u8         reserved_at_1[0x1];
 384         u8         flow_counter[0x1];
 385         u8         flow_modify_en[0x1];
 386         u8         modify_root[0x1];
 387         u8         identified_miss_table_mode[0x1];
 388         u8         flow_table_modify[0x1];
 389         u8         reformat[0x1];
 390         u8         decap[0x1];
 391         u8         reserved_at_9[0x1];
 392         u8         pop_vlan[0x1];
 393         u8         push_vlan[0x1];
 394         u8         reserved_at_c[0x1];
 395         u8         pop_vlan_2[0x1];
 396         u8         push_vlan_2[0x1];
 397         u8         reformat_and_vlan_action[0x1];
 398         u8         reserved_at_10[0x1];
 399         u8         sw_owner[0x1];
 400         u8         reformat_l3_tunnel_to_l2[0x1];
 401         u8         reformat_l2_to_l3_tunnel[0x1];
 402         u8         reformat_and_modify_action[0x1];
 403         u8         reserved_at_15[0x2];
 404         u8         table_miss_action_domain[0x1];
 405         u8         termination_table[0x1];
 406         u8         reserved_at_19[0x7];
 407         u8         reserved_at_20[0x2];
 408         u8         log_max_ft_size[0x6];
 409         u8         log_max_modify_header_context[0x8];
 410         u8         max_modify_header_actions[0x8];
 411         u8         max_ft_level[0x8];
 412 
 413         u8         reserved_at_40[0x20];
 414 
 415         u8         reserved_at_60[0x18];
 416         u8         log_max_ft_num[0x8];
 417 
 418         u8         reserved_at_80[0x18];
 419         u8         log_max_destination[0x8];
 420 
 421         u8         log_max_flow_counter[0x8];
 422         u8         reserved_at_a8[0x10];
 423         u8         log_max_flow[0x8];
 424 
 425         u8         reserved_at_c0[0x40];
 426 
 427         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 428 
 429         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 430 };
 431 
 432 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 433         u8         send[0x1];
 434         u8         receive[0x1];
 435         u8         write[0x1];
 436         u8         read[0x1];
 437         u8         atomic[0x1];
 438         u8         srq_receive[0x1];
 439         u8         reserved_at_6[0x1a];
 440 };
 441 
 442 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 443         u8         smac_47_16[0x20];
 444 
 445         u8         smac_15_0[0x10];
 446         u8         ethertype[0x10];
 447 
 448         u8         dmac_47_16[0x20];
 449 
 450         u8         dmac_15_0[0x10];
 451         u8         first_prio[0x3];
 452         u8         first_cfi[0x1];
 453         u8         first_vid[0xc];
 454 
 455         u8         ip_protocol[0x8];
 456         u8         ip_dscp[0x6];
 457         u8         ip_ecn[0x2];
 458         u8         cvlan_tag[0x1];
 459         u8         svlan_tag[0x1];
 460         u8         frag[0x1];
 461         u8         ip_version[0x4];
 462         u8         tcp_flags[0x9];
 463 
 464         u8         tcp_sport[0x10];
 465         u8         tcp_dport[0x10];
 466 
 467         u8         reserved_at_c0[0x18];
 468         u8         ttl_hoplimit[0x8];
 469 
 470         u8         udp_sport[0x10];
 471         u8         udp_dport[0x10];
 472 
 473         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 474 
 475         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 476 };
 477 
 478 struct mlx5_ifc_nvgre_key_bits {
 479         u8 hi[0x18];
 480         u8 lo[0x8];
 481 };
 482 
 483 union mlx5_ifc_gre_key_bits {
 484         struct mlx5_ifc_nvgre_key_bits nvgre;
 485         u8 key[0x20];
 486 };
 487 
 488 struct mlx5_ifc_fte_match_set_misc_bits {
 489         u8         gre_c_present[0x1];
 490         u8         reserved_at_1[0x1];
 491         u8         gre_k_present[0x1];
 492         u8         gre_s_present[0x1];
 493         u8         source_vhca_port[0x4];
 494         u8         source_sqn[0x18];
 495 
 496         u8         source_eswitch_owner_vhca_id[0x10];
 497         u8         source_port[0x10];
 498 
 499         u8         outer_second_prio[0x3];
 500         u8         outer_second_cfi[0x1];
 501         u8         outer_second_vid[0xc];
 502         u8         inner_second_prio[0x3];
 503         u8         inner_second_cfi[0x1];
 504         u8         inner_second_vid[0xc];
 505 
 506         u8         outer_second_cvlan_tag[0x1];
 507         u8         inner_second_cvlan_tag[0x1];
 508         u8         outer_second_svlan_tag[0x1];
 509         u8         inner_second_svlan_tag[0x1];
 510         u8         reserved_at_64[0xc];
 511         u8         gre_protocol[0x10];
 512 
 513         union mlx5_ifc_gre_key_bits gre_key;
 514 
 515         u8         vxlan_vni[0x18];
 516         u8         reserved_at_b8[0x8];
 517 
 518         u8         geneve_vni[0x18];
 519         u8         reserved_at_d8[0x7];
 520         u8         geneve_oam[0x1];
 521 
 522         u8         reserved_at_e0[0xc];
 523         u8         outer_ipv6_flow_label[0x14];
 524 
 525         u8         reserved_at_100[0xc];
 526         u8         inner_ipv6_flow_label[0x14];
 527 
 528         u8         reserved_at_120[0xa];
 529         u8         geneve_opt_len[0x6];
 530         u8         geneve_protocol_type[0x10];
 531 
 532         u8         reserved_at_140[0x8];
 533         u8         bth_dst_qp[0x18];
 534         u8         reserved_at_160[0x20];
 535         u8         outer_esp_spi[0x20];
 536         u8         reserved_at_1a0[0x60];
 537 };
 538 
 539 struct mlx5_ifc_fte_match_mpls_bits {
 540         u8         mpls_label[0x14];
 541         u8         mpls_exp[0x3];
 542         u8         mpls_s_bos[0x1];
 543         u8         mpls_ttl[0x8];
 544 };
 545 
 546 struct mlx5_ifc_fte_match_set_misc2_bits {
 547         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 548 
 549         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 550 
 551         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 552 
 553         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 554 
 555         u8         metadata_reg_c_7[0x20];
 556 
 557         u8         metadata_reg_c_6[0x20];
 558 
 559         u8         metadata_reg_c_5[0x20];
 560 
 561         u8         metadata_reg_c_4[0x20];
 562 
 563         u8         metadata_reg_c_3[0x20];
 564 
 565         u8         metadata_reg_c_2[0x20];
 566 
 567         u8         metadata_reg_c_1[0x20];
 568 
 569         u8         metadata_reg_c_0[0x20];
 570 
 571         u8         metadata_reg_a[0x20];
 572 
 573         u8         metadata_reg_b[0x20];
 574 
 575         u8         reserved_at_1c0[0x40];
 576 };
 577 
 578 struct mlx5_ifc_fte_match_set_misc3_bits {
 579         u8         inner_tcp_seq_num[0x20];
 580 
 581         u8         outer_tcp_seq_num[0x20];
 582 
 583         u8         inner_tcp_ack_num[0x20];
 584 
 585         u8         outer_tcp_ack_num[0x20];
 586 
 587         u8         reserved_at_80[0x8];
 588         u8         outer_vxlan_gpe_vni[0x18];
 589 
 590         u8         outer_vxlan_gpe_next_protocol[0x8];
 591         u8         outer_vxlan_gpe_flags[0x8];
 592         u8         reserved_at_b0[0x10];
 593 
 594         u8         icmp_header_data[0x20];
 595 
 596         u8         icmpv6_header_data[0x20];
 597 
 598         u8         icmp_type[0x8];
 599         u8         icmp_code[0x8];
 600         u8         icmpv6_type[0x8];
 601         u8         icmpv6_code[0x8];
 602 
 603         u8         geneve_tlv_option_0_data[0x20];
 604 
 605         u8         reserved_at_140[0xc0];
 606 };
 607 
 608 struct mlx5_ifc_cmd_pas_bits {
 609         u8         pa_h[0x20];
 610 
 611         u8         pa_l[0x14];
 612         u8         reserved_at_34[0xc];
 613 };
 614 
 615 struct mlx5_ifc_uint64_bits {
 616         u8         hi[0x20];
 617 
 618         u8         lo[0x20];
 619 };
 620 
 621 enum {
 622         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 623         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 624         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 625         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 626         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 627         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 628         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 629         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 630         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 631         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 632 };
 633 
 634 struct mlx5_ifc_ads_bits {
 635         u8         fl[0x1];
 636         u8         free_ar[0x1];
 637         u8         reserved_at_2[0xe];
 638         u8         pkey_index[0x10];
 639 
 640         u8         reserved_at_20[0x8];
 641         u8         grh[0x1];
 642         u8         mlid[0x7];
 643         u8         rlid[0x10];
 644 
 645         u8         ack_timeout[0x5];
 646         u8         reserved_at_45[0x3];
 647         u8         src_addr_index[0x8];
 648         u8         reserved_at_50[0x4];
 649         u8         stat_rate[0x4];
 650         u8         hop_limit[0x8];
 651 
 652         u8         reserved_at_60[0x4];
 653         u8         tclass[0x8];
 654         u8         flow_label[0x14];
 655 
 656         u8         rgid_rip[16][0x8];
 657 
 658         u8         reserved_at_100[0x4];
 659         u8         f_dscp[0x1];
 660         u8         f_ecn[0x1];
 661         u8         reserved_at_106[0x1];
 662         u8         f_eth_prio[0x1];
 663         u8         ecn[0x2];
 664         u8         dscp[0x6];
 665         u8         udp_sport[0x10];
 666 
 667         u8         dei_cfi[0x1];
 668         u8         eth_prio[0x3];
 669         u8         sl[0x4];
 670         u8         vhca_port_num[0x8];
 671         u8         rmac_47_32[0x10];
 672 
 673         u8         rmac_31_0[0x20];
 674 };
 675 
 676 struct mlx5_ifc_flow_table_nic_cap_bits {
 677         u8         nic_rx_multi_path_tirs[0x1];
 678         u8         nic_rx_multi_path_tirs_fts[0x1];
 679         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 680         u8         reserved_at_3[0x1d];
 681         u8         encap_general_header[0x1];
 682         u8         reserved_at_21[0xa];
 683         u8         log_max_packet_reformat_context[0x5];
 684         u8         reserved_at_30[0x6];
 685         u8         max_encap_header_size[0xa];
 686         u8         reserved_at_40[0x1c0];
 687 
 688         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 689 
 690         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 691 
 692         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 693 
 694         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 695 
 696         u8         reserved_at_a00[0x200];
 697 
 698         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 699 
 700         u8         reserved_at_e00[0x1200];
 701 
 702         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 703 
 704         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 705 
 706         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 707 
 708         u8         reserved_at_20c0[0x5f40];
 709 };
 710 
 711 enum {
 712         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 713         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 714         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 715         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 716         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 717         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 718         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 719         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 720 };
 721 
 722 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 723         u8      fdb_to_vport_reg_c_id[0x8];
 724         u8      reserved_at_8[0xf];
 725         u8      flow_source[0x1];
 726         u8      reserved_at_18[0x2];
 727         u8      multi_fdb_encap[0x1];
 728         u8      reserved_at_1b[0x1];
 729         u8      fdb_multi_path_to_table[0x1];
 730         u8      reserved_at_1d[0x3];
 731 
 732         u8      reserved_at_20[0x1e0];
 733 
 734         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 735 
 736         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 737 
 738         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 739 
 740         u8      reserved_at_800[0x1000];
 741 
 742         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 743 
 744         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 745 
 746         u8      sw_steering_uplink_icm_address_rx[0x40];
 747 
 748         u8      sw_steering_uplink_icm_address_tx[0x40];
 749 
 750         u8      reserved_at_1900[0x6700];
 751 };
 752 
 753 enum {
 754         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 755         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 756 };
 757 
 758 struct mlx5_ifc_e_switch_cap_bits {
 759         u8         vport_svlan_strip[0x1];
 760         u8         vport_cvlan_strip[0x1];
 761         u8         vport_svlan_insert[0x1];
 762         u8         vport_cvlan_insert_if_not_exist[0x1];
 763         u8         vport_cvlan_insert_overwrite[0x1];
 764         u8         reserved_at_5[0x3];
 765         u8         esw_uplink_ingress_acl[0x1];
 766         u8         reserved_at_9[0x10];
 767         u8         esw_functions_changed[0x1];
 768         u8         reserved_at_1a[0x1];
 769         u8         ecpf_vport_exists[0x1];
 770         u8         counter_eswitch_affinity[0x1];
 771         u8         merged_eswitch[0x1];
 772         u8         nic_vport_node_guid_modify[0x1];
 773         u8         nic_vport_port_guid_modify[0x1];
 774 
 775         u8         vxlan_encap_decap[0x1];
 776         u8         nvgre_encap_decap[0x1];
 777         u8         reserved_at_22[0x1];
 778         u8         log_max_fdb_encap_uplink[0x5];
 779         u8         reserved_at_21[0x3];
 780         u8         log_max_packet_reformat_context[0x5];
 781         u8         reserved_2b[0x6];
 782         u8         max_encap_header_size[0xa];
 783 
 784         u8         reserved_at_40[0xb];
 785         u8         log_max_esw_sf[0x5];
 786         u8         esw_sf_base_id[0x10];
 787 
 788         u8         reserved_at_60[0x7a0];
 789 
 790 };
 791 
 792 struct mlx5_ifc_qos_cap_bits {
 793         u8         packet_pacing[0x1];
 794         u8         esw_scheduling[0x1];
 795         u8         esw_bw_share[0x1];
 796         u8         esw_rate_limit[0x1];
 797         u8         reserved_at_4[0x1];
 798         u8         packet_pacing_burst_bound[0x1];
 799         u8         packet_pacing_typical_size[0x1];
 800         u8         reserved_at_7[0x19];
 801 
 802         u8         reserved_at_20[0x20];
 803 
 804         u8         packet_pacing_max_rate[0x20];
 805 
 806         u8         packet_pacing_min_rate[0x20];
 807 
 808         u8         reserved_at_80[0x10];
 809         u8         packet_pacing_rate_table_size[0x10];
 810 
 811         u8         esw_element_type[0x10];
 812         u8         esw_tsar_type[0x10];
 813 
 814         u8         reserved_at_c0[0x10];
 815         u8         max_qos_para_vport[0x10];
 816 
 817         u8         max_tsar_bw_share[0x20];
 818 
 819         u8         reserved_at_100[0x700];
 820 };
 821 
 822 struct mlx5_ifc_debug_cap_bits {
 823         u8         core_dump_general[0x1];
 824         u8         core_dump_qp[0x1];
 825         u8         reserved_at_2[0x1e];
 826 
 827         u8         reserved_at_20[0x2];
 828         u8         stall_detect[0x1];
 829         u8         reserved_at_23[0x1d];
 830 
 831         u8         reserved_at_40[0x7c0];
 832 };
 833 
 834 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 835         u8         csum_cap[0x1];
 836         u8         vlan_cap[0x1];
 837         u8         lro_cap[0x1];
 838         u8         lro_psh_flag[0x1];
 839         u8         lro_time_stamp[0x1];
 840         u8         reserved_at_5[0x2];
 841         u8         wqe_vlan_insert[0x1];
 842         u8         self_lb_en_modifiable[0x1];
 843         u8         reserved_at_9[0x2];
 844         u8         max_lso_cap[0x5];
 845         u8         multi_pkt_send_wqe[0x2];
 846         u8         wqe_inline_mode[0x2];
 847         u8         rss_ind_tbl_cap[0x4];
 848         u8         reg_umr_sq[0x1];
 849         u8         scatter_fcs[0x1];
 850         u8         enhanced_multi_pkt_send_wqe[0x1];
 851         u8         tunnel_lso_const_out_ip_id[0x1];
 852         u8         reserved_at_1c[0x2];
 853         u8         tunnel_stateless_gre[0x1];
 854         u8         tunnel_stateless_vxlan[0x1];
 855 
 856         u8         swp[0x1];
 857         u8         swp_csum[0x1];
 858         u8         swp_lso[0x1];
 859         u8         cqe_checksum_full[0x1];
 860         u8         tunnel_stateless_geneve_tx[0x1];
 861         u8         tunnel_stateless_mpls_over_udp[0x1];
 862         u8         tunnel_stateless_mpls_over_gre[0x1];
 863         u8         tunnel_stateless_vxlan_gpe[0x1];
 864         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 865         u8         tunnel_stateless_ip_over_ip[0x1];
 866         u8         reserved_at_2a[0x6];
 867         u8         max_vxlan_udp_ports[0x8];
 868         u8         reserved_at_38[0x6];
 869         u8         max_geneve_opt_len[0x1];
 870         u8         tunnel_stateless_geneve_rx[0x1];
 871 
 872         u8         reserved_at_40[0x10];
 873         u8         lro_min_mss_size[0x10];
 874 
 875         u8         reserved_at_60[0x120];
 876 
 877         u8         lro_timer_supported_periods[4][0x20];
 878 
 879         u8         reserved_at_200[0x600];
 880 };
 881 
 882 struct mlx5_ifc_roce_cap_bits {
 883         u8         roce_apm[0x1];
 884         u8         reserved_at_1[0x1f];
 885 
 886         u8         reserved_at_20[0x60];
 887 
 888         u8         reserved_at_80[0xc];
 889         u8         l3_type[0x4];
 890         u8         reserved_at_90[0x8];
 891         u8         roce_version[0x8];
 892 
 893         u8         reserved_at_a0[0x10];
 894         u8         r_roce_dest_udp_port[0x10];
 895 
 896         u8         r_roce_max_src_udp_port[0x10];
 897         u8         r_roce_min_src_udp_port[0x10];
 898 
 899         u8         reserved_at_e0[0x10];
 900         u8         roce_address_table_size[0x10];
 901 
 902         u8         reserved_at_100[0x700];
 903 };
 904 
 905 struct mlx5_ifc_sync_steering_in_bits {
 906         u8         opcode[0x10];
 907         u8         uid[0x10];
 908 
 909         u8         reserved_at_20[0x10];
 910         u8         op_mod[0x10];
 911 
 912         u8         reserved_at_40[0xc0];
 913 };
 914 
 915 struct mlx5_ifc_sync_steering_out_bits {
 916         u8         status[0x8];
 917         u8         reserved_at_8[0x18];
 918 
 919         u8         syndrome[0x20];
 920 
 921         u8         reserved_at_40[0x40];
 922 };
 923 
 924 struct mlx5_ifc_device_mem_cap_bits {
 925         u8         memic[0x1];
 926         u8         reserved_at_1[0x1f];
 927 
 928         u8         reserved_at_20[0xb];
 929         u8         log_min_memic_alloc_size[0x5];
 930         u8         reserved_at_30[0x8];
 931         u8         log_max_memic_addr_alignment[0x8];
 932 
 933         u8         memic_bar_start_addr[0x40];
 934 
 935         u8         memic_bar_size[0x20];
 936 
 937         u8         max_memic_size[0x20];
 938 
 939         u8         steering_sw_icm_start_address[0x40];
 940 
 941         u8         reserved_at_100[0x8];
 942         u8         log_header_modify_sw_icm_size[0x8];
 943         u8         reserved_at_110[0x2];
 944         u8         log_sw_icm_alloc_granularity[0x6];
 945         u8         log_steering_sw_icm_size[0x8];
 946 
 947         u8         reserved_at_120[0x20];
 948 
 949         u8         header_modify_sw_icm_start_address[0x40];
 950 
 951         u8         reserved_at_180[0x680];
 952 };
 953 
 954 struct mlx5_ifc_device_event_cap_bits {
 955         u8         user_affiliated_events[4][0x40];
 956 
 957         u8         user_unaffiliated_events[4][0x40];
 958 };
 959 
 960 enum {
 961         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 962         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 963         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 964         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 965         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 966         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 967         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 968         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 969         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 970 };
 971 
 972 enum {
 973         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 974         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 975         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 976         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 977         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 978         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 979         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 980         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 981         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 982 };
 983 
 984 struct mlx5_ifc_atomic_caps_bits {
 985         u8         reserved_at_0[0x40];
 986 
 987         u8         atomic_req_8B_endianness_mode[0x2];
 988         u8         reserved_at_42[0x4];
 989         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 990 
 991         u8         reserved_at_47[0x19];
 992 
 993         u8         reserved_at_60[0x20];
 994 
 995         u8         reserved_at_80[0x10];
 996         u8         atomic_operations[0x10];
 997 
 998         u8         reserved_at_a0[0x10];
 999         u8         atomic_size_qp[0x10];
1000 
1001         u8         reserved_at_c0[0x10];
1002         u8         atomic_size_dc[0x10];
1003 
1004         u8         reserved_at_e0[0x720];
1005 };
1006 
1007 struct mlx5_ifc_odp_cap_bits {
1008         u8         reserved_at_0[0x40];
1009 
1010         u8         sig[0x1];
1011         u8         reserved_at_41[0x1f];
1012 
1013         u8         reserved_at_60[0x20];
1014 
1015         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1016 
1017         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1018 
1019         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1020 
1021         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1022 
1023         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1024 
1025         u8         reserved_at_120[0x6E0];
1026 };
1027 
1028 struct mlx5_ifc_calc_op {
1029         u8        reserved_at_0[0x10];
1030         u8        reserved_at_10[0x9];
1031         u8        op_swap_endianness[0x1];
1032         u8        op_min[0x1];
1033         u8        op_xor[0x1];
1034         u8        op_or[0x1];
1035         u8        op_and[0x1];
1036         u8        op_max[0x1];
1037         u8        op_add[0x1];
1038 };
1039 
1040 struct mlx5_ifc_vector_calc_cap_bits {
1041         u8         calc_matrix[0x1];
1042         u8         reserved_at_1[0x1f];
1043         u8         reserved_at_20[0x8];
1044         u8         max_vec_count[0x8];
1045         u8         reserved_at_30[0xd];
1046         u8         max_chunk_size[0x3];
1047         struct mlx5_ifc_calc_op calc0;
1048         struct mlx5_ifc_calc_op calc1;
1049         struct mlx5_ifc_calc_op calc2;
1050         struct mlx5_ifc_calc_op calc3;
1051 
1052         u8         reserved_at_c0[0x720];
1053 };
1054 
1055 struct mlx5_ifc_tls_cap_bits {
1056         u8         tls_1_2_aes_gcm_128[0x1];
1057         u8         tls_1_3_aes_gcm_128[0x1];
1058         u8         tls_1_2_aes_gcm_256[0x1];
1059         u8         tls_1_3_aes_gcm_256[0x1];
1060         u8         reserved_at_4[0x1c];
1061 
1062         u8         reserved_at_20[0x7e0];
1063 };
1064 
1065 enum {
1066         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1067         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1068         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1069         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1070 };
1071 
1072 enum {
1073         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1074         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1075 };
1076 
1077 enum {
1078         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1079         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1080         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1081         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1082         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1083 };
1084 
1085 enum {
1086         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1087         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1088         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1089         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1090         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1091         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1092 };
1093 
1094 enum {
1095         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1096         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1097 };
1098 
1099 enum {
1100         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1101         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1102         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1103 };
1104 
1105 enum {
1106         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1107         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1108 };
1109 
1110 enum {
1111         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1112         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1113         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1114 };
1115 
1116 enum {
1117         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1118         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1119         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1120 };
1121 
1122 enum {
1123         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1124         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1125 };
1126 
1127 #define MLX5_FC_BULK_SIZE_FACTOR 128
1128 
1129 enum mlx5_fc_bulk_alloc_bitmask {
1130         MLX5_FC_BULK_128   = (1 << 0),
1131         MLX5_FC_BULK_256   = (1 << 1),
1132         MLX5_FC_BULK_512   = (1 << 2),
1133         MLX5_FC_BULK_1024  = (1 << 3),
1134         MLX5_FC_BULK_2048  = (1 << 4),
1135         MLX5_FC_BULK_4096  = (1 << 5),
1136         MLX5_FC_BULK_8192  = (1 << 6),
1137         MLX5_FC_BULK_16384 = (1 << 7),
1138 };
1139 
1140 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1141 
1142 struct mlx5_ifc_cmd_hca_cap_bits {
1143         u8         reserved_at_0[0x30];
1144         u8         vhca_id[0x10];
1145 
1146         u8         reserved_at_40[0x40];
1147 
1148         u8         log_max_srq_sz[0x8];
1149         u8         log_max_qp_sz[0x8];
1150         u8         event_cap[0x1];
1151         u8         reserved_at_91[0x7];
1152         u8         prio_tag_required[0x1];
1153         u8         reserved_at_99[0x2];
1154         u8         log_max_qp[0x5];
1155 
1156         u8         reserved_at_a0[0xb];
1157         u8         log_max_srq[0x5];
1158         u8         reserved_at_b0[0x10];
1159 
1160         u8         reserved_at_c0[0x8];
1161         u8         log_max_cq_sz[0x8];
1162         u8         reserved_at_d0[0xb];
1163         u8         log_max_cq[0x5];
1164 
1165         u8         log_max_eq_sz[0x8];
1166         u8         reserved_at_e8[0x2];
1167         u8         log_max_mkey[0x6];
1168         u8         reserved_at_f0[0x8];
1169         u8         dump_fill_mkey[0x1];
1170         u8         reserved_at_f9[0x2];
1171         u8         fast_teardown[0x1];
1172         u8         log_max_eq[0x4];
1173 
1174         u8         max_indirection[0x8];
1175         u8         fixed_buffer_size[0x1];
1176         u8         log_max_mrw_sz[0x7];
1177         u8         force_teardown[0x1];
1178         u8         reserved_at_111[0x1];
1179         u8         log_max_bsf_list_size[0x6];
1180         u8         umr_extended_translation_offset[0x1];
1181         u8         null_mkey[0x1];
1182         u8         log_max_klm_list_size[0x6];
1183 
1184         u8         reserved_at_120[0xa];
1185         u8         log_max_ra_req_dc[0x6];
1186         u8         reserved_at_130[0xa];
1187         u8         log_max_ra_res_dc[0x6];
1188 
1189         u8         reserved_at_140[0xa];
1190         u8         log_max_ra_req_qp[0x6];
1191         u8         reserved_at_150[0xa];
1192         u8         log_max_ra_res_qp[0x6];
1193 
1194         u8         end_pad[0x1];
1195         u8         cc_query_allowed[0x1];
1196         u8         cc_modify_allowed[0x1];
1197         u8         start_pad[0x1];
1198         u8         cache_line_128byte[0x1];
1199         u8         reserved_at_165[0x4];
1200         u8         rts2rts_qp_counters_set_id[0x1];
1201         u8         reserved_at_16a[0x2];
1202         u8         vnic_env_int_rq_oob[0x1];
1203         u8         sbcam_reg[0x1];
1204         u8         reserved_at_16e[0x1];
1205         u8         qcam_reg[0x1];
1206         u8         gid_table_size[0x10];
1207 
1208         u8         out_of_seq_cnt[0x1];
1209         u8         vport_counters[0x1];
1210         u8         retransmission_q_counters[0x1];
1211         u8         debug[0x1];
1212         u8         modify_rq_counter_set_id[0x1];
1213         u8         rq_delay_drop[0x1];
1214         u8         max_qp_cnt[0xa];
1215         u8         pkey_table_size[0x10];
1216 
1217         u8         vport_group_manager[0x1];
1218         u8         vhca_group_manager[0x1];
1219         u8         ib_virt[0x1];
1220         u8         eth_virt[0x1];
1221         u8         vnic_env_queue_counters[0x1];
1222         u8         ets[0x1];
1223         u8         nic_flow_table[0x1];
1224         u8         eswitch_manager[0x1];
1225         u8         device_memory[0x1];
1226         u8         mcam_reg[0x1];
1227         u8         pcam_reg[0x1];
1228         u8         local_ca_ack_delay[0x5];
1229         u8         port_module_event[0x1];
1230         u8         enhanced_error_q_counters[0x1];
1231         u8         ports_check[0x1];
1232         u8         reserved_at_1b3[0x1];
1233         u8         disable_link_up[0x1];
1234         u8         beacon_led[0x1];
1235         u8         port_type[0x2];
1236         u8         num_ports[0x8];
1237 
1238         u8         reserved_at_1c0[0x1];
1239         u8         pps[0x1];
1240         u8         pps_modify[0x1];
1241         u8         log_max_msg[0x5];
1242         u8         reserved_at_1c8[0x4];
1243         u8         max_tc[0x4];
1244         u8         temp_warn_event[0x1];
1245         u8         dcbx[0x1];
1246         u8         general_notification_event[0x1];
1247         u8         reserved_at_1d3[0x2];
1248         u8         fpga[0x1];
1249         u8         rol_s[0x1];
1250         u8         rol_g[0x1];
1251         u8         reserved_at_1d8[0x1];
1252         u8         wol_s[0x1];
1253         u8         wol_g[0x1];
1254         u8         wol_a[0x1];
1255         u8         wol_b[0x1];
1256         u8         wol_m[0x1];
1257         u8         wol_u[0x1];
1258         u8         wol_p[0x1];
1259 
1260         u8         stat_rate_support[0x10];
1261         u8         reserved_at_1f0[0xc];
1262         u8         cqe_version[0x4];
1263 
1264         u8         compact_address_vector[0x1];
1265         u8         striding_rq[0x1];
1266         u8         reserved_at_202[0x1];
1267         u8         ipoib_enhanced_offloads[0x1];
1268         u8         ipoib_basic_offloads[0x1];
1269         u8         reserved_at_205[0x1];
1270         u8         repeated_block_disabled[0x1];
1271         u8         umr_modify_entity_size_disabled[0x1];
1272         u8         umr_modify_atomic_disabled[0x1];
1273         u8         umr_indirect_mkey_disabled[0x1];
1274         u8         umr_fence[0x2];
1275         u8         dc_req_scat_data_cqe[0x1];
1276         u8         reserved_at_20d[0x2];
1277         u8         drain_sigerr[0x1];
1278         u8         cmdif_checksum[0x2];
1279         u8         sigerr_cqe[0x1];
1280         u8         reserved_at_213[0x1];
1281         u8         wq_signature[0x1];
1282         u8         sctr_data_cqe[0x1];
1283         u8         reserved_at_216[0x1];
1284         u8         sho[0x1];
1285         u8         tph[0x1];
1286         u8         rf[0x1];
1287         u8         dct[0x1];
1288         u8         qos[0x1];
1289         u8         eth_net_offloads[0x1];
1290         u8         roce[0x1];
1291         u8         atomic[0x1];
1292         u8         reserved_at_21f[0x1];
1293 
1294         u8         cq_oi[0x1];
1295         u8         cq_resize[0x1];
1296         u8         cq_moderation[0x1];
1297         u8         reserved_at_223[0x3];
1298         u8         cq_eq_remap[0x1];
1299         u8         pg[0x1];
1300         u8         block_lb_mc[0x1];
1301         u8         reserved_at_229[0x1];
1302         u8         scqe_break_moderation[0x1];
1303         u8         cq_period_start_from_cqe[0x1];
1304         u8         cd[0x1];
1305         u8         reserved_at_22d[0x1];
1306         u8         apm[0x1];
1307         u8         vector_calc[0x1];
1308         u8         umr_ptr_rlky[0x1];
1309         u8         imaicl[0x1];
1310         u8         qp_packet_based[0x1];
1311         u8         reserved_at_233[0x3];
1312         u8         qkv[0x1];
1313         u8         pkv[0x1];
1314         u8         set_deth_sqpn[0x1];
1315         u8         reserved_at_239[0x3];
1316         u8         xrc[0x1];
1317         u8         ud[0x1];
1318         u8         uc[0x1];
1319         u8         rc[0x1];
1320 
1321         u8         uar_4k[0x1];
1322         u8         reserved_at_241[0x9];
1323         u8         uar_sz[0x6];
1324         u8         reserved_at_250[0x8];
1325         u8         log_pg_sz[0x8];
1326 
1327         u8         bf[0x1];
1328         u8         driver_version[0x1];
1329         u8         pad_tx_eth_packet[0x1];
1330         u8         reserved_at_263[0x8];
1331         u8         log_bf_reg_size[0x5];
1332 
1333         u8         reserved_at_270[0x8];
1334         u8         lag_tx_port_affinity[0x1];
1335         u8         reserved_at_279[0x2];
1336         u8         lag_master[0x1];
1337         u8         num_lag_ports[0x4];
1338 
1339         u8         reserved_at_280[0x10];
1340         u8         max_wqe_sz_sq[0x10];
1341 
1342         u8         reserved_at_2a0[0x10];
1343         u8         max_wqe_sz_rq[0x10];
1344 
1345         u8         max_flow_counter_31_16[0x10];
1346         u8         max_wqe_sz_sq_dc[0x10];
1347 
1348         u8         reserved_at_2e0[0x7];
1349         u8         max_qp_mcg[0x19];
1350 
1351         u8         reserved_at_300[0x10];
1352         u8         flow_counter_bulk_alloc[0x8];
1353         u8         log_max_mcg[0x8];
1354 
1355         u8         reserved_at_320[0x3];
1356         u8         log_max_transport_domain[0x5];
1357         u8         reserved_at_328[0x3];
1358         u8         log_max_pd[0x5];
1359         u8         reserved_at_330[0xb];
1360         u8         log_max_xrcd[0x5];
1361 
1362         u8         nic_receive_steering_discard[0x1];
1363         u8         receive_discard_vport_down[0x1];
1364         u8         transmit_discard_vport_down[0x1];
1365         u8         reserved_at_343[0x5];
1366         u8         log_max_flow_counter_bulk[0x8];
1367         u8         max_flow_counter_15_0[0x10];
1368 
1369 
1370         u8         reserved_at_360[0x3];
1371         u8         log_max_rq[0x5];
1372         u8         reserved_at_368[0x3];
1373         u8         log_max_sq[0x5];
1374         u8         reserved_at_370[0x3];
1375         u8         log_max_tir[0x5];
1376         u8         reserved_at_378[0x3];
1377         u8         log_max_tis[0x5];
1378 
1379         u8         basic_cyclic_rcv_wqe[0x1];
1380         u8         reserved_at_381[0x2];
1381         u8         log_max_rmp[0x5];
1382         u8         reserved_at_388[0x3];
1383         u8         log_max_rqt[0x5];
1384         u8         reserved_at_390[0x3];
1385         u8         log_max_rqt_size[0x5];
1386         u8         reserved_at_398[0x3];
1387         u8         log_max_tis_per_sq[0x5];
1388 
1389         u8         ext_stride_num_range[0x1];
1390         u8         reserved_at_3a1[0x2];
1391         u8         log_max_stride_sz_rq[0x5];
1392         u8         reserved_at_3a8[0x3];
1393         u8         log_min_stride_sz_rq[0x5];
1394         u8         reserved_at_3b0[0x3];
1395         u8         log_max_stride_sz_sq[0x5];
1396         u8         reserved_at_3b8[0x3];
1397         u8         log_min_stride_sz_sq[0x5];
1398 
1399         u8         hairpin[0x1];
1400         u8         reserved_at_3c1[0x2];
1401         u8         log_max_hairpin_queues[0x5];
1402         u8         reserved_at_3c8[0x3];
1403         u8         log_max_hairpin_wq_data_sz[0x5];
1404         u8         reserved_at_3d0[0x3];
1405         u8         log_max_hairpin_num_packets[0x5];
1406         u8         reserved_at_3d8[0x3];
1407         u8         log_max_wq_sz[0x5];
1408 
1409         u8         nic_vport_change_event[0x1];
1410         u8         disable_local_lb_uc[0x1];
1411         u8         disable_local_lb_mc[0x1];
1412         u8         log_min_hairpin_wq_data_sz[0x5];
1413         u8         reserved_at_3e8[0x3];
1414         u8         log_max_vlan_list[0x5];
1415         u8         reserved_at_3f0[0x3];
1416         u8         log_max_current_mc_list[0x5];
1417         u8         reserved_at_3f8[0x3];
1418         u8         log_max_current_uc_list[0x5];
1419 
1420         u8         general_obj_types[0x40];
1421 
1422         u8         reserved_at_440[0x20];
1423 
1424         u8         reserved_at_460[0x3];
1425         u8         log_max_uctx[0x5];
1426         u8         reserved_at_468[0x3];
1427         u8         log_max_umem[0x5];
1428         u8         max_num_eqs[0x10];
1429 
1430         u8         reserved_at_480[0x1];
1431         u8         tls_tx[0x1];
1432         u8         reserved_at_482[0x1];
1433         u8         log_max_l2_table[0x5];
1434         u8         reserved_at_488[0x8];
1435         u8         log_uar_page_sz[0x10];
1436 
1437         u8         reserved_at_4a0[0x20];
1438         u8         device_frequency_mhz[0x20];
1439         u8         device_frequency_khz[0x20];
1440 
1441         u8         reserved_at_500[0x20];
1442         u8         num_of_uars_per_page[0x20];
1443 
1444         u8         flex_parser_protocols[0x20];
1445 
1446         u8         max_geneve_tlv_options[0x8];
1447         u8         reserved_at_568[0x3];
1448         u8         max_geneve_tlv_option_data_len[0x5];
1449         u8         reserved_at_570[0x10];
1450 
1451         u8         reserved_at_580[0x33];
1452         u8         log_max_dek[0x5];
1453         u8         reserved_at_5b8[0x4];
1454         u8         mini_cqe_resp_stride_index[0x1];
1455         u8         cqe_128_always[0x1];
1456         u8         cqe_compression_128[0x1];
1457         u8         cqe_compression[0x1];
1458 
1459         u8         cqe_compression_timeout[0x10];
1460         u8         cqe_compression_max_num[0x10];
1461 
1462         u8         reserved_at_5e0[0x10];
1463         u8         tag_matching[0x1];
1464         u8         rndv_offload_rc[0x1];
1465         u8         rndv_offload_dc[0x1];
1466         u8         log_tag_matching_list_sz[0x5];
1467         u8         reserved_at_5f8[0x3];
1468         u8         log_max_xrq[0x5];
1469 
1470         u8         affiliate_nic_vport_criteria[0x8];
1471         u8         native_port_num[0x8];
1472         u8         num_vhca_ports[0x8];
1473         u8         reserved_at_618[0x6];
1474         u8         sw_owner_id[0x1];
1475         u8         reserved_at_61f[0x1];
1476 
1477         u8         max_num_of_monitor_counters[0x10];
1478         u8         num_ppcnt_monitor_counters[0x10];
1479 
1480         u8         reserved_at_640[0x10];
1481         u8         num_q_monitor_counters[0x10];
1482 
1483         u8         reserved_at_660[0x20];
1484 
1485         u8         sf[0x1];
1486         u8         sf_set_partition[0x1];
1487         u8         reserved_at_682[0x1];
1488         u8         log_max_sf[0x5];
1489         u8         reserved_at_688[0x8];
1490         u8         log_min_sf_size[0x8];
1491         u8         max_num_sf_partitions[0x8];
1492 
1493         u8         uctx_cap[0x20];
1494 
1495         u8         reserved_at_6c0[0x4];
1496         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1497         u8         flex_parser_id_icmp_dw1[0x4];
1498         u8         flex_parser_id_icmp_dw0[0x4];
1499         u8         flex_parser_id_icmpv6_dw1[0x4];
1500         u8         flex_parser_id_icmpv6_dw0[0x4];
1501         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1502         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1503 
1504         u8         reserved_at_6e0[0x10];
1505         u8         sf_base_id[0x10];
1506 
1507         u8         reserved_at_700[0x80];
1508         u8         vhca_tunnel_commands[0x40];
1509         u8         reserved_at_7c0[0x40];
1510 };
1511 
1512 enum mlx5_flow_destination_type {
1513         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1514         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1515         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1516 
1517         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1518         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1519         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1520 };
1521 
1522 enum mlx5_flow_table_miss_action {
1523         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1524         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1525         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1526 };
1527 
1528 struct mlx5_ifc_dest_format_struct_bits {
1529         u8         destination_type[0x8];
1530         u8         destination_id[0x18];
1531 
1532         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1533         u8         packet_reformat[0x1];
1534         u8         reserved_at_22[0xe];
1535         u8         destination_eswitch_owner_vhca_id[0x10];
1536 };
1537 
1538 struct mlx5_ifc_flow_counter_list_bits {
1539         u8         flow_counter_id[0x20];
1540 
1541         u8         reserved_at_20[0x20];
1542 };
1543 
1544 struct mlx5_ifc_extended_dest_format_bits {
1545         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1546 
1547         u8         packet_reformat_id[0x20];
1548 
1549         u8         reserved_at_60[0x20];
1550 };
1551 
1552 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1553         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1554         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1555 };
1556 
1557 struct mlx5_ifc_fte_match_param_bits {
1558         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1559 
1560         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1561 
1562         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1563 
1564         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1565 
1566         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1567 
1568         u8         reserved_at_a00[0x600];
1569 };
1570 
1571 enum {
1572         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1573         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1574         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1575         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1576         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1577 };
1578 
1579 struct mlx5_ifc_rx_hash_field_select_bits {
1580         u8         l3_prot_type[0x1];
1581         u8         l4_prot_type[0x1];
1582         u8         selected_fields[0x1e];
1583 };
1584 
1585 enum {
1586         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1587         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1588 };
1589 
1590 enum {
1591         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1592         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1593 };
1594 
1595 struct mlx5_ifc_wq_bits {
1596         u8         wq_type[0x4];
1597         u8         wq_signature[0x1];
1598         u8         end_padding_mode[0x2];
1599         u8         cd_slave[0x1];
1600         u8         reserved_at_8[0x18];
1601 
1602         u8         hds_skip_first_sge[0x1];
1603         u8         log2_hds_buf_size[0x3];
1604         u8         reserved_at_24[0x7];
1605         u8         page_offset[0x5];
1606         u8         lwm[0x10];
1607 
1608         u8         reserved_at_40[0x8];
1609         u8         pd[0x18];
1610 
1611         u8         reserved_at_60[0x8];
1612         u8         uar_page[0x18];
1613 
1614         u8         dbr_addr[0x40];
1615 
1616         u8         hw_counter[0x20];
1617 
1618         u8         sw_counter[0x20];
1619 
1620         u8         reserved_at_100[0xc];
1621         u8         log_wq_stride[0x4];
1622         u8         reserved_at_110[0x3];
1623         u8         log_wq_pg_sz[0x5];
1624         u8         reserved_at_118[0x3];
1625         u8         log_wq_sz[0x5];
1626 
1627         u8         dbr_umem_valid[0x1];
1628         u8         wq_umem_valid[0x1];
1629         u8         reserved_at_122[0x1];
1630         u8         log_hairpin_num_packets[0x5];
1631         u8         reserved_at_128[0x3];
1632         u8         log_hairpin_data_sz[0x5];
1633 
1634         u8         reserved_at_130[0x4];
1635         u8         log_wqe_num_of_strides[0x4];
1636         u8         two_byte_shift_en[0x1];
1637         u8         reserved_at_139[0x4];
1638         u8         log_wqe_stride_size[0x3];
1639 
1640         u8         reserved_at_140[0x4c0];
1641 
1642         struct mlx5_ifc_cmd_pas_bits pas[0];
1643 };
1644 
1645 struct mlx5_ifc_rq_num_bits {
1646         u8         reserved_at_0[0x8];
1647         u8         rq_num[0x18];
1648 };
1649 
1650 struct mlx5_ifc_mac_address_layout_bits {
1651         u8         reserved_at_0[0x10];
1652         u8         mac_addr_47_32[0x10];
1653 
1654         u8         mac_addr_31_0[0x20];
1655 };
1656 
1657 struct mlx5_ifc_vlan_layout_bits {
1658         u8         reserved_at_0[0x14];
1659         u8         vlan[0x0c];
1660 
1661         u8         reserved_at_20[0x20];
1662 };
1663 
1664 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1665         u8         reserved_at_0[0xa0];
1666 
1667         u8         min_time_between_cnps[0x20];
1668 
1669         u8         reserved_at_c0[0x12];
1670         u8         cnp_dscp[0x6];
1671         u8         reserved_at_d8[0x4];
1672         u8         cnp_prio_mode[0x1];
1673         u8         cnp_802p_prio[0x3];
1674 
1675         u8         reserved_at_e0[0x720];
1676 };
1677 
1678 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1679         u8         reserved_at_0[0x60];
1680 
1681         u8         reserved_at_60[0x4];
1682         u8         clamp_tgt_rate[0x1];
1683         u8         reserved_at_65[0x3];
1684         u8         clamp_tgt_rate_after_time_inc[0x1];
1685         u8         reserved_at_69[0x17];
1686 
1687         u8         reserved_at_80[0x20];
1688 
1689         u8         rpg_time_reset[0x20];
1690 
1691         u8         rpg_byte_reset[0x20];
1692 
1693         u8         rpg_threshold[0x20];
1694 
1695         u8         rpg_max_rate[0x20];
1696 
1697         u8         rpg_ai_rate[0x20];
1698 
1699         u8         rpg_hai_rate[0x20];
1700 
1701         u8         rpg_gd[0x20];
1702 
1703         u8         rpg_min_dec_fac[0x20];
1704 
1705         u8         rpg_min_rate[0x20];
1706 
1707         u8         reserved_at_1c0[0xe0];
1708 
1709         u8         rate_to_set_on_first_cnp[0x20];
1710 
1711         u8         dce_tcp_g[0x20];
1712 
1713         u8         dce_tcp_rtt[0x20];
1714 
1715         u8         rate_reduce_monitor_period[0x20];
1716 
1717         u8         reserved_at_320[0x20];
1718 
1719         u8         initial_alpha_value[0x20];
1720 
1721         u8         reserved_at_360[0x4a0];
1722 };
1723 
1724 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1725         u8         reserved_at_0[0x80];
1726 
1727         u8         rppp_max_rps[0x20];
1728 
1729         u8         rpg_time_reset[0x20];
1730 
1731         u8         rpg_byte_reset[0x20];
1732 
1733         u8         rpg_threshold[0x20];
1734 
1735         u8         rpg_max_rate[0x20];
1736 
1737         u8         rpg_ai_rate[0x20];
1738 
1739         u8         rpg_hai_rate[0x20];
1740 
1741         u8         rpg_gd[0x20];
1742 
1743         u8         rpg_min_dec_fac[0x20];
1744 
1745         u8         rpg_min_rate[0x20];
1746 
1747         u8         reserved_at_1c0[0x640];
1748 };
1749 
1750 enum {
1751         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1752         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1753         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1754 };
1755 
1756 struct mlx5_ifc_resize_field_select_bits {
1757         u8         resize_field_select[0x20];
1758 };
1759 
1760 enum {
1761         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1762         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1763         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1764         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1765 };
1766 
1767 struct mlx5_ifc_modify_field_select_bits {
1768         u8         modify_field_select[0x20];
1769 };
1770 
1771 struct mlx5_ifc_field_select_r_roce_np_bits {
1772         u8         field_select_r_roce_np[0x20];
1773 };
1774 
1775 struct mlx5_ifc_field_select_r_roce_rp_bits {
1776         u8         field_select_r_roce_rp[0x20];
1777 };
1778 
1779 enum {
1780         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1781         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1782         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1783         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1784         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1785         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1786         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1787         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1788         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1789         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1790 };
1791 
1792 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1793         u8         field_select_8021qaurp[0x20];
1794 };
1795 
1796 struct mlx5_ifc_phys_layer_cntrs_bits {
1797         u8         time_since_last_clear_high[0x20];
1798 
1799         u8         time_since_last_clear_low[0x20];
1800 
1801         u8         symbol_errors_high[0x20];
1802 
1803         u8         symbol_errors_low[0x20];
1804 
1805         u8         sync_headers_errors_high[0x20];
1806 
1807         u8         sync_headers_errors_low[0x20];
1808 
1809         u8         edpl_bip_errors_lane0_high[0x20];
1810 
1811         u8         edpl_bip_errors_lane0_low[0x20];
1812 
1813         u8         edpl_bip_errors_lane1_high[0x20];
1814 
1815         u8         edpl_bip_errors_lane1_low[0x20];
1816 
1817         u8         edpl_bip_errors_lane2_high[0x20];
1818 
1819         u8         edpl_bip_errors_lane2_low[0x20];
1820 
1821         u8         edpl_bip_errors_lane3_high[0x20];
1822 
1823         u8         edpl_bip_errors_lane3_low[0x20];
1824 
1825         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1826 
1827         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1828 
1829         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1830 
1831         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1832 
1833         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1834 
1835         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1836 
1837         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1838 
1839         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1840 
1841         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1842 
1843         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1844 
1845         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1846 
1847         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1848 
1849         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1850 
1851         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1852 
1853         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1854 
1855         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1856 
1857         u8         rs_fec_corrected_blocks_high[0x20];
1858 
1859         u8         rs_fec_corrected_blocks_low[0x20];
1860 
1861         u8         rs_fec_uncorrectable_blocks_high[0x20];
1862 
1863         u8         rs_fec_uncorrectable_blocks_low[0x20];
1864 
1865         u8         rs_fec_no_errors_blocks_high[0x20];
1866 
1867         u8         rs_fec_no_errors_blocks_low[0x20];
1868 
1869         u8         rs_fec_single_error_blocks_high[0x20];
1870 
1871         u8         rs_fec_single_error_blocks_low[0x20];
1872 
1873         u8         rs_fec_corrected_symbols_total_high[0x20];
1874 
1875         u8         rs_fec_corrected_symbols_total_low[0x20];
1876 
1877         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1878 
1879         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1880 
1881         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1882 
1883         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1884 
1885         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1886 
1887         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1888 
1889         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1890 
1891         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1892 
1893         u8         link_down_events[0x20];
1894 
1895         u8         successful_recovery_events[0x20];
1896 
1897         u8         reserved_at_640[0x180];
1898 };
1899 
1900 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1901         u8         time_since_last_clear_high[0x20];
1902 
1903         u8         time_since_last_clear_low[0x20];
1904 
1905         u8         phy_received_bits_high[0x20];
1906 
1907         u8         phy_received_bits_low[0x20];
1908 
1909         u8         phy_symbol_errors_high[0x20];
1910 
1911         u8         phy_symbol_errors_low[0x20];
1912 
1913         u8         phy_corrected_bits_high[0x20];
1914 
1915         u8         phy_corrected_bits_low[0x20];
1916 
1917         u8         phy_corrected_bits_lane0_high[0x20];
1918 
1919         u8         phy_corrected_bits_lane0_low[0x20];
1920 
1921         u8         phy_corrected_bits_lane1_high[0x20];
1922 
1923         u8         phy_corrected_bits_lane1_low[0x20];
1924 
1925         u8         phy_corrected_bits_lane2_high[0x20];
1926 
1927         u8         phy_corrected_bits_lane2_low[0x20];
1928 
1929         u8         phy_corrected_bits_lane3_high[0x20];
1930 
1931         u8         phy_corrected_bits_lane3_low[0x20];
1932 
1933         u8         reserved_at_200[0x5c0];
1934 };
1935 
1936 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1937         u8         symbol_error_counter[0x10];
1938 
1939         u8         link_error_recovery_counter[0x8];
1940 
1941         u8         link_downed_counter[0x8];
1942 
1943         u8         port_rcv_errors[0x10];
1944 
1945         u8         port_rcv_remote_physical_errors[0x10];
1946 
1947         u8         port_rcv_switch_relay_errors[0x10];
1948 
1949         u8         port_xmit_discards[0x10];
1950 
1951         u8         port_xmit_constraint_errors[0x8];
1952 
1953         u8         port_rcv_constraint_errors[0x8];
1954 
1955         u8         reserved_at_70[0x8];
1956 
1957         u8         link_overrun_errors[0x8];
1958 
1959         u8         reserved_at_80[0x10];
1960 
1961         u8         vl_15_dropped[0x10];
1962 
1963         u8         reserved_at_a0[0x80];
1964 
1965         u8         port_xmit_wait[0x20];
1966 };
1967 
1968 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
1969         u8         transmit_queue_high[0x20];
1970 
1971         u8         transmit_queue_low[0x20];
1972 
1973         u8         no_buffer_discard_uc_high[0x20];
1974 
1975         u8         no_buffer_discard_uc_low[0x20];
1976 
1977         u8         reserved_at_80[0x740];
1978 };
1979 
1980 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
1981         u8         wred_discard_high[0x20];
1982 
1983         u8         wred_discard_low[0x20];
1984 
1985         u8         ecn_marked_tc_high[0x20];
1986 
1987         u8         ecn_marked_tc_low[0x20];
1988 
1989         u8         reserved_at_80[0x740];
1990 };
1991 
1992 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1993         u8         rx_octets_high[0x20];
1994 
1995         u8         rx_octets_low[0x20];
1996 
1997         u8         reserved_at_40[0xc0];
1998 
1999         u8         rx_frames_high[0x20];
2000 
2001         u8         rx_frames_low[0x20];
2002 
2003         u8         tx_octets_high[0x20];
2004 
2005         u8         tx_octets_low[0x20];
2006 
2007         u8         reserved_at_180[0xc0];
2008 
2009         u8         tx_frames_high[0x20];
2010 
2011         u8         tx_frames_low[0x20];
2012 
2013         u8         rx_pause_high[0x20];
2014 
2015         u8         rx_pause_low[0x20];
2016 
2017         u8         rx_pause_duration_high[0x20];
2018 
2019         u8         rx_pause_duration_low[0x20];
2020 
2021         u8         tx_pause_high[0x20];
2022 
2023         u8         tx_pause_low[0x20];
2024 
2025         u8         tx_pause_duration_high[0x20];
2026 
2027         u8         tx_pause_duration_low[0x20];
2028 
2029         u8         rx_pause_transition_high[0x20];
2030 
2031         u8         rx_pause_transition_low[0x20];
2032 
2033         u8         reserved_at_3c0[0x40];
2034 
2035         u8         device_stall_minor_watermark_cnt_high[0x20];
2036 
2037         u8         device_stall_minor_watermark_cnt_low[0x20];
2038 
2039         u8         device_stall_critical_watermark_cnt_high[0x20];
2040 
2041         u8         device_stall_critical_watermark_cnt_low[0x20];
2042 
2043         u8         reserved_at_480[0x340];
2044 };
2045 
2046 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2047         u8         port_transmit_wait_high[0x20];
2048 
2049         u8         port_transmit_wait_low[0x20];
2050 
2051         u8         reserved_at_40[0x100];
2052 
2053         u8         rx_buffer_almost_full_high[0x20];
2054 
2055         u8         rx_buffer_almost_full_low[0x20];
2056 
2057         u8         rx_buffer_full_high[0x20];
2058 
2059         u8         rx_buffer_full_low[0x20];
2060 
2061         u8         rx_icrc_encapsulated_high[0x20];
2062 
2063         u8         rx_icrc_encapsulated_low[0x20];
2064 
2065         u8         reserved_at_200[0x5c0];
2066 };
2067 
2068 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2069         u8         dot3stats_alignment_errors_high[0x20];
2070 
2071         u8         dot3stats_alignment_errors_low[0x20];
2072 
2073         u8         dot3stats_fcs_errors_high[0x20];
2074 
2075         u8         dot3stats_fcs_errors_low[0x20];
2076 
2077         u8         dot3stats_single_collision_frames_high[0x20];
2078 
2079         u8         dot3stats_single_collision_frames_low[0x20];
2080 
2081         u8         dot3stats_multiple_collision_frames_high[0x20];
2082 
2083         u8         dot3stats_multiple_collision_frames_low[0x20];
2084 
2085         u8         dot3stats_sqe_test_errors_high[0x20];
2086 
2087         u8         dot3stats_sqe_test_errors_low[0x20];
2088 
2089         u8         dot3stats_deferred_transmissions_high[0x20];
2090 
2091         u8         dot3stats_deferred_transmissions_low[0x20];
2092 
2093         u8         dot3stats_late_collisions_high[0x20];
2094 
2095         u8         dot3stats_late_collisions_low[0x20];
2096 
2097         u8         dot3stats_excessive_collisions_high[0x20];
2098 
2099         u8         dot3stats_excessive_collisions_low[0x20];
2100 
2101         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2102 
2103         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2104 
2105         u8         dot3stats_carrier_sense_errors_high[0x20];
2106 
2107         u8         dot3stats_carrier_sense_errors_low[0x20];
2108 
2109         u8         dot3stats_frame_too_longs_high[0x20];
2110 
2111         u8         dot3stats_frame_too_longs_low[0x20];
2112 
2113         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2114 
2115         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2116 
2117         u8         dot3stats_symbol_errors_high[0x20];
2118 
2119         u8         dot3stats_symbol_errors_low[0x20];
2120 
2121         u8         dot3control_in_unknown_opcodes_high[0x20];
2122 
2123         u8         dot3control_in_unknown_opcodes_low[0x20];
2124 
2125         u8         dot3in_pause_frames_high[0x20];
2126 
2127         u8         dot3in_pause_frames_low[0x20];
2128 
2129         u8         dot3out_pause_frames_high[0x20];
2130 
2131         u8         dot3out_pause_frames_low[0x20];
2132 
2133         u8         reserved_at_400[0x3c0];
2134 };
2135 
2136 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2137         u8         ether_stats_drop_events_high[0x20];
2138 
2139         u8         ether_stats_drop_events_low[0x20];
2140 
2141         u8         ether_stats_octets_high[0x20];
2142 
2143         u8         ether_stats_octets_low[0x20];
2144 
2145         u8         ether_stats_pkts_high[0x20];
2146 
2147         u8         ether_stats_pkts_low[0x20];
2148 
2149         u8         ether_stats_broadcast_pkts_high[0x20];
2150 
2151         u8         ether_stats_broadcast_pkts_low[0x20];
2152 
2153         u8         ether_stats_multicast_pkts_high[0x20];
2154 
2155         u8         ether_stats_multicast_pkts_low[0x20];
2156 
2157         u8         ether_stats_crc_align_errors_high[0x20];
2158 
2159         u8         ether_stats_crc_align_errors_low[0x20];
2160 
2161         u8         ether_stats_undersize_pkts_high[0x20];
2162 
2163         u8         ether_stats_undersize_pkts_low[0x20];
2164 
2165         u8         ether_stats_oversize_pkts_high[0x20];
2166 
2167         u8         ether_stats_oversize_pkts_low[0x20];
2168 
2169         u8         ether_stats_fragments_high[0x20];
2170 
2171         u8         ether_stats_fragments_low[0x20];
2172 
2173         u8         ether_stats_jabbers_high[0x20];
2174 
2175         u8         ether_stats_jabbers_low[0x20];
2176 
2177         u8         ether_stats_collisions_high[0x20];
2178 
2179         u8         ether_stats_collisions_low[0x20];
2180 
2181         u8         ether_stats_pkts64octets_high[0x20];
2182 
2183         u8         ether_stats_pkts64octets_low[0x20];
2184 
2185         u8         ether_stats_pkts65to127octets_high[0x20];
2186 
2187         u8         ether_stats_pkts65to127octets_low[0x20];
2188 
2189         u8         ether_stats_pkts128to255octets_high[0x20];
2190 
2191         u8         ether_stats_pkts128to255octets_low[0x20];
2192 
2193         u8         ether_stats_pkts256to511octets_high[0x20];
2194 
2195         u8         ether_stats_pkts256to511octets_low[0x20];
2196 
2197         u8         ether_stats_pkts512to1023octets_high[0x20];
2198 
2199         u8         ether_stats_pkts512to1023octets_low[0x20];
2200 
2201         u8         ether_stats_pkts1024to1518octets_high[0x20];
2202 
2203         u8         ether_stats_pkts1024to1518octets_low[0x20];
2204 
2205         u8         ether_stats_pkts1519to2047octets_high[0x20];
2206 
2207         u8         ether_stats_pkts1519to2047octets_low[0x20];
2208 
2209         u8         ether_stats_pkts2048to4095octets_high[0x20];
2210 
2211         u8         ether_stats_pkts2048to4095octets_low[0x20];
2212 
2213         u8         ether_stats_pkts4096to8191octets_high[0x20];
2214 
2215         u8         ether_stats_pkts4096to8191octets_low[0x20];
2216 
2217         u8         ether_stats_pkts8192to10239octets_high[0x20];
2218 
2219         u8         ether_stats_pkts8192to10239octets_low[0x20];
2220 
2221         u8         reserved_at_540[0x280];
2222 };
2223 
2224 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2225         u8         if_in_octets_high[0x20];
2226 
2227         u8         if_in_octets_low[0x20];
2228 
2229         u8         if_in_ucast_pkts_high[0x20];
2230 
2231         u8         if_in_ucast_pkts_low[0x20];
2232 
2233         u8         if_in_discards_high[0x20];
2234 
2235         u8         if_in_discards_low[0x20];
2236 
2237         u8         if_in_errors_high[0x20];
2238 
2239         u8         if_in_errors_low[0x20];
2240 
2241         u8         if_in_unknown_protos_high[0x20];
2242 
2243         u8         if_in_unknown_protos_low[0x20];
2244 
2245         u8         if_out_octets_high[0x20];
2246 
2247         u8         if_out_octets_low[0x20];
2248 
2249         u8         if_out_ucast_pkts_high[0x20];
2250 
2251         u8         if_out_ucast_pkts_low[0x20];
2252 
2253         u8         if_out_discards_high[0x20];
2254 
2255         u8         if_out_discards_low[0x20];
2256 
2257         u8         if_out_errors_high[0x20];
2258 
2259         u8         if_out_errors_low[0x20];
2260 
2261         u8         if_in_multicast_pkts_high[0x20];
2262 
2263         u8         if_in_multicast_pkts_low[0x20];
2264 
2265         u8         if_in_broadcast_pkts_high[0x20];
2266 
2267         u8         if_in_broadcast_pkts_low[0x20];
2268 
2269         u8         if_out_multicast_pkts_high[0x20];
2270 
2271         u8         if_out_multicast_pkts_low[0x20];
2272 
2273         u8         if_out_broadcast_pkts_high[0x20];
2274 
2275         u8         if_out_broadcast_pkts_low[0x20];
2276 
2277         u8         reserved_at_340[0x480];
2278 };
2279 
2280 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2281         u8         a_frames_transmitted_ok_high[0x20];
2282 
2283         u8         a_frames_transmitted_ok_low[0x20];
2284 
2285         u8         a_frames_received_ok_high[0x20];
2286 
2287         u8         a_frames_received_ok_low[0x20];
2288 
2289         u8         a_frame_check_sequence_errors_high[0x20];
2290 
2291         u8         a_frame_check_sequence_errors_low[0x20];
2292 
2293         u8         a_alignment_errors_high[0x20];
2294 
2295         u8         a_alignment_errors_low[0x20];
2296 
2297         u8         a_octets_transmitted_ok_high[0x20];
2298 
2299         u8         a_octets_transmitted_ok_low[0x20];
2300 
2301         u8         a_octets_received_ok_high[0x20];
2302 
2303         u8         a_octets_received_ok_low[0x20];
2304 
2305         u8         a_multicast_frames_xmitted_ok_high[0x20];
2306 
2307         u8         a_multicast_frames_xmitted_ok_low[0x20];
2308 
2309         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2310 
2311         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2312 
2313         u8         a_multicast_frames_received_ok_high[0x20];
2314 
2315         u8         a_multicast_frames_received_ok_low[0x20];
2316 
2317         u8         a_broadcast_frames_received_ok_high[0x20];
2318 
2319         u8         a_broadcast_frames_received_ok_low[0x20];
2320 
2321         u8         a_in_range_length_errors_high[0x20];
2322 
2323         u8         a_in_range_length_errors_low[0x20];
2324 
2325         u8         a_out_of_range_length_field_high[0x20];
2326 
2327         u8         a_out_of_range_length_field_low[0x20];
2328 
2329         u8         a_frame_too_long_errors_high[0x20];
2330 
2331         u8         a_frame_too_long_errors_low[0x20];
2332 
2333         u8         a_symbol_error_during_carrier_high[0x20];
2334 
2335         u8         a_symbol_error_during_carrier_low[0x20];
2336 
2337         u8         a_mac_control_frames_transmitted_high[0x20];
2338 
2339         u8         a_mac_control_frames_transmitted_low[0x20];
2340 
2341         u8         a_mac_control_frames_received_high[0x20];
2342 
2343         u8         a_mac_control_frames_received_low[0x20];
2344 
2345         u8         a_unsupported_opcodes_received_high[0x20];
2346 
2347         u8         a_unsupported_opcodes_received_low[0x20];
2348 
2349         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2350 
2351         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2352 
2353         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2354 
2355         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2356 
2357         u8         reserved_at_4c0[0x300];
2358 };
2359 
2360 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2361         u8         life_time_counter_high[0x20];
2362 
2363         u8         life_time_counter_low[0x20];
2364 
2365         u8         rx_errors[0x20];
2366 
2367         u8         tx_errors[0x20];
2368 
2369         u8         l0_to_recovery_eieos[0x20];
2370 
2371         u8         l0_to_recovery_ts[0x20];
2372 
2373         u8         l0_to_recovery_framing[0x20];
2374 
2375         u8         l0_to_recovery_retrain[0x20];
2376 
2377         u8         crc_error_dllp[0x20];
2378 
2379         u8         crc_error_tlp[0x20];
2380 
2381         u8         tx_overflow_buffer_pkt_high[0x20];
2382 
2383         u8         tx_overflow_buffer_pkt_low[0x20];
2384 
2385         u8         outbound_stalled_reads[0x20];
2386 
2387         u8         outbound_stalled_writes[0x20];
2388 
2389         u8         outbound_stalled_reads_events[0x20];
2390 
2391         u8         outbound_stalled_writes_events[0x20];
2392 
2393         u8         reserved_at_200[0x5c0];
2394 };
2395 
2396 struct mlx5_ifc_cmd_inter_comp_event_bits {
2397         u8         command_completion_vector[0x20];
2398 
2399         u8         reserved_at_20[0xc0];
2400 };
2401 
2402 struct mlx5_ifc_stall_vl_event_bits {
2403         u8         reserved_at_0[0x18];
2404         u8         port_num[0x1];
2405         u8         reserved_at_19[0x3];
2406         u8         vl[0x4];
2407 
2408         u8         reserved_at_20[0xa0];
2409 };
2410 
2411 struct mlx5_ifc_db_bf_congestion_event_bits {
2412         u8         event_subtype[0x8];
2413         u8         reserved_at_8[0x8];
2414         u8         congestion_level[0x8];
2415         u8         reserved_at_18[0x8];
2416 
2417         u8         reserved_at_20[0xa0];
2418 };
2419 
2420 struct mlx5_ifc_gpio_event_bits {
2421         u8         reserved_at_0[0x60];
2422 
2423         u8         gpio_event_hi[0x20];
2424 
2425         u8         gpio_event_lo[0x20];
2426 
2427         u8         reserved_at_a0[0x40];
2428 };
2429 
2430 struct mlx5_ifc_port_state_change_event_bits {
2431         u8         reserved_at_0[0x40];
2432 
2433         u8         port_num[0x4];
2434         u8         reserved_at_44[0x1c];
2435 
2436         u8         reserved_at_60[0x80];
2437 };
2438 
2439 struct mlx5_ifc_dropped_packet_logged_bits {
2440         u8         reserved_at_0[0xe0];
2441 };
2442 
2443 enum {
2444         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2445         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2446 };
2447 
2448 struct mlx5_ifc_cq_error_bits {
2449         u8         reserved_at_0[0x8];
2450         u8         cqn[0x18];
2451 
2452         u8         reserved_at_20[0x20];
2453 
2454         u8         reserved_at_40[0x18];
2455         u8         syndrome[0x8];
2456 
2457         u8         reserved_at_60[0x80];
2458 };
2459 
2460 struct mlx5_ifc_rdma_page_fault_event_bits {
2461         u8         bytes_committed[0x20];
2462 
2463         u8         r_key[0x20];
2464 
2465         u8         reserved_at_40[0x10];
2466         u8         packet_len[0x10];
2467 
2468         u8         rdma_op_len[0x20];
2469 
2470         u8         rdma_va[0x40];
2471 
2472         u8         reserved_at_c0[0x5];
2473         u8         rdma[0x1];
2474         u8         write[0x1];
2475         u8         requestor[0x1];
2476         u8         qp_number[0x18];
2477 };
2478 
2479 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2480         u8         bytes_committed[0x20];
2481 
2482         u8         reserved_at_20[0x10];
2483         u8         wqe_index[0x10];
2484 
2485         u8         reserved_at_40[0x10];
2486         u8         len[0x10];
2487 
2488         u8         reserved_at_60[0x60];
2489 
2490         u8         reserved_at_c0[0x5];
2491         u8         rdma[0x1];
2492         u8         write_read[0x1];
2493         u8         requestor[0x1];
2494         u8         qpn[0x18];
2495 };
2496 
2497 struct mlx5_ifc_qp_events_bits {
2498         u8         reserved_at_0[0xa0];
2499 
2500         u8         type[0x8];
2501         u8         reserved_at_a8[0x18];
2502 
2503         u8         reserved_at_c0[0x8];
2504         u8         qpn_rqn_sqn[0x18];
2505 };
2506 
2507 struct mlx5_ifc_dct_events_bits {
2508         u8         reserved_at_0[0xc0];
2509 
2510         u8         reserved_at_c0[0x8];
2511         u8         dct_number[0x18];
2512 };
2513 
2514 struct mlx5_ifc_comp_event_bits {
2515         u8         reserved_at_0[0xc0];
2516 
2517         u8         reserved_at_c0[0x8];
2518         u8         cq_number[0x18];
2519 };
2520 
2521 enum {
2522         MLX5_QPC_STATE_RST        = 0x0,
2523         MLX5_QPC_STATE_INIT       = 0x1,
2524         MLX5_QPC_STATE_RTR        = 0x2,
2525         MLX5_QPC_STATE_RTS        = 0x3,
2526         MLX5_QPC_STATE_SQER       = 0x4,
2527         MLX5_QPC_STATE_ERR        = 0x6,
2528         MLX5_QPC_STATE_SQD        = 0x7,
2529         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2530 };
2531 
2532 enum {
2533         MLX5_QPC_ST_RC            = 0x0,
2534         MLX5_QPC_ST_UC            = 0x1,
2535         MLX5_QPC_ST_UD            = 0x2,
2536         MLX5_QPC_ST_XRC           = 0x3,
2537         MLX5_QPC_ST_DCI           = 0x5,
2538         MLX5_QPC_ST_QP0           = 0x7,
2539         MLX5_QPC_ST_QP1           = 0x8,
2540         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2541         MLX5_QPC_ST_REG_UMR       = 0xc,
2542 };
2543 
2544 enum {
2545         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2546         MLX5_QPC_PM_STATE_REARM     = 0x1,
2547         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2548         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2549 };
2550 
2551 enum {
2552         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2553 };
2554 
2555 enum {
2556         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2557         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2558 };
2559 
2560 enum {
2561         MLX5_QPC_MTU_256_BYTES        = 0x1,
2562         MLX5_QPC_MTU_512_BYTES        = 0x2,
2563         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2564         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2565         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2566         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2567 };
2568 
2569 enum {
2570         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2571         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2572         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2573         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2574         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2575         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2576         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2577         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2578 };
2579 
2580 enum {
2581         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2582         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2583         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2584 };
2585 
2586 enum {
2587         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2588         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2589         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2590 };
2591 
2592 struct mlx5_ifc_qpc_bits {
2593         u8         state[0x4];
2594         u8         lag_tx_port_affinity[0x4];
2595         u8         st[0x8];
2596         u8         reserved_at_10[0x3];
2597         u8         pm_state[0x2];
2598         u8         reserved_at_15[0x1];
2599         u8         req_e2e_credit_mode[0x2];
2600         u8         offload_type[0x4];
2601         u8         end_padding_mode[0x2];
2602         u8         reserved_at_1e[0x2];
2603 
2604         u8         wq_signature[0x1];
2605         u8         block_lb_mc[0x1];
2606         u8         atomic_like_write_en[0x1];
2607         u8         latency_sensitive[0x1];
2608         u8         reserved_at_24[0x1];
2609         u8         drain_sigerr[0x1];
2610         u8         reserved_at_26[0x2];
2611         u8         pd[0x18];
2612 
2613         u8         mtu[0x3];
2614         u8         log_msg_max[0x5];
2615         u8         reserved_at_48[0x1];
2616         u8         log_rq_size[0x4];
2617         u8         log_rq_stride[0x3];
2618         u8         no_sq[0x1];
2619         u8         log_sq_size[0x4];
2620         u8         reserved_at_55[0x6];
2621         u8         rlky[0x1];
2622         u8         ulp_stateless_offload_mode[0x4];
2623 
2624         u8         counter_set_id[0x8];
2625         u8         uar_page[0x18];
2626 
2627         u8         reserved_at_80[0x8];
2628         u8         user_index[0x18];
2629 
2630         u8         reserved_at_a0[0x3];
2631         u8         log_page_size[0x5];
2632         u8         remote_qpn[0x18];
2633 
2634         struct mlx5_ifc_ads_bits primary_address_path;
2635 
2636         struct mlx5_ifc_ads_bits secondary_address_path;
2637 
2638         u8         log_ack_req_freq[0x4];
2639         u8         reserved_at_384[0x4];
2640         u8         log_sra_max[0x3];
2641         u8         reserved_at_38b[0x2];
2642         u8         retry_count[0x3];
2643         u8         rnr_retry[0x3];
2644         u8         reserved_at_393[0x1];
2645         u8         fre[0x1];
2646         u8         cur_rnr_retry[0x3];
2647         u8         cur_retry_count[0x3];
2648         u8         reserved_at_39b[0x5];
2649 
2650         u8         reserved_at_3a0[0x20];
2651 
2652         u8         reserved_at_3c0[0x8];
2653         u8         next_send_psn[0x18];
2654 
2655         u8         reserved_at_3e0[0x8];
2656         u8         cqn_snd[0x18];
2657 
2658         u8         reserved_at_400[0x8];
2659         u8         deth_sqpn[0x18];
2660 
2661         u8         reserved_at_420[0x20];
2662 
2663         u8         reserved_at_440[0x8];
2664         u8         last_acked_psn[0x18];
2665 
2666         u8         reserved_at_460[0x8];
2667         u8         ssn[0x18];
2668 
2669         u8         reserved_at_480[0x8];
2670         u8         log_rra_max[0x3];
2671         u8         reserved_at_48b[0x1];
2672         u8         atomic_mode[0x4];
2673         u8         rre[0x1];
2674         u8         rwe[0x1];
2675         u8         rae[0x1];
2676         u8         reserved_at_493[0x1];
2677         u8         page_offset[0x6];
2678         u8         reserved_at_49a[0x3];
2679         u8         cd_slave_receive[0x1];
2680         u8         cd_slave_send[0x1];
2681         u8         cd_master[0x1];
2682 
2683         u8         reserved_at_4a0[0x3];
2684         u8         min_rnr_nak[0x5];
2685         u8         next_rcv_psn[0x18];
2686 
2687         u8         reserved_at_4c0[0x8];
2688         u8         xrcd[0x18];
2689 
2690         u8         reserved_at_4e0[0x8];
2691         u8         cqn_rcv[0x18];
2692 
2693         u8         dbr_addr[0x40];
2694 
2695         u8         q_key[0x20];
2696 
2697         u8         reserved_at_560[0x5];
2698         u8         rq_type[0x3];
2699         u8         srqn_rmpn_xrqn[0x18];
2700 
2701         u8         reserved_at_580[0x8];
2702         u8         rmsn[0x18];
2703 
2704         u8         hw_sq_wqebb_counter[0x10];
2705         u8         sw_sq_wqebb_counter[0x10];
2706 
2707         u8         hw_rq_counter[0x20];
2708 
2709         u8         sw_rq_counter[0x20];
2710 
2711         u8         reserved_at_600[0x20];
2712 
2713         u8         reserved_at_620[0xf];
2714         u8         cgs[0x1];
2715         u8         cs_req[0x8];
2716         u8         cs_res[0x8];
2717 
2718         u8         dc_access_key[0x40];
2719 
2720         u8         reserved_at_680[0x3];
2721         u8         dbr_umem_valid[0x1];
2722 
2723         u8         reserved_at_684[0xbc];
2724 };
2725 
2726 struct mlx5_ifc_roce_addr_layout_bits {
2727         u8         source_l3_address[16][0x8];
2728 
2729         u8         reserved_at_80[0x3];
2730         u8         vlan_valid[0x1];
2731         u8         vlan_id[0xc];
2732         u8         source_mac_47_32[0x10];
2733 
2734         u8         source_mac_31_0[0x20];
2735 
2736         u8         reserved_at_c0[0x14];
2737         u8         roce_l3_type[0x4];
2738         u8         roce_version[0x8];
2739 
2740         u8         reserved_at_e0[0x20];
2741 };
2742 
2743 union mlx5_ifc_hca_cap_union_bits {
2744         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2745         struct mlx5_ifc_odp_cap_bits odp_cap;
2746         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2747         struct mlx5_ifc_roce_cap_bits roce_cap;
2748         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2749         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2750         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2751         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2752         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2753         struct mlx5_ifc_qos_cap_bits qos_cap;
2754         struct mlx5_ifc_debug_cap_bits debug_cap;
2755         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2756         struct mlx5_ifc_tls_cap_bits tls_cap;
2757         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2758         u8         reserved_at_0[0x8000];
2759 };
2760 
2761 enum {
2762         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2763         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2764         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2765         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2766         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2767         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2768         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2769         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2770         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2771         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2772         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2773 };
2774 
2775 enum {
2776         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2777         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2778         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2779 };
2780 
2781 struct mlx5_ifc_vlan_bits {
2782         u8         ethtype[0x10];
2783         u8         prio[0x3];
2784         u8         cfi[0x1];
2785         u8         vid[0xc];
2786 };
2787 
2788 struct mlx5_ifc_flow_context_bits {
2789         struct mlx5_ifc_vlan_bits push_vlan;
2790 
2791         u8         group_id[0x20];
2792 
2793         u8         reserved_at_40[0x8];
2794         u8         flow_tag[0x18];
2795 
2796         u8         reserved_at_60[0x10];
2797         u8         action[0x10];
2798 
2799         u8         extended_destination[0x1];
2800         u8         reserved_at_81[0x1];
2801         u8         flow_source[0x2];
2802         u8         reserved_at_84[0x4];
2803         u8         destination_list_size[0x18];
2804 
2805         u8         reserved_at_a0[0x8];
2806         u8         flow_counter_list_size[0x18];
2807 
2808         u8         packet_reformat_id[0x20];
2809 
2810         u8         modify_header_id[0x20];
2811 
2812         struct mlx5_ifc_vlan_bits push_vlan_2;
2813 
2814         u8         reserved_at_120[0xe0];
2815 
2816         struct mlx5_ifc_fte_match_param_bits match_value;
2817 
2818         u8         reserved_at_1200[0x600];
2819 
2820         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2821 };
2822 
2823 enum {
2824         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2825         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2826 };
2827 
2828 struct mlx5_ifc_xrc_srqc_bits {
2829         u8         state[0x4];
2830         u8         log_xrc_srq_size[0x4];
2831         u8         reserved_at_8[0x18];
2832 
2833         u8         wq_signature[0x1];
2834         u8         cont_srq[0x1];
2835         u8         reserved_at_22[0x1];
2836         u8         rlky[0x1];
2837         u8         basic_cyclic_rcv_wqe[0x1];
2838         u8         log_rq_stride[0x3];
2839         u8         xrcd[0x18];
2840 
2841         u8         page_offset[0x6];
2842         u8         reserved_at_46[0x1];
2843         u8         dbr_umem_valid[0x1];
2844         u8         cqn[0x18];
2845 
2846         u8         reserved_at_60[0x20];
2847 
2848         u8         user_index_equal_xrc_srqn[0x1];
2849         u8         reserved_at_81[0x1];
2850         u8         log_page_size[0x6];
2851         u8         user_index[0x18];
2852 
2853         u8         reserved_at_a0[0x20];
2854 
2855         u8         reserved_at_c0[0x8];
2856         u8         pd[0x18];
2857 
2858         u8         lwm[0x10];
2859         u8         wqe_cnt[0x10];
2860 
2861         u8         reserved_at_100[0x40];
2862 
2863         u8         db_record_addr_h[0x20];
2864 
2865         u8         db_record_addr_l[0x1e];
2866         u8         reserved_at_17e[0x2];
2867 
2868         u8         reserved_at_180[0x80];
2869 };
2870 
2871 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2872         u8         counter_error_queues[0x20];
2873 
2874         u8         total_error_queues[0x20];
2875 
2876         u8         send_queue_priority_update_flow[0x20];
2877 
2878         u8         reserved_at_60[0x20];
2879 
2880         u8         nic_receive_steering_discard[0x40];
2881 
2882         u8         receive_discard_vport_down[0x40];
2883 
2884         u8         transmit_discard_vport_down[0x40];
2885 
2886         u8         reserved_at_140[0xa0];
2887 
2888         u8         internal_rq_out_of_buffer[0x20];
2889 
2890         u8         reserved_at_200[0xe00];
2891 };
2892 
2893 struct mlx5_ifc_traffic_counter_bits {
2894         u8         packets[0x40];
2895 
2896         u8         octets[0x40];
2897 };
2898 
2899 struct mlx5_ifc_tisc_bits {
2900         u8         strict_lag_tx_port_affinity[0x1];
2901         u8         tls_en[0x1];
2902         u8         reserved_at_2[0x2];
2903         u8         lag_tx_port_affinity[0x04];
2904 
2905         u8         reserved_at_8[0x4];
2906         u8         prio[0x4];
2907         u8         reserved_at_10[0x10];
2908 
2909         u8         reserved_at_20[0x100];
2910 
2911         u8         reserved_at_120[0x8];
2912         u8         transport_domain[0x18];
2913 
2914         u8         reserved_at_140[0x8];
2915         u8         underlay_qpn[0x18];
2916 
2917         u8         reserved_at_160[0x8];
2918         u8         pd[0x18];
2919 
2920         u8         reserved_at_180[0x380];
2921 };
2922 
2923 enum {
2924         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2925         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2926 };
2927 
2928 enum {
2929         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2930         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2931 };
2932 
2933 enum {
2934         MLX5_RX_HASH_FN_NONE           = 0x0,
2935         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2936         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2937 };
2938 
2939 enum {
2940         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2941         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2942 };
2943 
2944 struct mlx5_ifc_tirc_bits {
2945         u8         reserved_at_0[0x20];
2946 
2947         u8         disp_type[0x4];
2948         u8         reserved_at_24[0x1c];
2949 
2950         u8         reserved_at_40[0x40];
2951 
2952         u8         reserved_at_80[0x4];
2953         u8         lro_timeout_period_usecs[0x10];
2954         u8         lro_enable_mask[0x4];
2955         u8         lro_max_ip_payload_size[0x8];
2956 
2957         u8         reserved_at_a0[0x40];
2958 
2959         u8         reserved_at_e0[0x8];
2960         u8         inline_rqn[0x18];
2961 
2962         u8         rx_hash_symmetric[0x1];
2963         u8         reserved_at_101[0x1];
2964         u8         tunneled_offload_en[0x1];
2965         u8         reserved_at_103[0x5];
2966         u8         indirect_table[0x18];
2967 
2968         u8         rx_hash_fn[0x4];
2969         u8         reserved_at_124[0x2];
2970         u8         self_lb_block[0x2];
2971         u8         transport_domain[0x18];
2972 
2973         u8         rx_hash_toeplitz_key[10][0x20];
2974 
2975         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2976 
2977         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2978 
2979         u8         reserved_at_2c0[0x4c0];
2980 };
2981 
2982 enum {
2983         MLX5_SRQC_STATE_GOOD   = 0x0,
2984         MLX5_SRQC_STATE_ERROR  = 0x1,
2985 };
2986 
2987 struct mlx5_ifc_srqc_bits {
2988         u8         state[0x4];
2989         u8         log_srq_size[0x4];
2990         u8         reserved_at_8[0x18];
2991 
2992         u8         wq_signature[0x1];
2993         u8         cont_srq[0x1];
2994         u8         reserved_at_22[0x1];
2995         u8         rlky[0x1];
2996         u8         reserved_at_24[0x1];
2997         u8         log_rq_stride[0x3];
2998         u8         xrcd[0x18];
2999 
3000         u8         page_offset[0x6];
3001         u8         reserved_at_46[0x2];
3002         u8         cqn[0x18];
3003 
3004         u8         reserved_at_60[0x20];
3005 
3006         u8         reserved_at_80[0x2];
3007         u8         log_page_size[0x6];
3008         u8         reserved_at_88[0x18];
3009 
3010         u8         reserved_at_a0[0x20];
3011 
3012         u8         reserved_at_c0[0x8];
3013         u8         pd[0x18];
3014 
3015         u8         lwm[0x10];
3016         u8         wqe_cnt[0x10];
3017 
3018         u8         reserved_at_100[0x40];
3019 
3020         u8         dbr_addr[0x40];
3021 
3022         u8         reserved_at_180[0x80];
3023 };
3024 
3025 enum {
3026         MLX5_SQC_STATE_RST  = 0x0,
3027         MLX5_SQC_STATE_RDY  = 0x1,
3028         MLX5_SQC_STATE_ERR  = 0x3,
3029 };
3030 
3031 struct mlx5_ifc_sqc_bits {
3032         u8         rlky[0x1];
3033         u8         cd_master[0x1];
3034         u8         fre[0x1];
3035         u8         flush_in_error_en[0x1];
3036         u8         allow_multi_pkt_send_wqe[0x1];
3037         u8         min_wqe_inline_mode[0x3];
3038         u8         state[0x4];
3039         u8         reg_umr[0x1];
3040         u8         allow_swp[0x1];
3041         u8         hairpin[0x1];
3042         u8         reserved_at_f[0x11];
3043 
3044         u8         reserved_at_20[0x8];
3045         u8         user_index[0x18];
3046 
3047         u8         reserved_at_40[0x8];
3048         u8         cqn[0x18];
3049 
3050         u8         reserved_at_60[0x8];
3051         u8         hairpin_peer_rq[0x18];
3052 
3053         u8         reserved_at_80[0x10];
3054         u8         hairpin_peer_vhca[0x10];
3055 
3056         u8         reserved_at_a0[0x50];
3057 
3058         u8         packet_pacing_rate_limit_index[0x10];
3059         u8         tis_lst_sz[0x10];
3060         u8         reserved_at_110[0x10];
3061 
3062         u8         reserved_at_120[0x40];
3063 
3064         u8         reserved_at_160[0x8];
3065         u8         tis_num_0[0x18];
3066 
3067         struct mlx5_ifc_wq_bits wq;
3068 };
3069 
3070 enum {
3071         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3072         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3073         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3074         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3075 };
3076 
3077 enum {
3078         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3079         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3080         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3081         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3082 };
3083 
3084 struct mlx5_ifc_scheduling_context_bits {
3085         u8         element_type[0x8];
3086         u8         reserved_at_8[0x18];
3087 
3088         u8         element_attributes[0x20];
3089 
3090         u8         parent_element_id[0x20];
3091 
3092         u8         reserved_at_60[0x40];
3093 
3094         u8         bw_share[0x20];
3095 
3096         u8         max_average_bw[0x20];
3097 
3098         u8         reserved_at_e0[0x120];
3099 };
3100 
3101 struct mlx5_ifc_rqtc_bits {
3102         u8         reserved_at_0[0xa0];
3103 
3104         u8         reserved_at_a0[0x10];
3105         u8         rqt_max_size[0x10];
3106 
3107         u8         reserved_at_c0[0x10];
3108         u8         rqt_actual_size[0x10];
3109 
3110         u8         reserved_at_e0[0x6a0];
3111 
3112         struct mlx5_ifc_rq_num_bits rq_num[0];
3113 };
3114 
3115 enum {
3116         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3117         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3118 };
3119 
3120 enum {
3121         MLX5_RQC_STATE_RST  = 0x0,
3122         MLX5_RQC_STATE_RDY  = 0x1,
3123         MLX5_RQC_STATE_ERR  = 0x3,
3124 };
3125 
3126 struct mlx5_ifc_rqc_bits {
3127         u8         rlky[0x1];
3128         u8         delay_drop_en[0x1];
3129         u8         scatter_fcs[0x1];
3130         u8         vsd[0x1];
3131         u8         mem_rq_type[0x4];
3132         u8         state[0x4];
3133         u8         reserved_at_c[0x1];
3134         u8         flush_in_error_en[0x1];
3135         u8         hairpin[0x1];
3136         u8         reserved_at_f[0x11];
3137 
3138         u8         reserved_at_20[0x8];
3139         u8         user_index[0x18];
3140 
3141         u8         reserved_at_40[0x8];
3142         u8         cqn[0x18];
3143 
3144         u8         counter_set_id[0x8];
3145         u8         reserved_at_68[0x18];
3146 
3147         u8         reserved_at_80[0x8];
3148         u8         rmpn[0x18];
3149 
3150         u8         reserved_at_a0[0x8];
3151         u8         hairpin_peer_sq[0x18];
3152 
3153         u8         reserved_at_c0[0x10];
3154         u8         hairpin_peer_vhca[0x10];
3155 
3156         u8         reserved_at_e0[0xa0];
3157 
3158         struct mlx5_ifc_wq_bits wq;
3159 };
3160 
3161 enum {
3162         MLX5_RMPC_STATE_RDY  = 0x1,
3163         MLX5_RMPC_STATE_ERR  = 0x3,
3164 };
3165 
3166 struct mlx5_ifc_rmpc_bits {
3167         u8         reserved_at_0[0x8];
3168         u8         state[0x4];
3169         u8         reserved_at_c[0x14];
3170 
3171         u8         basic_cyclic_rcv_wqe[0x1];
3172         u8         reserved_at_21[0x1f];
3173 
3174         u8         reserved_at_40[0x140];
3175 
3176         struct mlx5_ifc_wq_bits wq;
3177 };
3178 
3179 struct mlx5_ifc_nic_vport_context_bits {
3180         u8         reserved_at_0[0x5];
3181         u8         min_wqe_inline_mode[0x3];
3182         u8         reserved_at_8[0x15];
3183         u8         disable_mc_local_lb[0x1];
3184         u8         disable_uc_local_lb[0x1];
3185         u8         roce_en[0x1];
3186 
3187         u8         arm_change_event[0x1];
3188         u8         reserved_at_21[0x1a];
3189         u8         event_on_mtu[0x1];
3190         u8         event_on_promisc_change[0x1];
3191         u8         event_on_vlan_change[0x1];
3192         u8         event_on_mc_address_change[0x1];
3193         u8         event_on_uc_address_change[0x1];
3194 
3195         u8         reserved_at_40[0xc];
3196 
3197         u8         affiliation_criteria[0x4];
3198         u8         affiliated_vhca_id[0x10];
3199 
3200         u8         reserved_at_60[0xd0];
3201 
3202         u8         mtu[0x10];
3203 
3204         u8         system_image_guid[0x40];
3205         u8         port_guid[0x40];
3206         u8         node_guid[0x40];
3207 
3208         u8         reserved_at_200[0x140];
3209         u8         qkey_violation_counter[0x10];
3210         u8         reserved_at_350[0x430];
3211 
3212         u8         promisc_uc[0x1];
3213         u8         promisc_mc[0x1];
3214         u8         promisc_all[0x1];
3215         u8         reserved_at_783[0x2];
3216         u8         allowed_list_type[0x3];
3217         u8         reserved_at_788[0xc];
3218         u8         allowed_list_size[0xc];
3219 
3220         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3221 
3222         u8         reserved_at_7e0[0x20];
3223 
3224         u8         current_uc_mac_address[0][0x40];
3225 };
3226 
3227 enum {
3228         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3229         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3230         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3231         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3232         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3233         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3234 };
3235 
3236 struct mlx5_ifc_mkc_bits {
3237         u8         reserved_at_0[0x1];
3238         u8         free[0x1];
3239         u8         reserved_at_2[0x1];
3240         u8         access_mode_4_2[0x3];
3241         u8         reserved_at_6[0x7];
3242         u8         relaxed_ordering_write[0x1];
3243         u8         reserved_at_e[0x1];
3244         u8         small_fence_on_rdma_read_response[0x1];
3245         u8         umr_en[0x1];
3246         u8         a[0x1];
3247         u8         rw[0x1];
3248         u8         rr[0x1];
3249         u8         lw[0x1];
3250         u8         lr[0x1];
3251         u8         access_mode_1_0[0x2];
3252         u8         reserved_at_18[0x8];
3253 
3254         u8         qpn[0x18];
3255         u8         mkey_7_0[0x8];
3256 
3257         u8         reserved_at_40[0x20];
3258 
3259         u8         length64[0x1];
3260         u8         bsf_en[0x1];
3261         u8         sync_umr[0x1];
3262         u8         reserved_at_63[0x2];
3263         u8         expected_sigerr_count[0x1];
3264         u8         reserved_at_66[0x1];
3265         u8         en_rinval[0x1];
3266         u8         pd[0x18];
3267 
3268         u8         start_addr[0x40];
3269 
3270         u8         len[0x40];
3271 
3272         u8         bsf_octword_size[0x20];
3273 
3274         u8         reserved_at_120[0x80];
3275 
3276         u8         translations_octword_size[0x20];
3277 
3278         u8         reserved_at_1c0[0x1b];
3279         u8         log_page_size[0x5];
3280 
3281         u8         reserved_at_1e0[0x20];
3282 };
3283 
3284 struct mlx5_ifc_pkey_bits {
3285         u8         reserved_at_0[0x10];
3286         u8         pkey[0x10];
3287 };
3288 
3289 struct mlx5_ifc_array128_auto_bits {
3290         u8         array128_auto[16][0x8];
3291 };
3292 
3293 struct mlx5_ifc_hca_vport_context_bits {
3294         u8         field_select[0x20];
3295 
3296         u8         reserved_at_20[0xe0];
3297 
3298         u8         sm_virt_aware[0x1];
3299         u8         has_smi[0x1];
3300         u8         has_raw[0x1];
3301         u8         grh_required[0x1];
3302         u8         reserved_at_104[0xc];
3303         u8         port_physical_state[0x4];
3304         u8         vport_state_policy[0x4];
3305         u8         port_state[0x4];
3306         u8         vport_state[0x4];
3307 
3308         u8         reserved_at_120[0x20];
3309 
3310         u8         system_image_guid[0x40];
3311 
3312         u8         port_guid[0x40];
3313 
3314         u8         node_guid[0x40];
3315 
3316         u8         cap_mask1[0x20];
3317 
3318         u8         cap_mask1_field_select[0x20];
3319 
3320         u8         cap_mask2[0x20];
3321 
3322         u8         cap_mask2_field_select[0x20];
3323 
3324         u8         reserved_at_280[0x80];
3325 
3326         u8         lid[0x10];
3327         u8         reserved_at_310[0x4];
3328         u8         init_type_reply[0x4];
3329         u8         lmc[0x3];
3330         u8         subnet_timeout[0x5];
3331 
3332         u8         sm_lid[0x10];
3333         u8         sm_sl[0x4];
3334         u8         reserved_at_334[0xc];
3335 
3336         u8         qkey_violation_counter[0x10];
3337         u8         pkey_violation_counter[0x10];
3338 
3339         u8         reserved_at_360[0xca0];
3340 };
3341 
3342 struct mlx5_ifc_esw_vport_context_bits {
3343         u8         fdb_to_vport_reg_c[0x1];
3344         u8         reserved_at_1[0x2];
3345         u8         vport_svlan_strip[0x1];
3346         u8         vport_cvlan_strip[0x1];
3347         u8         vport_svlan_insert[0x1];
3348         u8         vport_cvlan_insert[0x2];
3349         u8         fdb_to_vport_reg_c_id[0x8];
3350         u8         reserved_at_10[0x10];
3351 
3352         u8         reserved_at_20[0x20];
3353 
3354         u8         svlan_cfi[0x1];
3355         u8         svlan_pcp[0x3];
3356         u8         svlan_id[0xc];
3357         u8         cvlan_cfi[0x1];
3358         u8         cvlan_pcp[0x3];
3359         u8         cvlan_id[0xc];
3360 
3361         u8         reserved_at_60[0x720];
3362 
3363         u8         sw_steering_vport_icm_address_rx[0x40];
3364 
3365         u8         sw_steering_vport_icm_address_tx[0x40];
3366 };
3367 
3368 enum {
3369         MLX5_EQC_STATUS_OK                = 0x0,
3370         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3371 };
3372 
3373 enum {
3374         MLX5_EQC_ST_ARMED  = 0x9,
3375         MLX5_EQC_ST_FIRED  = 0xa,
3376 };
3377 
3378 struct mlx5_ifc_eqc_bits {
3379         u8         status[0x4];
3380         u8         reserved_at_4[0x9];
3381         u8         ec[0x1];
3382         u8         oi[0x1];
3383         u8         reserved_at_f[0x5];
3384         u8         st[0x4];
3385         u8         reserved_at_18[0x8];
3386 
3387         u8         reserved_at_20[0x20];
3388 
3389         u8         reserved_at_40[0x14];
3390         u8         page_offset[0x6];
3391         u8         reserved_at_5a[0x6];
3392 
3393         u8         reserved_at_60[0x3];
3394         u8         log_eq_size[0x5];
3395         u8         uar_page[0x18];
3396 
3397         u8         reserved_at_80[0x20];
3398 
3399         u8         reserved_at_a0[0x18];
3400         u8         intr[0x8];
3401 
3402         u8         reserved_at_c0[0x3];
3403         u8         log_page_size[0x5];
3404         u8         reserved_at_c8[0x18];
3405 
3406         u8         reserved_at_e0[0x60];
3407 
3408         u8         reserved_at_140[0x8];
3409         u8         consumer_counter[0x18];
3410 
3411         u8         reserved_at_160[0x8];
3412         u8         producer_counter[0x18];
3413 
3414         u8         reserved_at_180[0x80];
3415 };
3416 
3417 enum {
3418         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3419         MLX5_DCTC_STATE_DRAINING  = 0x1,
3420         MLX5_DCTC_STATE_DRAINED   = 0x2,
3421 };
3422 
3423 enum {
3424         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3425         MLX5_DCTC_CS_RES_NA         = 0x1,
3426         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3427 };
3428 
3429 enum {
3430         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3431         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3432         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3433         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3434         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3435 };
3436 
3437 struct mlx5_ifc_dctc_bits {
3438         u8         reserved_at_0[0x4];
3439         u8         state[0x4];
3440         u8         reserved_at_8[0x18];
3441 
3442         u8         reserved_at_20[0x8];
3443         u8         user_index[0x18];
3444 
3445         u8         reserved_at_40[0x8];
3446         u8         cqn[0x18];
3447 
3448         u8         counter_set_id[0x8];
3449         u8         atomic_mode[0x4];
3450         u8         rre[0x1];
3451         u8         rwe[0x1];
3452         u8         rae[0x1];
3453         u8         atomic_like_write_en[0x1];
3454         u8         latency_sensitive[0x1];
3455         u8         rlky[0x1];
3456         u8         free_ar[0x1];
3457         u8         reserved_at_73[0xd];
3458 
3459         u8         reserved_at_80[0x8];
3460         u8         cs_res[0x8];
3461         u8         reserved_at_90[0x3];
3462         u8         min_rnr_nak[0x5];
3463         u8         reserved_at_98[0x8];
3464 
3465         u8         reserved_at_a0[0x8];
3466         u8         srqn_xrqn[0x18];
3467 
3468         u8         reserved_at_c0[0x8];
3469         u8         pd[0x18];
3470 
3471         u8         tclass[0x8];
3472         u8         reserved_at_e8[0x4];
3473         u8         flow_label[0x14];
3474 
3475         u8         dc_access_key[0x40];
3476 
3477         u8         reserved_at_140[0x5];
3478         u8         mtu[0x3];
3479         u8         port[0x8];
3480         u8         pkey_index[0x10];
3481 
3482         u8         reserved_at_160[0x8];
3483         u8         my_addr_index[0x8];
3484         u8         reserved_at_170[0x8];
3485         u8         hop_limit[0x8];
3486 
3487         u8         dc_access_key_violation_count[0x20];
3488 
3489         u8         reserved_at_1a0[0x14];
3490         u8         dei_cfi[0x1];
3491         u8         eth_prio[0x3];
3492         u8         ecn[0x2];
3493         u8         dscp[0x6];
3494 
3495         u8         reserved_at_1c0[0x40];
3496 };
3497 
3498 enum {
3499         MLX5_CQC_STATUS_OK             = 0x0,
3500         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3501         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3502 };
3503 
3504 enum {
3505         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3506         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3507 };
3508 
3509 enum {
3510         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3511         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3512         MLX5_CQC_ST_FIRED                                 = 0xa,
3513 };
3514 
3515 enum {
3516         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3517         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3518         MLX5_CQ_PERIOD_NUM_MODES
3519 };
3520 
3521 struct mlx5_ifc_cqc_bits {
3522         u8         status[0x4];
3523         u8         reserved_at_4[0x2];
3524         u8         dbr_umem_valid[0x1];
3525         u8         reserved_at_7[0x1];
3526         u8         cqe_sz[0x3];
3527         u8         cc[0x1];
3528         u8         reserved_at_c[0x1];
3529         u8         scqe_break_moderation_en[0x1];
3530         u8         oi[0x1];
3531         u8         cq_period_mode[0x2];
3532         u8         cqe_comp_en[0x1];
3533         u8         mini_cqe_res_format[0x2];
3534         u8         st[0x4];
3535         u8         reserved_at_18[0x8];
3536 
3537         u8         reserved_at_20[0x20];
3538 
3539         u8         reserved_at_40[0x14];
3540         u8         page_offset[0x6];
3541         u8         reserved_at_5a[0x6];
3542 
3543         u8         reserved_at_60[0x3];
3544         u8         log_cq_size[0x5];
3545         u8         uar_page[0x18];
3546 
3547         u8         reserved_at_80[0x4];
3548         u8         cq_period[0xc];
3549         u8         cq_max_count[0x10];
3550 
3551         u8         reserved_at_a0[0x18];
3552         u8         c_eqn[0x8];
3553 
3554         u8         reserved_at_c0[0x3];
3555         u8         log_page_size[0x5];
3556         u8         reserved_at_c8[0x18];
3557 
3558         u8         reserved_at_e0[0x20];
3559 
3560         u8         reserved_at_100[0x8];
3561         u8         last_notified_index[0x18];
3562 
3563         u8         reserved_at_120[0x8];
3564         u8         last_solicit_index[0x18];
3565 
3566         u8         reserved_at_140[0x8];
3567         u8         consumer_counter[0x18];
3568 
3569         u8         reserved_at_160[0x8];
3570         u8         producer_counter[0x18];
3571 
3572         u8         reserved_at_180[0x40];
3573 
3574         u8         dbr_addr[0x40];
3575 };
3576 
3577 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3578         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3579         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3580         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3581         u8         reserved_at_0[0x800];
3582 };
3583 
3584 struct mlx5_ifc_query_adapter_param_block_bits {
3585         u8         reserved_at_0[0xc0];
3586 
3587         u8         reserved_at_c0[0x8];
3588         u8         ieee_vendor_id[0x18];
3589 
3590         u8         reserved_at_e0[0x10];
3591         u8         vsd_vendor_id[0x10];
3592 
3593         u8         vsd[208][0x8];
3594 
3595         u8         vsd_contd_psid[16][0x8];
3596 };
3597 
3598 enum {
3599         MLX5_XRQC_STATE_GOOD   = 0x0,
3600         MLX5_XRQC_STATE_ERROR  = 0x1,
3601 };
3602 
3603 enum {
3604         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3605         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3606 };
3607 
3608 enum {
3609         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3610 };
3611 
3612 struct mlx5_ifc_tag_matching_topology_context_bits {
3613         u8         log_matching_list_sz[0x4];
3614         u8         reserved_at_4[0xc];
3615         u8         append_next_index[0x10];
3616 
3617         u8         sw_phase_cnt[0x10];
3618         u8         hw_phase_cnt[0x10];
3619 
3620         u8         reserved_at_40[0x40];
3621 };
3622 
3623 struct mlx5_ifc_xrqc_bits {
3624         u8         state[0x4];
3625         u8         rlkey[0x1];
3626         u8         reserved_at_5[0xf];
3627         u8         topology[0x4];
3628         u8         reserved_at_18[0x4];
3629         u8         offload[0x4];
3630 
3631         u8         reserved_at_20[0x8];
3632         u8         user_index[0x18];
3633 
3634         u8         reserved_at_40[0x8];
3635         u8         cqn[0x18];
3636 
3637         u8         reserved_at_60[0xa0];
3638 
3639         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3640 
3641         u8         reserved_at_180[0x280];
3642 
3643         struct mlx5_ifc_wq_bits wq;
3644 };
3645 
3646 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3647         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3648         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3649         u8         reserved_at_0[0x20];
3650 };
3651 
3652 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3653         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3654         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3655         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3656         u8         reserved_at_0[0x20];
3657 };
3658 
3659 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3660         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3661         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3662         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3663         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3664         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3665         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3666         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3667         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3668         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3669         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3670         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3671         u8         reserved_at_0[0x7c0];
3672 };
3673 
3674 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3675         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3676         u8         reserved_at_0[0x7c0];
3677 };
3678 
3679 union mlx5_ifc_event_auto_bits {
3680         struct mlx5_ifc_comp_event_bits comp_event;
3681         struct mlx5_ifc_dct_events_bits dct_events;
3682         struct mlx5_ifc_qp_events_bits qp_events;
3683         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3684         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3685         struct mlx5_ifc_cq_error_bits cq_error;
3686         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3687         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3688         struct mlx5_ifc_gpio_event_bits gpio_event;
3689         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3690         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3691         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3692         u8         reserved_at_0[0xe0];
3693 };
3694 
3695 struct mlx5_ifc_health_buffer_bits {
3696         u8         reserved_at_0[0x100];
3697 
3698         u8         assert_existptr[0x20];
3699 
3700         u8         assert_callra[0x20];
3701 
3702         u8         reserved_at_140[0x40];
3703 
3704         u8         fw_version[0x20];
3705 
3706         u8         hw_id[0x20];
3707 
3708         u8         reserved_at_1c0[0x20];
3709 
3710         u8         irisc_index[0x8];
3711         u8         synd[0x8];
3712         u8         ext_synd[0x10];
3713 };
3714 
3715 struct mlx5_ifc_register_loopback_control_bits {
3716         u8         no_lb[0x1];
3717         u8         reserved_at_1[0x7];
3718         u8         port[0x8];
3719         u8         reserved_at_10[0x10];
3720 
3721         u8         reserved_at_20[0x60];
3722 };
3723 
3724 struct mlx5_ifc_vport_tc_element_bits {
3725         u8         traffic_class[0x4];
3726         u8         reserved_at_4[0xc];
3727         u8         vport_number[0x10];
3728 };
3729 
3730 struct mlx5_ifc_vport_element_bits {
3731         u8         reserved_at_0[0x10];
3732         u8         vport_number[0x10];
3733 };
3734 
3735 enum {
3736         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3737         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3738         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3739 };
3740 
3741 struct mlx5_ifc_tsar_element_bits {
3742         u8         reserved_at_0[0x8];
3743         u8         tsar_type[0x8];
3744         u8         reserved_at_10[0x10];
3745 };
3746 
3747 enum {
3748         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3749         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3750 };
3751 
3752 struct mlx5_ifc_teardown_hca_out_bits {
3753         u8         status[0x8];
3754         u8         reserved_at_8[0x18];
3755 
3756         u8         syndrome[0x20];
3757 
3758         u8         reserved_at_40[0x3f];
3759 
3760         u8         state[0x1];
3761 };
3762 
3763 enum {
3764         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3765         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3766         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3767 };
3768 
3769 struct mlx5_ifc_teardown_hca_in_bits {
3770         u8         opcode[0x10];
3771         u8         reserved_at_10[0x10];
3772 
3773         u8         reserved_at_20[0x10];
3774         u8         op_mod[0x10];
3775 
3776         u8         reserved_at_40[0x10];
3777         u8         profile[0x10];
3778 
3779         u8         reserved_at_60[0x20];
3780 };
3781 
3782 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3783         u8         status[0x8];
3784         u8         reserved_at_8[0x18];
3785 
3786         u8         syndrome[0x20];
3787 
3788         u8         reserved_at_40[0x40];
3789 };
3790 
3791 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3792         u8         opcode[0x10];
3793         u8         uid[0x10];
3794 
3795         u8         reserved_at_20[0x10];
3796         u8         op_mod[0x10];
3797 
3798         u8         reserved_at_40[0x8];
3799         u8         qpn[0x18];
3800 
3801         u8         reserved_at_60[0x20];
3802 
3803         u8         opt_param_mask[0x20];
3804 
3805         u8         reserved_at_a0[0x20];
3806 
3807         struct mlx5_ifc_qpc_bits qpc;
3808 
3809         u8         reserved_at_800[0x80];
3810 };
3811 
3812 struct mlx5_ifc_sqd2rts_qp_out_bits {
3813         u8         status[0x8];
3814         u8         reserved_at_8[0x18];
3815 
3816         u8         syndrome[0x20];
3817 
3818         u8         reserved_at_40[0x40];
3819 };
3820 
3821 struct mlx5_ifc_sqd2rts_qp_in_bits {
3822         u8         opcode[0x10];
3823         u8         uid[0x10];
3824 
3825         u8         reserved_at_20[0x10];
3826         u8         op_mod[0x10];
3827 
3828         u8         reserved_at_40[0x8];
3829         u8         qpn[0x18];
3830 
3831         u8         reserved_at_60[0x20];
3832 
3833         u8         opt_param_mask[0x20];
3834 
3835         u8         reserved_at_a0[0x20];
3836 
3837         struct mlx5_ifc_qpc_bits qpc;
3838 
3839         u8         reserved_at_800[0x80];
3840 };
3841 
3842 struct mlx5_ifc_set_roce_address_out_bits {
3843         u8         status[0x8];
3844         u8         reserved_at_8[0x18];
3845 
3846         u8         syndrome[0x20];
3847 
3848         u8         reserved_at_40[0x40];
3849 };
3850 
3851 struct mlx5_ifc_set_roce_address_in_bits {
3852         u8         opcode[0x10];
3853         u8         reserved_at_10[0x10];
3854 
3855         u8         reserved_at_20[0x10];
3856         u8         op_mod[0x10];
3857 
3858         u8         roce_address_index[0x10];
3859         u8         reserved_at_50[0xc];
3860         u8         vhca_port_num[0x4];
3861 
3862         u8         reserved_at_60[0x20];
3863 
3864         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3865 };
3866 
3867 struct mlx5_ifc_set_mad_demux_out_bits {
3868         u8         status[0x8];
3869         u8         reserved_at_8[0x18];
3870 
3871         u8         syndrome[0x20];
3872 
3873         u8         reserved_at_40[0x40];
3874 };
3875 
3876 enum {
3877         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3878         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3879 };
3880 
3881 struct mlx5_ifc_set_mad_demux_in_bits {
3882         u8         opcode[0x10];
3883         u8         reserved_at_10[0x10];
3884 
3885         u8         reserved_at_20[0x10];
3886         u8         op_mod[0x10];
3887 
3888         u8         reserved_at_40[0x20];
3889 
3890         u8         reserved_at_60[0x6];
3891         u8         demux_mode[0x2];
3892         u8         reserved_at_68[0x18];
3893 };
3894 
3895 struct mlx5_ifc_set_l2_table_entry_out_bits {
3896         u8         status[0x8];
3897         u8         reserved_at_8[0x18];
3898 
3899         u8         syndrome[0x20];
3900 
3901         u8         reserved_at_40[0x40];
3902 };
3903 
3904 struct mlx5_ifc_set_l2_table_entry_in_bits {
3905         u8         opcode[0x10];
3906         u8         reserved_at_10[0x10];
3907 
3908         u8         reserved_at_20[0x10];
3909         u8         op_mod[0x10];
3910 
3911         u8         reserved_at_40[0x60];
3912 
3913         u8         reserved_at_a0[0x8];
3914         u8         table_index[0x18];
3915 
3916         u8         reserved_at_c0[0x20];
3917 
3918         u8         reserved_at_e0[0x13];
3919         u8         vlan_valid[0x1];
3920         u8         vlan[0xc];
3921 
3922         struct mlx5_ifc_mac_address_layout_bits mac_address;
3923 
3924         u8         reserved_at_140[0xc0];
3925 };
3926 
3927 struct mlx5_ifc_set_issi_out_bits {
3928         u8         status[0x8];
3929         u8         reserved_at_8[0x18];
3930 
3931         u8         syndrome[0x20];
3932 
3933         u8         reserved_at_40[0x40];
3934 };
3935 
3936 struct mlx5_ifc_set_issi_in_bits {
3937         u8         opcode[0x10];
3938         u8         reserved_at_10[0x10];
3939 
3940         u8         reserved_at_20[0x10];
3941         u8         op_mod[0x10];
3942 
3943         u8         reserved_at_40[0x10];
3944         u8         current_issi[0x10];
3945 
3946         u8         reserved_at_60[0x20];
3947 };
3948 
3949 struct mlx5_ifc_set_hca_cap_out_bits {
3950         u8         status[0x8];
3951         u8         reserved_at_8[0x18];
3952 
3953         u8         syndrome[0x20];
3954 
3955         u8         reserved_at_40[0x40];
3956 };
3957 
3958 struct mlx5_ifc_set_hca_cap_in_bits {
3959         u8         opcode[0x10];
3960         u8         reserved_at_10[0x10];
3961 
3962         u8         reserved_at_20[0x10];
3963         u8         op_mod[0x10];
3964 
3965         u8         reserved_at_40[0x40];
3966 
3967         union mlx5_ifc_hca_cap_union_bits capability;
3968 };
3969 
3970 enum {
3971         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3972         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3973         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3974         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3975 };
3976 
3977 struct mlx5_ifc_set_fte_out_bits {
3978         u8         status[0x8];
3979         u8         reserved_at_8[0x18];
3980 
3981         u8         syndrome[0x20];
3982 
3983         u8         reserved_at_40[0x40];
3984 };
3985 
3986 struct mlx5_ifc_set_fte_in_bits {
3987         u8         opcode[0x10];
3988         u8         reserved_at_10[0x10];
3989 
3990         u8         reserved_at_20[0x10];
3991         u8         op_mod[0x10];
3992 
3993         u8         other_vport[0x1];
3994         u8         reserved_at_41[0xf];
3995         u8         vport_number[0x10];
3996 
3997         u8         reserved_at_60[0x20];
3998 
3999         u8         table_type[0x8];
4000         u8         reserved_at_88[0x18];
4001 
4002         u8         reserved_at_a0[0x8];
4003         u8         table_id[0x18];
4004 
4005         u8         reserved_at_c0[0x18];
4006         u8         modify_enable_mask[0x8];
4007 
4008         u8         reserved_at_e0[0x20];
4009 
4010         u8         flow_index[0x20];
4011 
4012         u8         reserved_at_120[0xe0];
4013 
4014         struct mlx5_ifc_flow_context_bits flow_context;
4015 };
4016 
4017 struct mlx5_ifc_rts2rts_qp_out_bits {
4018         u8         status[0x8];
4019         u8         reserved_at_8[0x18];
4020 
4021         u8         syndrome[0x20];
4022 
4023         u8         reserved_at_40[0x40];
4024 };
4025 
4026 struct mlx5_ifc_rts2rts_qp_in_bits {
4027         u8         opcode[0x10];
4028         u8         uid[0x10];
4029 
4030         u8         reserved_at_20[0x10];
4031         u8         op_mod[0x10];
4032 
4033         u8         reserved_at_40[0x8];
4034         u8         qpn[0x18];
4035 
4036         u8         reserved_at_60[0x20];
4037 
4038         u8         opt_param_mask[0x20];
4039 
4040         u8         reserved_at_a0[0x20];
4041 
4042         struct mlx5_ifc_qpc_bits qpc;
4043 
4044         u8         reserved_at_800[0x80];
4045 };
4046 
4047 struct mlx5_ifc_rtr2rts_qp_out_bits {
4048         u8         status[0x8];
4049         u8         reserved_at_8[0x18];
4050 
4051         u8         syndrome[0x20];
4052 
4053         u8         reserved_at_40[0x40];
4054 };
4055 
4056 struct mlx5_ifc_rtr2rts_qp_in_bits {
4057         u8         opcode[0x10];
4058         u8         uid[0x10];
4059 
4060         u8         reserved_at_20[0x10];
4061         u8         op_mod[0x10];
4062 
4063         u8         reserved_at_40[0x8];
4064         u8         qpn[0x18];
4065 
4066         u8         reserved_at_60[0x20];
4067 
4068         u8         opt_param_mask[0x20];
4069 
4070         u8         reserved_at_a0[0x20];
4071 
4072         struct mlx5_ifc_qpc_bits qpc;
4073 
4074         u8         reserved_at_800[0x80];
4075 };
4076 
4077 struct mlx5_ifc_rst2init_qp_out_bits {
4078         u8         status[0x8];
4079         u8         reserved_at_8[0x18];
4080 
4081         u8         syndrome[0x20];
4082 
4083         u8         reserved_at_40[0x40];
4084 };
4085 
4086 struct mlx5_ifc_rst2init_qp_in_bits {
4087         u8         opcode[0x10];
4088         u8         uid[0x10];
4089 
4090         u8         reserved_at_20[0x10];
4091         u8         op_mod[0x10];
4092 
4093         u8         reserved_at_40[0x8];
4094         u8         qpn[0x18];
4095 
4096         u8         reserved_at_60[0x20];
4097 
4098         u8         opt_param_mask[0x20];
4099 
4100         u8         reserved_at_a0[0x20];
4101 
4102         struct mlx5_ifc_qpc_bits qpc;
4103 
4104         u8         reserved_at_800[0x80];
4105 };
4106 
4107 struct mlx5_ifc_query_xrq_out_bits {
4108         u8         status[0x8];
4109         u8         reserved_at_8[0x18];
4110 
4111         u8         syndrome[0x20];
4112 
4113         u8         reserved_at_40[0x40];
4114 
4115         struct mlx5_ifc_xrqc_bits xrq_context;
4116 };
4117 
4118 struct mlx5_ifc_query_xrq_in_bits {
4119         u8         opcode[0x10];
4120         u8         reserved_at_10[0x10];
4121 
4122         u8         reserved_at_20[0x10];
4123         u8         op_mod[0x10];
4124 
4125         u8         reserved_at_40[0x8];
4126         u8         xrqn[0x18];
4127 
4128         u8         reserved_at_60[0x20];
4129 };
4130 
4131 struct mlx5_ifc_query_xrc_srq_out_bits {
4132         u8         status[0x8];
4133         u8         reserved_at_8[0x18];
4134 
4135         u8         syndrome[0x20];
4136 
4137         u8         reserved_at_40[0x40];
4138 
4139         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4140 
4141         u8         reserved_at_280[0x600];
4142 
4143         u8         pas[0][0x40];
4144 };
4145 
4146 struct mlx5_ifc_query_xrc_srq_in_bits {
4147         u8         opcode[0x10];
4148         u8         reserved_at_10[0x10];
4149 
4150         u8         reserved_at_20[0x10];
4151         u8         op_mod[0x10];
4152 
4153         u8         reserved_at_40[0x8];
4154         u8         xrc_srqn[0x18];
4155 
4156         u8         reserved_at_60[0x20];
4157 };
4158 
4159 enum {
4160         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4161         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4162 };
4163 
4164 struct mlx5_ifc_query_vport_state_out_bits {
4165         u8         status[0x8];
4166         u8         reserved_at_8[0x18];
4167 
4168         u8         syndrome[0x20];
4169 
4170         u8         reserved_at_40[0x20];
4171 
4172         u8         reserved_at_60[0x18];
4173         u8         admin_state[0x4];
4174         u8         state[0x4];
4175 };
4176 
4177 enum {
4178         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4179         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4180 };
4181 
4182 struct mlx5_ifc_arm_monitor_counter_in_bits {
4183         u8         opcode[0x10];
4184         u8         uid[0x10];
4185 
4186         u8         reserved_at_20[0x10];
4187         u8         op_mod[0x10];
4188 
4189         u8         reserved_at_40[0x20];
4190 
4191         u8         reserved_at_60[0x20];
4192 };
4193 
4194 struct mlx5_ifc_arm_monitor_counter_out_bits {
4195         u8         status[0x8];
4196         u8         reserved_at_8[0x18];
4197 
4198         u8         syndrome[0x20];
4199 
4200         u8         reserved_at_40[0x40];
4201 };
4202 
4203 enum {
4204         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4205         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4206 };
4207 
4208 enum mlx5_monitor_counter_ppcnt {
4209         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4210         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4211         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4212         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4213         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4214         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4215 };
4216 
4217 enum {
4218         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4219 };
4220 
4221 struct mlx5_ifc_monitor_counter_output_bits {
4222         u8         reserved_at_0[0x4];
4223         u8         type[0x4];
4224         u8         reserved_at_8[0x8];
4225         u8         counter[0x10];
4226 
4227         u8         counter_group_id[0x20];
4228 };
4229 
4230 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4231 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4232 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4233                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4234 
4235 struct mlx5_ifc_set_monitor_counter_in_bits {
4236         u8         opcode[0x10];
4237         u8         uid[0x10];
4238 
4239         u8         reserved_at_20[0x10];
4240         u8         op_mod[0x10];
4241 
4242         u8         reserved_at_40[0x10];
4243         u8         num_of_counters[0x10];
4244 
4245         u8         reserved_at_60[0x20];
4246 
4247         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4248 };
4249 
4250 struct mlx5_ifc_set_monitor_counter_out_bits {
4251         u8         status[0x8];
4252         u8         reserved_at_8[0x18];
4253 
4254         u8         syndrome[0x20];
4255 
4256         u8         reserved_at_40[0x40];
4257 };
4258 
4259 struct mlx5_ifc_query_vport_state_in_bits {
4260         u8         opcode[0x10];
4261         u8         reserved_at_10[0x10];
4262 
4263         u8         reserved_at_20[0x10];
4264         u8         op_mod[0x10];
4265 
4266         u8         other_vport[0x1];
4267         u8         reserved_at_41[0xf];
4268         u8         vport_number[0x10];
4269 
4270         u8         reserved_at_60[0x20];
4271 };
4272 
4273 struct mlx5_ifc_query_vnic_env_out_bits {
4274         u8         status[0x8];
4275         u8         reserved_at_8[0x18];
4276 
4277         u8         syndrome[0x20];
4278 
4279         u8         reserved_at_40[0x40];
4280 
4281         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4282 };
4283 
4284 enum {
4285         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4286 };
4287 
4288 struct mlx5_ifc_query_vnic_env_in_bits {
4289         u8         opcode[0x10];
4290         u8         reserved_at_10[0x10];
4291 
4292         u8         reserved_at_20[0x10];
4293         u8         op_mod[0x10];
4294 
4295         u8         other_vport[0x1];
4296         u8         reserved_at_41[0xf];
4297         u8         vport_number[0x10];
4298 
4299         u8         reserved_at_60[0x20];
4300 };
4301 
4302 struct mlx5_ifc_query_vport_counter_out_bits {
4303         u8         status[0x8];
4304         u8         reserved_at_8[0x18];
4305 
4306         u8         syndrome[0x20];
4307 
4308         u8         reserved_at_40[0x40];
4309 
4310         struct mlx5_ifc_traffic_counter_bits received_errors;
4311 
4312         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4313 
4314         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4315 
4316         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4317 
4318         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4319 
4320         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4321 
4322         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4323 
4324         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4325 
4326         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4327 
4328         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4329 
4330         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4331 
4332         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4333 
4334         u8         reserved_at_680[0xa00];
4335 };
4336 
4337 enum {
4338         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4339 };
4340 
4341 struct mlx5_ifc_query_vport_counter_in_bits {
4342         u8         opcode[0x10];
4343         u8         reserved_at_10[0x10];
4344 
4345         u8         reserved_at_20[0x10];
4346         u8         op_mod[0x10];
4347 
4348         u8         other_vport[0x1];
4349         u8         reserved_at_41[0xb];
4350         u8         port_num[0x4];
4351         u8         vport_number[0x10];
4352 
4353         u8         reserved_at_60[0x60];
4354 
4355         u8         clear[0x1];
4356         u8         reserved_at_c1[0x1f];
4357 
4358         u8         reserved_at_e0[0x20];
4359 };
4360 
4361 struct mlx5_ifc_query_tis_out_bits {
4362         u8         status[0x8];
4363         u8         reserved_at_8[0x18];
4364 
4365         u8         syndrome[0x20];
4366 
4367         u8         reserved_at_40[0x40];
4368 
4369         struct mlx5_ifc_tisc_bits tis_context;
4370 };
4371 
4372 struct mlx5_ifc_query_tis_in_bits {
4373         u8         opcode[0x10];
4374         u8         reserved_at_10[0x10];
4375 
4376         u8         reserved_at_20[0x10];
4377         u8         op_mod[0x10];
4378 
4379         u8         reserved_at_40[0x8];
4380         u8         tisn[0x18];
4381 
4382         u8         reserved_at_60[0x20];
4383 };
4384 
4385 struct mlx5_ifc_query_tir_out_bits {
4386         u8         status[0x8];
4387         u8         reserved_at_8[0x18];
4388 
4389         u8         syndrome[0x20];
4390 
4391         u8         reserved_at_40[0xc0];
4392 
4393         struct mlx5_ifc_tirc_bits tir_context;
4394 };
4395 
4396 struct mlx5_ifc_query_tir_in_bits {
4397         u8         opcode[0x10];
4398         u8         reserved_at_10[0x10];
4399 
4400         u8         reserved_at_20[0x10];
4401         u8         op_mod[0x10];
4402 
4403         u8         reserved_at_40[0x8];
4404         u8         tirn[0x18];
4405 
4406         u8         reserved_at_60[0x20];
4407 };
4408 
4409 struct mlx5_ifc_query_srq_out_bits {
4410         u8         status[0x8];
4411         u8         reserved_at_8[0x18];
4412 
4413         u8         syndrome[0x20];
4414 
4415         u8         reserved_at_40[0x40];
4416 
4417         struct mlx5_ifc_srqc_bits srq_context_entry;
4418 
4419         u8         reserved_at_280[0x600];
4420 
4421         u8         pas[0][0x40];
4422 };
4423 
4424 struct mlx5_ifc_query_srq_in_bits {
4425         u8         opcode[0x10];
4426         u8         reserved_at_10[0x10];
4427 
4428         u8         reserved_at_20[0x10];
4429         u8         op_mod[0x10];
4430 
4431         u8         reserved_at_40[0x8];
4432         u8         srqn[0x18];
4433 
4434         u8         reserved_at_60[0x20];
4435 };
4436 
4437 struct mlx5_ifc_query_sq_out_bits {
4438         u8         status[0x8];
4439         u8         reserved_at_8[0x18];
4440 
4441         u8         syndrome[0x20];
4442 
4443         u8         reserved_at_40[0xc0];
4444 
4445         struct mlx5_ifc_sqc_bits sq_context;
4446 };
4447 
4448 struct mlx5_ifc_query_sq_in_bits {
4449         u8         opcode[0x10];
4450         u8         reserved_at_10[0x10];
4451 
4452         u8         reserved_at_20[0x10];
4453         u8         op_mod[0x10];
4454 
4455         u8         reserved_at_40[0x8];
4456         u8         sqn[0x18];
4457 
4458         u8         reserved_at_60[0x20];
4459 };
4460 
4461 struct mlx5_ifc_query_special_contexts_out_bits {
4462         u8         status[0x8];
4463         u8         reserved_at_8[0x18];
4464 
4465         u8         syndrome[0x20];
4466 
4467         u8         dump_fill_mkey[0x20];
4468 
4469         u8         resd_lkey[0x20];
4470 
4471         u8         null_mkey[0x20];
4472 
4473         u8         reserved_at_a0[0x60];
4474 };
4475 
4476 struct mlx5_ifc_query_special_contexts_in_bits {
4477         u8         opcode[0x10];
4478         u8         reserved_at_10[0x10];
4479 
4480         u8         reserved_at_20[0x10];
4481         u8         op_mod[0x10];
4482 
4483         u8         reserved_at_40[0x40];
4484 };
4485 
4486 struct mlx5_ifc_query_scheduling_element_out_bits {
4487         u8         opcode[0x10];
4488         u8         reserved_at_10[0x10];
4489 
4490         u8         reserved_at_20[0x10];
4491         u8         op_mod[0x10];
4492 
4493         u8         reserved_at_40[0xc0];
4494 
4495         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4496 
4497         u8         reserved_at_300[0x100];
4498 };
4499 
4500 enum {
4501         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4502 };
4503 
4504 struct mlx5_ifc_query_scheduling_element_in_bits {
4505         u8         opcode[0x10];
4506         u8         reserved_at_10[0x10];
4507 
4508         u8         reserved_at_20[0x10];
4509         u8         op_mod[0x10];
4510 
4511         u8         scheduling_hierarchy[0x8];
4512         u8         reserved_at_48[0x18];
4513 
4514         u8         scheduling_element_id[0x20];
4515 
4516         u8         reserved_at_80[0x180];
4517 };
4518 
4519 struct mlx5_ifc_query_rqt_out_bits {
4520         u8         status[0x8];
4521         u8         reserved_at_8[0x18];
4522 
4523         u8         syndrome[0x20];
4524 
4525         u8         reserved_at_40[0xc0];
4526 
4527         struct mlx5_ifc_rqtc_bits rqt_context;
4528 };
4529 
4530 struct mlx5_ifc_query_rqt_in_bits {
4531         u8         opcode[0x10];
4532         u8         reserved_at_10[0x10];
4533 
4534         u8         reserved_at_20[0x10];
4535         u8         op_mod[0x10];
4536 
4537         u8         reserved_at_40[0x8];
4538         u8         rqtn[0x18];
4539 
4540         u8         reserved_at_60[0x20];
4541 };
4542 
4543 struct mlx5_ifc_query_rq_out_bits {
4544         u8         status[0x8];
4545         u8         reserved_at_8[0x18];
4546 
4547         u8         syndrome[0x20];
4548 
4549         u8         reserved_at_40[0xc0];
4550 
4551         struct mlx5_ifc_rqc_bits rq_context;
4552 };
4553 
4554 struct mlx5_ifc_query_rq_in_bits {
4555         u8         opcode[0x10];
4556         u8         reserved_at_10[0x10];
4557 
4558         u8         reserved_at_20[0x10];
4559         u8         op_mod[0x10];
4560 
4561         u8         reserved_at_40[0x8];
4562         u8         rqn[0x18];
4563 
4564         u8         reserved_at_60[0x20];
4565 };
4566 
4567 struct mlx5_ifc_query_roce_address_out_bits {
4568         u8         status[0x8];
4569         u8         reserved_at_8[0x18];
4570 
4571         u8         syndrome[0x20];
4572 
4573         u8         reserved_at_40[0x40];
4574 
4575         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4576 };
4577 
4578 struct mlx5_ifc_query_roce_address_in_bits {
4579         u8         opcode[0x10];
4580         u8         reserved_at_10[0x10];
4581 
4582         u8         reserved_at_20[0x10];
4583         u8         op_mod[0x10];
4584 
4585         u8         roce_address_index[0x10];
4586         u8         reserved_at_50[0xc];
4587         u8         vhca_port_num[0x4];
4588 
4589         u8         reserved_at_60[0x20];
4590 };
4591 
4592 struct mlx5_ifc_query_rmp_out_bits {
4593         u8         status[0x8];
4594         u8         reserved_at_8[0x18];
4595 
4596         u8         syndrome[0x20];
4597 
4598         u8         reserved_at_40[0xc0];
4599 
4600         struct mlx5_ifc_rmpc_bits rmp_context;
4601 };
4602 
4603 struct mlx5_ifc_query_rmp_in_bits {
4604         u8         opcode[0x10];
4605         u8         reserved_at_10[0x10];
4606 
4607         u8         reserved_at_20[0x10];
4608         u8         op_mod[0x10];
4609 
4610         u8         reserved_at_40[0x8];
4611         u8         rmpn[0x18];
4612 
4613         u8         reserved_at_60[0x20];
4614 };
4615 
4616 struct mlx5_ifc_query_qp_out_bits {
4617         u8         status[0x8];
4618         u8         reserved_at_8[0x18];
4619 
4620         u8         syndrome[0x20];
4621 
4622         u8         reserved_at_40[0x40];
4623 
4624         u8         opt_param_mask[0x20];
4625 
4626         u8         reserved_at_a0[0x20];
4627 
4628         struct mlx5_ifc_qpc_bits qpc;
4629 
4630         u8         reserved_at_800[0x80];
4631 
4632         u8         pas[0][0x40];
4633 };
4634 
4635 struct mlx5_ifc_query_qp_in_bits {
4636         u8         opcode[0x10];
4637         u8         reserved_at_10[0x10];
4638 
4639         u8         reserved_at_20[0x10];
4640         u8         op_mod[0x10];
4641 
4642         u8         reserved_at_40[0x8];
4643         u8         qpn[0x18];
4644 
4645         u8         reserved_at_60[0x20];
4646 };
4647 
4648 struct mlx5_ifc_query_q_counter_out_bits {
4649         u8         status[0x8];
4650         u8         reserved_at_8[0x18];
4651 
4652         u8         syndrome[0x20];
4653 
4654         u8         reserved_at_40[0x40];
4655 
4656         u8         rx_write_requests[0x20];
4657 
4658         u8         reserved_at_a0[0x20];
4659 
4660         u8         rx_read_requests[0x20];
4661 
4662         u8         reserved_at_e0[0x20];
4663 
4664         u8         rx_atomic_requests[0x20];
4665 
4666         u8         reserved_at_120[0x20];
4667 
4668         u8         rx_dct_connect[0x20];
4669 
4670         u8         reserved_at_160[0x20];
4671 
4672         u8         out_of_buffer[0x20];
4673 
4674         u8         reserved_at_1a0[0x20];
4675 
4676         u8         out_of_sequence[0x20];
4677 
4678         u8         reserved_at_1e0[0x20];
4679 
4680         u8         duplicate_request[0x20];
4681 
4682         u8         reserved_at_220[0x20];
4683 
4684         u8         rnr_nak_retry_err[0x20];
4685 
4686         u8         reserved_at_260[0x20];
4687 
4688         u8         packet_seq_err[0x20];
4689 
4690         u8         reserved_at_2a0[0x20];
4691 
4692         u8         implied_nak_seq_err[0x20];
4693 
4694         u8         reserved_at_2e0[0x20];
4695 
4696         u8         local_ack_timeout_err[0x20];
4697 
4698         u8         reserved_at_320[0xa0];
4699 
4700         u8         resp_local_length_error[0x20];
4701 
4702         u8         req_local_length_error[0x20];
4703 
4704         u8         resp_local_qp_error[0x20];
4705 
4706         u8         local_operation_error[0x20];
4707 
4708         u8         resp_local_protection[0x20];
4709 
4710         u8         req_local_protection[0x20];
4711 
4712         u8         resp_cqe_error[0x20];
4713 
4714         u8         req_cqe_error[0x20];
4715 
4716         u8         req_mw_binding[0x20];
4717 
4718         u8         req_bad_response[0x20];
4719 
4720         u8         req_remote_invalid_request[0x20];
4721 
4722         u8         resp_remote_invalid_request[0x20];
4723 
4724         u8         req_remote_access_errors[0x20];
4725 
4726         u8         resp_remote_access_errors[0x20];
4727 
4728         u8         req_remote_operation_errors[0x20];
4729 
4730         u8         req_transport_retries_exceeded[0x20];
4731 
4732         u8         cq_overflow[0x20];
4733 
4734         u8         resp_cqe_flush_error[0x20];
4735 
4736         u8         req_cqe_flush_error[0x20];
4737 
4738         u8         reserved_at_620[0x1e0];
4739 };
4740 
4741 struct mlx5_ifc_query_q_counter_in_bits {
4742         u8         opcode[0x10];
4743         u8         reserved_at_10[0x10];
4744 
4745         u8         reserved_at_20[0x10];
4746         u8         op_mod[0x10];
4747 
4748         u8         reserved_at_40[0x80];
4749 
4750         u8         clear[0x1];
4751         u8         reserved_at_c1[0x1f];
4752 
4753         u8         reserved_at_e0[0x18];
4754         u8         counter_set_id[0x8];
4755 };
4756 
4757 struct mlx5_ifc_query_pages_out_bits {
4758         u8         status[0x8];
4759         u8         reserved_at_8[0x18];
4760 
4761         u8         syndrome[0x20];
4762 
4763         u8         embedded_cpu_function[0x1];
4764         u8         reserved_at_41[0xf];
4765         u8         function_id[0x10];
4766 
4767         u8         num_pages[0x20];
4768 };
4769 
4770 enum {
4771         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4772         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4773         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4774 };
4775 
4776 struct mlx5_ifc_query_pages_in_bits {
4777         u8         opcode[0x10];
4778         u8         reserved_at_10[0x10];
4779 
4780         u8         reserved_at_20[0x10];
4781         u8         op_mod[0x10];
4782 
4783         u8         embedded_cpu_function[0x1];
4784         u8         reserved_at_41[0xf];
4785         u8         function_id[0x10];
4786 
4787         u8         reserved_at_60[0x20];
4788 };
4789 
4790 struct mlx5_ifc_query_nic_vport_context_out_bits {
4791         u8         status[0x8];
4792         u8         reserved_at_8[0x18];
4793 
4794         u8         syndrome[0x20];
4795 
4796         u8         reserved_at_40[0x40];
4797 
4798         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4799 };
4800 
4801 struct mlx5_ifc_query_nic_vport_context_in_bits {
4802         u8         opcode[0x10];
4803         u8         reserved_at_10[0x10];
4804 
4805         u8         reserved_at_20[0x10];
4806         u8         op_mod[0x10];
4807 
4808         u8         other_vport[0x1];
4809         u8         reserved_at_41[0xf];
4810         u8         vport_number[0x10];
4811 
4812         u8         reserved_at_60[0x5];
4813         u8         allowed_list_type[0x3];
4814         u8         reserved_at_68[0x18];
4815 };
4816 
4817 struct mlx5_ifc_query_mkey_out_bits {
4818         u8         status[0x8];
4819         u8         reserved_at_8[0x18];
4820 
4821         u8         syndrome[0x20];
4822 
4823         u8         reserved_at_40[0x40];
4824 
4825         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4826 
4827         u8         reserved_at_280[0x600];
4828 
4829         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4830 
4831         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4832 };
4833 
4834 struct mlx5_ifc_query_mkey_in_bits {
4835         u8         opcode[0x10];
4836         u8         reserved_at_10[0x10];
4837 
4838         u8         reserved_at_20[0x10];
4839         u8         op_mod[0x10];
4840 
4841         u8         reserved_at_40[0x8];
4842         u8         mkey_index[0x18];
4843 
4844         u8         pg_access[0x1];
4845         u8         reserved_at_61[0x1f];
4846 };
4847 
4848 struct mlx5_ifc_query_mad_demux_out_bits {
4849         u8         status[0x8];
4850         u8         reserved_at_8[0x18];
4851 
4852         u8         syndrome[0x20];
4853 
4854         u8         reserved_at_40[0x40];
4855 
4856         u8         mad_dumux_parameters_block[0x20];
4857 };
4858 
4859 struct mlx5_ifc_query_mad_demux_in_bits {
4860         u8         opcode[0x10];
4861         u8         reserved_at_10[0x10];
4862 
4863         u8         reserved_at_20[0x10];
4864         u8         op_mod[0x10];
4865 
4866         u8         reserved_at_40[0x40];
4867 };
4868 
4869 struct mlx5_ifc_query_l2_table_entry_out_bits {
4870         u8         status[0x8];
4871         u8         reserved_at_8[0x18];
4872 
4873         u8         syndrome[0x20];
4874 
4875         u8         reserved_at_40[0xa0];
4876 
4877         u8         reserved_at_e0[0x13];
4878         u8         vlan_valid[0x1];
4879         u8         vlan[0xc];
4880 
4881         struct mlx5_ifc_mac_address_layout_bits mac_address;
4882 
4883         u8         reserved_at_140[0xc0];
4884 };
4885 
4886 struct mlx5_ifc_query_l2_table_entry_in_bits {
4887         u8         opcode[0x10];
4888         u8         reserved_at_10[0x10];
4889 
4890         u8         reserved_at_20[0x10];
4891         u8         op_mod[0x10];
4892 
4893         u8         reserved_at_40[0x60];
4894 
4895         u8         reserved_at_a0[0x8];
4896         u8         table_index[0x18];
4897 
4898         u8         reserved_at_c0[0x140];
4899 };
4900 
4901 struct mlx5_ifc_query_issi_out_bits {
4902         u8         status[0x8];
4903         u8         reserved_at_8[0x18];
4904 
4905         u8         syndrome[0x20];
4906 
4907         u8         reserved_at_40[0x10];
4908         u8         current_issi[0x10];
4909 
4910         u8         reserved_at_60[0xa0];
4911 
4912         u8         reserved_at_100[76][0x8];
4913         u8         supported_issi_dw0[0x20];
4914 };
4915 
4916 struct mlx5_ifc_query_issi_in_bits {
4917         u8         opcode[0x10];
4918         u8         reserved_at_10[0x10];
4919 
4920         u8         reserved_at_20[0x10];
4921         u8         op_mod[0x10];
4922 
4923         u8         reserved_at_40[0x40];
4924 };
4925 
4926 struct mlx5_ifc_set_driver_version_out_bits {
4927         u8         status[0x8];
4928         u8         reserved_0[0x18];
4929 
4930         u8         syndrome[0x20];
4931         u8         reserved_1[0x40];
4932 };
4933 
4934 struct mlx5_ifc_set_driver_version_in_bits {
4935         u8         opcode[0x10];
4936         u8         reserved_0[0x10];
4937 
4938         u8         reserved_1[0x10];
4939         u8         op_mod[0x10];
4940 
4941         u8         reserved_2[0x40];
4942         u8         driver_version[64][0x8];
4943 };
4944 
4945 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4946         u8         status[0x8];
4947         u8         reserved_at_8[0x18];
4948 
4949         u8         syndrome[0x20];
4950 
4951         u8         reserved_at_40[0x40];
4952 
4953         struct mlx5_ifc_pkey_bits pkey[0];
4954 };
4955 
4956 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4957         u8         opcode[0x10];
4958         u8         reserved_at_10[0x10];
4959 
4960         u8         reserved_at_20[0x10];
4961         u8         op_mod[0x10];
4962 
4963         u8         other_vport[0x1];
4964         u8         reserved_at_41[0xb];
4965         u8         port_num[0x4];
4966         u8         vport_number[0x10];
4967 
4968         u8         reserved_at_60[0x10];
4969         u8         pkey_index[0x10];
4970 };
4971 
4972 enum {
4973         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4974         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4975         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4976 };
4977 
4978 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4979         u8         status[0x8];
4980         u8         reserved_at_8[0x18];
4981 
4982         u8         syndrome[0x20];
4983 
4984         u8         reserved_at_40[0x20];
4985 
4986         u8         gids_num[0x10];
4987         u8         reserved_at_70[0x10];
4988 
4989         struct mlx5_ifc_array128_auto_bits gid[0];
4990 };
4991 
4992 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4993         u8         opcode[0x10];
4994         u8         reserved_at_10[0x10];
4995 
4996         u8         reserved_at_20[0x10];
4997         u8         op_mod[0x10];
4998 
4999         u8         other_vport[0x1];
5000         u8         reserved_at_41[0xb];
5001         u8         port_num[0x4];
5002         u8         vport_number[0x10];
5003 
5004         u8         reserved_at_60[0x10];
5005         u8         gid_index[0x10];
5006 };
5007 
5008 struct mlx5_ifc_query_hca_vport_context_out_bits {
5009         u8         status[0x8];
5010         u8         reserved_at_8[0x18];
5011 
5012         u8         syndrome[0x20];
5013 
5014         u8         reserved_at_40[0x40];
5015 
5016         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5017 };
5018 
5019 struct mlx5_ifc_query_hca_vport_context_in_bits {
5020         u8         opcode[0x10];
5021         u8         reserved_at_10[0x10];
5022 
5023         u8         reserved_at_20[0x10];
5024         u8         op_mod[0x10];
5025 
5026         u8         other_vport[0x1];
5027         u8         reserved_at_41[0xb];
5028         u8         port_num[0x4];
5029         u8         vport_number[0x10];
5030 
5031         u8         reserved_at_60[0x20];
5032 };
5033 
5034 struct mlx5_ifc_query_hca_cap_out_bits {
5035         u8         status[0x8];
5036         u8         reserved_at_8[0x18];
5037 
5038         u8         syndrome[0x20];
5039 
5040         u8         reserved_at_40[0x40];
5041 
5042         union mlx5_ifc_hca_cap_union_bits capability;
5043 };
5044 
5045 struct mlx5_ifc_query_hca_cap_in_bits {
5046         u8         opcode[0x10];
5047         u8         reserved_at_10[0x10];
5048 
5049         u8         reserved_at_20[0x10];
5050         u8         op_mod[0x10];
5051 
5052         u8         other_function[0x1];
5053         u8         reserved_at_41[0xf];
5054         u8         function_id[0x10];
5055 
5056         u8         reserved_at_60[0x20];
5057 };
5058 
5059 struct mlx5_ifc_other_hca_cap_bits {
5060         u8         roce[0x1];
5061         u8         reserved_at_1[0x27f];
5062 };
5063 
5064 struct mlx5_ifc_query_other_hca_cap_out_bits {
5065         u8         status[0x8];
5066         u8         reserved_at_8[0x18];
5067 
5068         u8         syndrome[0x20];
5069 
5070         u8         reserved_at_40[0x40];
5071 
5072         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5073 };
5074 
5075 struct mlx5_ifc_query_other_hca_cap_in_bits {
5076         u8         opcode[0x10];
5077         u8         reserved_at_10[0x10];
5078 
5079         u8         reserved_at_20[0x10];
5080         u8         op_mod[0x10];
5081 
5082         u8         reserved_at_40[0x10];
5083         u8         function_id[0x10];
5084 
5085         u8         reserved_at_60[0x20];
5086 };
5087 
5088 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5089         u8         status[0x8];
5090         u8         reserved_at_8[0x18];
5091 
5092         u8         syndrome[0x20];
5093 
5094         u8         reserved_at_40[0x40];
5095 };
5096 
5097 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5098         u8         opcode[0x10];
5099         u8         reserved_at_10[0x10];
5100 
5101         u8         reserved_at_20[0x10];
5102         u8         op_mod[0x10];
5103 
5104         u8         reserved_at_40[0x10];
5105         u8         function_id[0x10];
5106         u8         field_select[0x20];
5107 
5108         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5109 };
5110 
5111 struct mlx5_ifc_flow_table_context_bits {
5112         u8         reformat_en[0x1];
5113         u8         decap_en[0x1];
5114         u8         sw_owner[0x1];
5115         u8         termination_table[0x1];
5116         u8         table_miss_action[0x4];
5117         u8         level[0x8];
5118         u8         reserved_at_10[0x8];
5119         u8         log_size[0x8];
5120 
5121         u8         reserved_at_20[0x8];
5122         u8         table_miss_id[0x18];
5123 
5124         u8         reserved_at_40[0x8];
5125         u8         lag_master_next_table_id[0x18];
5126 
5127         u8         reserved_at_60[0x60];
5128 
5129         u8         sw_owner_icm_root_1[0x40];
5130 
5131         u8         sw_owner_icm_root_0[0x40];
5132 
5133 };
5134 
5135 struct mlx5_ifc_query_flow_table_out_bits {
5136         u8         status[0x8];
5137         u8         reserved_at_8[0x18];
5138 
5139         u8         syndrome[0x20];
5140 
5141         u8         reserved_at_40[0x80];
5142 
5143         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5144 };
5145 
5146 struct mlx5_ifc_query_flow_table_in_bits {
5147         u8         opcode[0x10];
5148         u8         reserved_at_10[0x10];
5149 
5150         u8         reserved_at_20[0x10];
5151         u8         op_mod[0x10];
5152 
5153         u8         reserved_at_40[0x40];
5154 
5155         u8         table_type[0x8];
5156         u8         reserved_at_88[0x18];
5157 
5158         u8         reserved_at_a0[0x8];
5159         u8         table_id[0x18];
5160 
5161         u8         reserved_at_c0[0x140];
5162 };
5163 
5164 struct mlx5_ifc_query_fte_out_bits {
5165         u8         status[0x8];
5166         u8         reserved_at_8[0x18];
5167 
5168         u8         syndrome[0x20];
5169 
5170         u8         reserved_at_40[0x1c0];
5171 
5172         struct mlx5_ifc_flow_context_bits flow_context;
5173 };
5174 
5175 struct mlx5_ifc_query_fte_in_bits {
5176         u8         opcode[0x10];
5177         u8         reserved_at_10[0x10];
5178 
5179         u8         reserved_at_20[0x10];
5180         u8         op_mod[0x10];
5181 
5182         u8         reserved_at_40[0x40];
5183 
5184         u8         table_type[0x8];
5185         u8         reserved_at_88[0x18];
5186 
5187         u8         reserved_at_a0[0x8];
5188         u8         table_id[0x18];
5189 
5190         u8         reserved_at_c0[0x40];
5191 
5192         u8         flow_index[0x20];
5193 
5194         u8         reserved_at_120[0xe0];
5195 };
5196 
5197 enum {
5198         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5199         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5200         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5201         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5202         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5203 };
5204 
5205 struct mlx5_ifc_query_flow_group_out_bits {
5206         u8         status[0x8];
5207         u8         reserved_at_8[0x18];
5208 
5209         u8         syndrome[0x20];
5210 
5211         u8         reserved_at_40[0xa0];
5212 
5213         u8         start_flow_index[0x20];
5214 
5215         u8         reserved_at_100[0x20];
5216 
5217         u8         end_flow_index[0x20];
5218 
5219         u8         reserved_at_140[0xa0];
5220 
5221         u8         reserved_at_1e0[0x18];
5222         u8         match_criteria_enable[0x8];
5223 
5224         struct mlx5_ifc_fte_match_param_bits match_criteria;
5225 
5226         u8         reserved_at_1200[0xe00];
5227 };
5228 
5229 struct mlx5_ifc_query_flow_group_in_bits {
5230         u8         opcode[0x10];
5231         u8         reserved_at_10[0x10];
5232 
5233         u8         reserved_at_20[0x10];
5234         u8         op_mod[0x10];
5235 
5236         u8         reserved_at_40[0x40];
5237 
5238         u8         table_type[0x8];
5239         u8         reserved_at_88[0x18];
5240 
5241         u8         reserved_at_a0[0x8];
5242         u8         table_id[0x18];
5243 
5244         u8         group_id[0x20];
5245 
5246         u8         reserved_at_e0[0x120];
5247 };
5248 
5249 struct mlx5_ifc_query_flow_counter_out_bits {
5250         u8         status[0x8];
5251         u8         reserved_at_8[0x18];
5252 
5253         u8         syndrome[0x20];
5254 
5255         u8         reserved_at_40[0x40];
5256 
5257         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5258 };
5259 
5260 struct mlx5_ifc_query_flow_counter_in_bits {
5261         u8         opcode[0x10];
5262         u8         reserved_at_10[0x10];
5263 
5264         u8         reserved_at_20[0x10];
5265         u8         op_mod[0x10];
5266 
5267         u8         reserved_at_40[0x80];
5268 
5269         u8         clear[0x1];
5270         u8         reserved_at_c1[0xf];
5271         u8         num_of_counters[0x10];
5272 
5273         u8         flow_counter_id[0x20];
5274 };
5275 
5276 struct mlx5_ifc_query_esw_vport_context_out_bits {
5277         u8         status[0x8];
5278         u8         reserved_at_8[0x18];
5279 
5280         u8         syndrome[0x20];
5281 
5282         u8         reserved_at_40[0x40];
5283 
5284         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5285 };
5286 
5287 struct mlx5_ifc_query_esw_vport_context_in_bits {
5288         u8         opcode[0x10];
5289         u8         reserved_at_10[0x10];
5290 
5291         u8         reserved_at_20[0x10];
5292         u8         op_mod[0x10];
5293 
5294         u8         other_vport[0x1];
5295         u8         reserved_at_41[0xf];
5296         u8         vport_number[0x10];
5297 
5298         u8         reserved_at_60[0x20];
5299 };
5300 
5301 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5302         u8         status[0x8];
5303         u8         reserved_at_8[0x18];
5304 
5305         u8         syndrome[0x20];
5306 
5307         u8         reserved_at_40[0x40];
5308 };
5309 
5310 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5311         u8         reserved_at_0[0x1b];
5312         u8         fdb_to_vport_reg_c_id[0x1];
5313         u8         vport_cvlan_insert[0x1];
5314         u8         vport_svlan_insert[0x1];
5315         u8         vport_cvlan_strip[0x1];
5316         u8         vport_svlan_strip[0x1];
5317 };
5318 
5319 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5320         u8         opcode[0x10];
5321         u8         reserved_at_10[0x10];
5322 
5323         u8         reserved_at_20[0x10];
5324         u8         op_mod[0x10];
5325 
5326         u8         other_vport[0x1];
5327         u8         reserved_at_41[0xf];
5328         u8         vport_number[0x10];
5329 
5330         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5331 
5332         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5333 };
5334 
5335 struct mlx5_ifc_query_eq_out_bits {
5336         u8         status[0x8];
5337         u8         reserved_at_8[0x18];
5338 
5339         u8         syndrome[0x20];
5340 
5341         u8         reserved_at_40[0x40];
5342 
5343         struct mlx5_ifc_eqc_bits eq_context_entry;
5344 
5345         u8         reserved_at_280[0x40];
5346 
5347         u8         event_bitmask[0x40];
5348 
5349         u8         reserved_at_300[0x580];
5350 
5351         u8         pas[0][0x40];
5352 };
5353 
5354 struct mlx5_ifc_query_eq_in_bits {
5355         u8         opcode[0x10];
5356         u8         reserved_at_10[0x10];
5357 
5358         u8         reserved_at_20[0x10];
5359         u8         op_mod[0x10];
5360 
5361         u8         reserved_at_40[0x18];
5362         u8         eq_number[0x8];
5363 
5364         u8         reserved_at_60[0x20];
5365 };
5366 
5367 struct mlx5_ifc_packet_reformat_context_in_bits {
5368         u8         reserved_at_0[0x5];
5369         u8         reformat_type[0x3];
5370         u8         reserved_at_8[0xe];
5371         u8         reformat_data_size[0xa];
5372 
5373         u8         reserved_at_20[0x10];
5374         u8         reformat_data[2][0x8];
5375 
5376         u8         more_reformat_data[0][0x8];
5377 };
5378 
5379 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5380         u8         status[0x8];
5381         u8         reserved_at_8[0x18];
5382 
5383         u8         syndrome[0x20];
5384 
5385         u8         reserved_at_40[0xa0];
5386 
5387         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5388 };
5389 
5390 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5391         u8         opcode[0x10];
5392         u8         reserved_at_10[0x10];
5393 
5394         u8         reserved_at_20[0x10];
5395         u8         op_mod[0x10];
5396 
5397         u8         packet_reformat_id[0x20];
5398 
5399         u8         reserved_at_60[0xa0];
5400 };
5401 
5402 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5403         u8         status[0x8];
5404         u8         reserved_at_8[0x18];
5405 
5406         u8         syndrome[0x20];
5407 
5408         u8         packet_reformat_id[0x20];
5409 
5410         u8         reserved_at_60[0x20];
5411 };
5412 
5413 enum mlx5_reformat_ctx_type {
5414         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5415         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5416         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5417         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5418         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5419 };
5420 
5421 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5422         u8         opcode[0x10];
5423         u8         reserved_at_10[0x10];
5424 
5425         u8         reserved_at_20[0x10];
5426         u8         op_mod[0x10];
5427 
5428         u8         reserved_at_40[0xa0];
5429 
5430         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5431 };
5432 
5433 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5434         u8         status[0x8];
5435         u8         reserved_at_8[0x18];
5436 
5437         u8         syndrome[0x20];
5438 
5439         u8         reserved_at_40[0x40];
5440 };
5441 
5442 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5443         u8         opcode[0x10];
5444         u8         reserved_at_10[0x10];
5445 
5446         u8         reserved_20[0x10];
5447         u8         op_mod[0x10];
5448 
5449         u8         packet_reformat_id[0x20];
5450 
5451         u8         reserved_60[0x20];
5452 };
5453 
5454 struct mlx5_ifc_set_action_in_bits {
5455         u8         action_type[0x4];
5456         u8         field[0xc];
5457         u8         reserved_at_10[0x3];
5458         u8         offset[0x5];
5459         u8         reserved_at_18[0x3];
5460         u8         length[0x5];
5461 
5462         u8         data[0x20];
5463 };
5464 
5465 struct mlx5_ifc_add_action_in_bits {
5466         u8         action_type[0x4];
5467         u8         field[0xc];
5468         u8         reserved_at_10[0x10];
5469 
5470         u8         data[0x20];
5471 };
5472 
5473 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5474         struct mlx5_ifc_set_action_in_bits set_action_in;
5475         struct mlx5_ifc_add_action_in_bits add_action_in;
5476         u8         reserved_at_0[0x40];
5477 };
5478 
5479 enum {
5480         MLX5_ACTION_TYPE_SET   = 0x1,
5481         MLX5_ACTION_TYPE_ADD   = 0x2,
5482 };
5483 
5484 enum {
5485         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5486         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5487         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5488         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5489         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5490         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5491         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5492         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5493         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5494         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5495         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5496         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5497         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5498         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5499         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5500         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5501         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5502         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5503         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5504         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5505         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5506         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5507         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5508         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5509         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5510         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5511         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5512         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5513         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5514         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5515         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5516         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5517         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5518         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5519 };
5520 
5521 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5522         u8         status[0x8];
5523         u8         reserved_at_8[0x18];
5524 
5525         u8         syndrome[0x20];
5526 
5527         u8         modify_header_id[0x20];
5528 
5529         u8         reserved_at_60[0x20];
5530 };
5531 
5532 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5533         u8         opcode[0x10];
5534         u8         reserved_at_10[0x10];
5535 
5536         u8         reserved_at_20[0x10];
5537         u8         op_mod[0x10];
5538 
5539         u8         reserved_at_40[0x20];
5540 
5541         u8         table_type[0x8];
5542         u8         reserved_at_68[0x10];
5543         u8         num_of_actions[0x8];
5544 
5545         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5546 };
5547 
5548 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5549         u8         status[0x8];
5550         u8         reserved_at_8[0x18];
5551 
5552         u8         syndrome[0x20];
5553 
5554         u8         reserved_at_40[0x40];
5555 };
5556 
5557 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5558         u8         opcode[0x10];
5559         u8         reserved_at_10[0x10];
5560 
5561         u8         reserved_at_20[0x10];
5562         u8         op_mod[0x10];
5563 
5564         u8         modify_header_id[0x20];
5565 
5566         u8         reserved_at_60[0x20];
5567 };
5568 
5569 struct mlx5_ifc_query_dct_out_bits {
5570         u8         status[0x8];
5571         u8         reserved_at_8[0x18];
5572 
5573         u8         syndrome[0x20];
5574 
5575         u8         reserved_at_40[0x40];
5576 
5577         struct mlx5_ifc_dctc_bits dct_context_entry;
5578 
5579         u8         reserved_at_280[0x180];
5580 };
5581 
5582 struct mlx5_ifc_query_dct_in_bits {
5583         u8         opcode[0x10];
5584         u8         reserved_at_10[0x10];
5585 
5586         u8         reserved_at_20[0x10];
5587         u8         op_mod[0x10];
5588 
5589         u8         reserved_at_40[0x8];
5590         u8         dctn[0x18];
5591 
5592         u8         reserved_at_60[0x20];
5593 };
5594 
5595 struct mlx5_ifc_query_cq_out_bits {
5596         u8         status[0x8];
5597         u8         reserved_at_8[0x18];
5598 
5599         u8         syndrome[0x20];
5600 
5601         u8         reserved_at_40[0x40];
5602 
5603         struct mlx5_ifc_cqc_bits cq_context;
5604 
5605         u8         reserved_at_280[0x600];
5606 
5607         u8         pas[0][0x40];
5608 };
5609 
5610 struct mlx5_ifc_query_cq_in_bits {
5611         u8         opcode[0x10];
5612         u8         reserved_at_10[0x10];
5613 
5614         u8         reserved_at_20[0x10];
5615         u8         op_mod[0x10];
5616 
5617         u8         reserved_at_40[0x8];
5618         u8         cqn[0x18];
5619 
5620         u8         reserved_at_60[0x20];
5621 };
5622 
5623 struct mlx5_ifc_query_cong_status_out_bits {
5624         u8         status[0x8];
5625         u8         reserved_at_8[0x18];
5626 
5627         u8         syndrome[0x20];
5628 
5629         u8         reserved_at_40[0x20];
5630 
5631         u8         enable[0x1];
5632         u8         tag_enable[0x1];
5633         u8         reserved_at_62[0x1e];
5634 };
5635 
5636 struct mlx5_ifc_query_cong_status_in_bits {
5637         u8         opcode[0x10];
5638         u8         reserved_at_10[0x10];
5639 
5640         u8         reserved_at_20[0x10];
5641         u8         op_mod[0x10];
5642 
5643         u8         reserved_at_40[0x18];
5644         u8         priority[0x4];
5645         u8         cong_protocol[0x4];
5646 
5647         u8         reserved_at_60[0x20];
5648 };
5649 
5650 struct mlx5_ifc_query_cong_statistics_out_bits {
5651         u8         status[0x8];
5652         u8         reserved_at_8[0x18];
5653 
5654         u8         syndrome[0x20];
5655 
5656         u8         reserved_at_40[0x40];
5657 
5658         u8         rp_cur_flows[0x20];
5659 
5660         u8         sum_flows[0x20];
5661 
5662         u8         rp_cnp_ignored_high[0x20];
5663 
5664         u8         rp_cnp_ignored_low[0x20];
5665 
5666         u8         rp_cnp_handled_high[0x20];
5667 
5668         u8         rp_cnp_handled_low[0x20];
5669 
5670         u8         reserved_at_140[0x100];
5671 
5672         u8         time_stamp_high[0x20];
5673 
5674         u8         time_stamp_low[0x20];
5675 
5676         u8         accumulators_period[0x20];
5677 
5678         u8         np_ecn_marked_roce_packets_high[0x20];
5679 
5680         u8         np_ecn_marked_roce_packets_low[0x20];
5681 
5682         u8         np_cnp_sent_high[0x20];
5683 
5684         u8         np_cnp_sent_low[0x20];
5685 
5686         u8         reserved_at_320[0x560];
5687 };
5688 
5689 struct mlx5_ifc_query_cong_statistics_in_bits {
5690         u8         opcode[0x10];
5691         u8         reserved_at_10[0x10];
5692 
5693         u8         reserved_at_20[0x10];
5694         u8         op_mod[0x10];
5695 
5696         u8         clear[0x1];
5697         u8         reserved_at_41[0x1f];
5698 
5699         u8         reserved_at_60[0x20];
5700 };
5701 
5702 struct mlx5_ifc_query_cong_params_out_bits {
5703         u8         status[0x8];
5704         u8         reserved_at_8[0x18];
5705 
5706         u8         syndrome[0x20];
5707 
5708         u8         reserved_at_40[0x40];
5709 
5710         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5711 };
5712 
5713 struct mlx5_ifc_query_cong_params_in_bits {
5714         u8         opcode[0x10];
5715         u8         reserved_at_10[0x10];
5716 
5717         u8         reserved_at_20[0x10];
5718         u8         op_mod[0x10];
5719 
5720         u8         reserved_at_40[0x1c];
5721         u8         cong_protocol[0x4];
5722 
5723         u8         reserved_at_60[0x20];
5724 };
5725 
5726 struct mlx5_ifc_query_adapter_out_bits {
5727         u8         status[0x8];
5728         u8         reserved_at_8[0x18];
5729 
5730         u8         syndrome[0x20];
5731 
5732         u8         reserved_at_40[0x40];
5733 
5734         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5735 };
5736 
5737 struct mlx5_ifc_query_adapter_in_bits {
5738         u8         opcode[0x10];
5739         u8         reserved_at_10[0x10];
5740 
5741         u8         reserved_at_20[0x10];
5742         u8         op_mod[0x10];
5743 
5744         u8         reserved_at_40[0x40];
5745 };
5746 
5747 struct mlx5_ifc_qp_2rst_out_bits {
5748         u8         status[0x8];
5749         u8         reserved_at_8[0x18];
5750 
5751         u8         syndrome[0x20];
5752 
5753         u8         reserved_at_40[0x40];
5754 };
5755 
5756 struct mlx5_ifc_qp_2rst_in_bits {
5757         u8         opcode[0x10];
5758         u8         uid[0x10];
5759 
5760         u8         reserved_at_20[0x10];
5761         u8         op_mod[0x10];
5762 
5763         u8         reserved_at_40[0x8];
5764         u8         qpn[0x18];
5765 
5766         u8         reserved_at_60[0x20];
5767 };
5768 
5769 struct mlx5_ifc_qp_2err_out_bits {
5770         u8         status[0x8];
5771         u8         reserved_at_8[0x18];
5772 
5773         u8         syndrome[0x20];
5774 
5775         u8         reserved_at_40[0x40];
5776 };
5777 
5778 struct mlx5_ifc_qp_2err_in_bits {
5779         u8         opcode[0x10];
5780         u8         uid[0x10];
5781 
5782         u8         reserved_at_20[0x10];
5783         u8         op_mod[0x10];
5784 
5785         u8         reserved_at_40[0x8];
5786         u8         qpn[0x18];
5787 
5788         u8         reserved_at_60[0x20];
5789 };
5790 
5791 struct mlx5_ifc_page_fault_resume_out_bits {
5792         u8         status[0x8];
5793         u8         reserved_at_8[0x18];
5794 
5795         u8         syndrome[0x20];
5796 
5797         u8         reserved_at_40[0x40];
5798 };
5799 
5800 struct mlx5_ifc_page_fault_resume_in_bits {
5801         u8         opcode[0x10];
5802         u8         reserved_at_10[0x10];
5803 
5804         u8         reserved_at_20[0x10];
5805         u8         op_mod[0x10];
5806 
5807         u8         error[0x1];
5808         u8         reserved_at_41[0x4];
5809         u8         page_fault_type[0x3];
5810         u8         wq_number[0x18];
5811 
5812         u8         reserved_at_60[0x8];
5813         u8         token[0x18];
5814 };
5815 
5816 struct mlx5_ifc_nop_out_bits {
5817         u8         status[0x8];
5818         u8         reserved_at_8[0x18];
5819 
5820         u8         syndrome[0x20];
5821 
5822         u8         reserved_at_40[0x40];
5823 };
5824 
5825 struct mlx5_ifc_nop_in_bits {
5826         u8         opcode[0x10];
5827         u8         reserved_at_10[0x10];
5828 
5829         u8         reserved_at_20[0x10];
5830         u8         op_mod[0x10];
5831 
5832         u8         reserved_at_40[0x40];
5833 };
5834 
5835 struct mlx5_ifc_modify_vport_state_out_bits {
5836         u8         status[0x8];
5837         u8         reserved_at_8[0x18];
5838 
5839         u8         syndrome[0x20];
5840 
5841         u8         reserved_at_40[0x40];
5842 };
5843 
5844 struct mlx5_ifc_modify_vport_state_in_bits {
5845         u8         opcode[0x10];
5846         u8         reserved_at_10[0x10];
5847 
5848         u8         reserved_at_20[0x10];
5849         u8         op_mod[0x10];
5850 
5851         u8         other_vport[0x1];
5852         u8         reserved_at_41[0xf];
5853         u8         vport_number[0x10];
5854 
5855         u8         reserved_at_60[0x18];
5856         u8         admin_state[0x4];
5857         u8         reserved_at_7c[0x4];
5858 };
5859 
5860 struct mlx5_ifc_modify_tis_out_bits {
5861         u8         status[0x8];
5862         u8         reserved_at_8[0x18];
5863 
5864         u8         syndrome[0x20];
5865 
5866         u8         reserved_at_40[0x40];
5867 };
5868 
5869 struct mlx5_ifc_modify_tis_bitmask_bits {
5870         u8         reserved_at_0[0x20];
5871 
5872         u8         reserved_at_20[0x1d];
5873         u8         lag_tx_port_affinity[0x1];
5874         u8         strict_lag_tx_port_affinity[0x1];
5875         u8         prio[0x1];
5876 };
5877 
5878 struct mlx5_ifc_modify_tis_in_bits {
5879         u8         opcode[0x10];
5880         u8         uid[0x10];
5881 
5882         u8         reserved_at_20[0x10];
5883         u8         op_mod[0x10];
5884 
5885         u8         reserved_at_40[0x8];
5886         u8         tisn[0x18];
5887 
5888         u8         reserved_at_60[0x20];
5889 
5890         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5891 
5892         u8         reserved_at_c0[0x40];
5893 
5894         struct mlx5_ifc_tisc_bits ctx;
5895 };
5896 
5897 struct mlx5_ifc_modify_tir_bitmask_bits {
5898         u8         reserved_at_0[0x20];
5899 
5900         u8         reserved_at_20[0x1b];
5901         u8         self_lb_en[0x1];
5902         u8         reserved_at_3c[0x1];
5903         u8         hash[0x1];
5904         u8         reserved_at_3e[0x1];
5905         u8         lro[0x1];
5906 };
5907 
5908 struct mlx5_ifc_modify_tir_out_bits {
5909         u8         status[0x8];
5910         u8         reserved_at_8[0x18];
5911 
5912         u8         syndrome[0x20];
5913 
5914         u8         reserved_at_40[0x40];
5915 };
5916 
5917 struct mlx5_ifc_modify_tir_in_bits {
5918         u8         opcode[0x10];
5919         u8         uid[0x10];
5920 
5921         u8         reserved_at_20[0x10];
5922         u8         op_mod[0x10];
5923 
5924         u8         reserved_at_40[0x8];
5925         u8         tirn[0x18];
5926 
5927         u8         reserved_at_60[0x20];
5928 
5929         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5930 
5931         u8         reserved_at_c0[0x40];
5932 
5933         struct mlx5_ifc_tirc_bits ctx;
5934 };
5935 
5936 struct mlx5_ifc_modify_sq_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_at_8[0x18];
5939 
5940         u8         syndrome[0x20];
5941 
5942         u8         reserved_at_40[0x40];
5943 };
5944 
5945 struct mlx5_ifc_modify_sq_in_bits {
5946         u8         opcode[0x10];
5947         u8         uid[0x10];
5948 
5949         u8         reserved_at_20[0x10];
5950         u8         op_mod[0x10];
5951 
5952         u8         sq_state[0x4];
5953         u8         reserved_at_44[0x4];
5954         u8         sqn[0x18];
5955 
5956         u8         reserved_at_60[0x20];
5957 
5958         u8         modify_bitmask[0x40];
5959 
5960         u8         reserved_at_c0[0x40];
5961 
5962         struct mlx5_ifc_sqc_bits ctx;
5963 };
5964 
5965 struct mlx5_ifc_modify_scheduling_element_out_bits {
5966         u8         status[0x8];
5967         u8         reserved_at_8[0x18];
5968 
5969         u8         syndrome[0x20];
5970 
5971         u8         reserved_at_40[0x1c0];
5972 };
5973 
5974 enum {
5975         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5976         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5977 };
5978 
5979 struct mlx5_ifc_modify_scheduling_element_in_bits {
5980         u8         opcode[0x10];
5981         u8         reserved_at_10[0x10];
5982 
5983         u8         reserved_at_20[0x10];
5984         u8         op_mod[0x10];
5985 
5986         u8         scheduling_hierarchy[0x8];
5987         u8         reserved_at_48[0x18];
5988 
5989         u8         scheduling_element_id[0x20];
5990 
5991         u8         reserved_at_80[0x20];
5992 
5993         u8         modify_bitmask[0x20];
5994 
5995         u8         reserved_at_c0[0x40];
5996 
5997         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5998 
5999         u8         reserved_at_300[0x100];
6000 };
6001 
6002 struct mlx5_ifc_modify_rqt_out_bits {
6003         u8         status[0x8];
6004         u8         reserved_at_8[0x18];
6005 
6006         u8         syndrome[0x20];
6007 
6008         u8         reserved_at_40[0x40];
6009 };
6010 
6011 struct mlx5_ifc_rqt_bitmask_bits {
6012         u8         reserved_at_0[0x20];
6013 
6014         u8         reserved_at_20[0x1f];
6015         u8         rqn_list[0x1];
6016 };
6017 
6018 struct mlx5_ifc_modify_rqt_in_bits {
6019         u8         opcode[0x10];
6020         u8         uid[0x10];
6021 
6022         u8         reserved_at_20[0x10];
6023         u8         op_mod[0x10];
6024 
6025         u8         reserved_at_40[0x8];
6026         u8         rqtn[0x18];
6027 
6028         u8         reserved_at_60[0x20];
6029 
6030         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6031 
6032         u8         reserved_at_c0[0x40];
6033 
6034         struct mlx5_ifc_rqtc_bits ctx;
6035 };
6036 
6037 struct mlx5_ifc_modify_rq_out_bits {
6038         u8         status[0x8];
6039         u8         reserved_at_8[0x18];
6040 
6041         u8         syndrome[0x20];
6042 
6043         u8         reserved_at_40[0x40];
6044 };
6045 
6046 enum {
6047         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6048         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6049         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6050 };
6051 
6052 struct mlx5_ifc_modify_rq_in_bits {
6053         u8         opcode[0x10];
6054         u8         uid[0x10];
6055 
6056         u8         reserved_at_20[0x10];
6057         u8         op_mod[0x10];
6058 
6059         u8         rq_state[0x4];
6060         u8         reserved_at_44[0x4];
6061         u8         rqn[0x18];
6062 
6063         u8         reserved_at_60[0x20];
6064 
6065         u8         modify_bitmask[0x40];
6066 
6067         u8         reserved_at_c0[0x40];
6068 
6069         struct mlx5_ifc_rqc_bits ctx;
6070 };
6071 
6072 struct mlx5_ifc_modify_rmp_out_bits {
6073         u8         status[0x8];
6074         u8         reserved_at_8[0x18];
6075 
6076         u8         syndrome[0x20];
6077 
6078         u8         reserved_at_40[0x40];
6079 };
6080 
6081 struct mlx5_ifc_rmp_bitmask_bits {
6082         u8         reserved_at_0[0x20];
6083 
6084         u8         reserved_at_20[0x1f];
6085         u8         lwm[0x1];
6086 };
6087 
6088 struct mlx5_ifc_modify_rmp_in_bits {
6089         u8         opcode[0x10];
6090         u8         uid[0x10];
6091 
6092         u8         reserved_at_20[0x10];
6093         u8         op_mod[0x10];
6094 
6095         u8         rmp_state[0x4];
6096         u8         reserved_at_44[0x4];
6097         u8         rmpn[0x18];
6098 
6099         u8         reserved_at_60[0x20];
6100 
6101         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6102 
6103         u8         reserved_at_c0[0x40];
6104 
6105         struct mlx5_ifc_rmpc_bits ctx;
6106 };
6107 
6108 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6109         u8         status[0x8];
6110         u8         reserved_at_8[0x18];
6111 
6112         u8         syndrome[0x20];
6113 
6114         u8         reserved_at_40[0x40];
6115 };
6116 
6117 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6118         u8         reserved_at_0[0x12];
6119         u8         affiliation[0x1];
6120         u8         reserved_at_13[0x1];
6121         u8         disable_uc_local_lb[0x1];
6122         u8         disable_mc_local_lb[0x1];
6123         u8         node_guid[0x1];
6124         u8         port_guid[0x1];
6125         u8         min_inline[0x1];
6126         u8         mtu[0x1];
6127         u8         change_event[0x1];
6128         u8         promisc[0x1];
6129         u8         permanent_address[0x1];
6130         u8         addresses_list[0x1];
6131         u8         roce_en[0x1];
6132         u8         reserved_at_1f[0x1];
6133 };
6134 
6135 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6136         u8         opcode[0x10];
6137         u8         reserved_at_10[0x10];
6138 
6139         u8         reserved_at_20[0x10];
6140         u8         op_mod[0x10];
6141 
6142         u8         other_vport[0x1];
6143         u8         reserved_at_41[0xf];
6144         u8         vport_number[0x10];
6145 
6146         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6147 
6148         u8         reserved_at_80[0x780];
6149 
6150         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6151 };
6152 
6153 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6154         u8         status[0x8];
6155         u8         reserved_at_8[0x18];
6156 
6157         u8         syndrome[0x20];
6158 
6159         u8         reserved_at_40[0x40];
6160 };
6161 
6162 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6163         u8         opcode[0x10];
6164         u8         reserved_at_10[0x10];
6165 
6166         u8         reserved_at_20[0x10];
6167         u8         op_mod[0x10];
6168 
6169         u8         other_vport[0x1];
6170         u8         reserved_at_41[0xb];
6171         u8         port_num[0x4];
6172         u8         vport_number[0x10];
6173 
6174         u8         reserved_at_60[0x20];
6175 
6176         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6177 };
6178 
6179 struct mlx5_ifc_modify_cq_out_bits {
6180         u8         status[0x8];
6181         u8         reserved_at_8[0x18];
6182 
6183         u8         syndrome[0x20];
6184 
6185         u8         reserved_at_40[0x40];
6186 };
6187 
6188 enum {
6189         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6190         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6191 };
6192 
6193 struct mlx5_ifc_modify_cq_in_bits {
6194         u8         opcode[0x10];
6195         u8         uid[0x10];
6196 
6197         u8         reserved_at_20[0x10];
6198         u8         op_mod[0x10];
6199 
6200         u8         reserved_at_40[0x8];
6201         u8         cqn[0x18];
6202 
6203         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6204 
6205         struct mlx5_ifc_cqc_bits cq_context;
6206 
6207         u8         reserved_at_280[0x60];
6208 
6209         u8         cq_umem_valid[0x1];
6210         u8         reserved_at_2e1[0x1f];
6211 
6212         u8         reserved_at_300[0x580];
6213 
6214         u8         pas[0][0x40];
6215 };
6216 
6217 struct mlx5_ifc_modify_cong_status_out_bits {
6218         u8         status[0x8];
6219         u8         reserved_at_8[0x18];
6220 
6221         u8         syndrome[0x20];
6222 
6223         u8         reserved_at_40[0x40];
6224 };
6225 
6226 struct mlx5_ifc_modify_cong_status_in_bits {
6227         u8         opcode[0x10];
6228         u8         reserved_at_10[0x10];
6229 
6230         u8         reserved_at_20[0x10];
6231         u8         op_mod[0x10];
6232 
6233         u8         reserved_at_40[0x18];
6234         u8         priority[0x4];
6235         u8         cong_protocol[0x4];
6236 
6237         u8         enable[0x1];
6238         u8         tag_enable[0x1];
6239         u8         reserved_at_62[0x1e];
6240 };
6241 
6242 struct mlx5_ifc_modify_cong_params_out_bits {
6243         u8         status[0x8];
6244         u8         reserved_at_8[0x18];
6245 
6246         u8         syndrome[0x20];
6247 
6248         u8         reserved_at_40[0x40];
6249 };
6250 
6251 struct mlx5_ifc_modify_cong_params_in_bits {
6252         u8         opcode[0x10];
6253         u8         reserved_at_10[0x10];
6254 
6255         u8         reserved_at_20[0x10];
6256         u8         op_mod[0x10];
6257 
6258         u8         reserved_at_40[0x1c];
6259         u8         cong_protocol[0x4];
6260 
6261         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6262 
6263         u8         reserved_at_80[0x80];
6264 
6265         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6266 };
6267 
6268 struct mlx5_ifc_manage_pages_out_bits {
6269         u8         status[0x8];
6270         u8         reserved_at_8[0x18];
6271 
6272         u8         syndrome[0x20];
6273 
6274         u8         output_num_entries[0x20];
6275 
6276         u8         reserved_at_60[0x20];
6277 
6278         u8         pas[0][0x40];
6279 };
6280 
6281 enum {
6282         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6283         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6284         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6285 };
6286 
6287 struct mlx5_ifc_manage_pages_in_bits {
6288         u8         opcode[0x10];
6289         u8         reserved_at_10[0x10];
6290 
6291         u8         reserved_at_20[0x10];
6292         u8         op_mod[0x10];
6293 
6294         u8         embedded_cpu_function[0x1];
6295         u8         reserved_at_41[0xf];
6296         u8         function_id[0x10];
6297 
6298         u8         input_num_entries[0x20];
6299 
6300         u8         pas[0][0x40];
6301 };
6302 
6303 struct mlx5_ifc_mad_ifc_out_bits {
6304         u8         status[0x8];
6305         u8         reserved_at_8[0x18];
6306 
6307         u8         syndrome[0x20];
6308 
6309         u8         reserved_at_40[0x40];
6310 
6311         u8         response_mad_packet[256][0x8];
6312 };
6313 
6314 struct mlx5_ifc_mad_ifc_in_bits {
6315         u8         opcode[0x10];
6316         u8         reserved_at_10[0x10];
6317 
6318         u8         reserved_at_20[0x10];
6319         u8         op_mod[0x10];
6320 
6321         u8         remote_lid[0x10];
6322         u8         reserved_at_50[0x8];
6323         u8         port[0x8];
6324 
6325         u8         reserved_at_60[0x20];
6326 
6327         u8         mad[256][0x8];
6328 };
6329 
6330 struct mlx5_ifc_init_hca_out_bits {
6331         u8         status[0x8];
6332         u8         reserved_at_8[0x18];
6333 
6334         u8         syndrome[0x20];
6335 
6336         u8         reserved_at_40[0x40];
6337 };
6338 
6339 struct mlx5_ifc_init_hca_in_bits {
6340         u8         opcode[0x10];
6341         u8         reserved_at_10[0x10];
6342 
6343         u8         reserved_at_20[0x10];
6344         u8         op_mod[0x10];
6345 
6346         u8         reserved_at_40[0x40];
6347         u8         sw_owner_id[4][0x20];
6348 };
6349 
6350 struct mlx5_ifc_init2rtr_qp_out_bits {
6351         u8         status[0x8];
6352         u8         reserved_at_8[0x18];
6353 
6354         u8         syndrome[0x20];
6355 
6356         u8         reserved_at_40[0x40];
6357 };
6358 
6359 struct mlx5_ifc_init2rtr_qp_in_bits {
6360         u8         opcode[0x10];
6361         u8         uid[0x10];
6362 
6363         u8         reserved_at_20[0x10];
6364         u8         op_mod[0x10];
6365 
6366         u8         reserved_at_40[0x8];
6367         u8         qpn[0x18];
6368 
6369         u8         reserved_at_60[0x20];
6370 
6371         u8         opt_param_mask[0x20];
6372 
6373         u8         reserved_at_a0[0x20];
6374 
6375         struct mlx5_ifc_qpc_bits qpc;
6376 
6377         u8         reserved_at_800[0x80];
6378 };
6379 
6380 struct mlx5_ifc_init2init_qp_out_bits {
6381         u8         status[0x8];
6382         u8         reserved_at_8[0x18];
6383 
6384         u8         syndrome[0x20];
6385 
6386         u8         reserved_at_40[0x40];
6387 };
6388 
6389 struct mlx5_ifc_init2init_qp_in_bits {
6390         u8         opcode[0x10];
6391         u8         uid[0x10];
6392 
6393         u8         reserved_at_20[0x10];
6394         u8         op_mod[0x10];
6395 
6396         u8         reserved_at_40[0x8];
6397         u8         qpn[0x18];
6398 
6399         u8         reserved_at_60[0x20];
6400 
6401         u8         opt_param_mask[0x20];
6402 
6403         u8         reserved_at_a0[0x20];
6404 
6405         struct mlx5_ifc_qpc_bits qpc;
6406 
6407         u8         reserved_at_800[0x80];
6408 };
6409 
6410 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6411         u8         status[0x8];
6412         u8         reserved_at_8[0x18];
6413 
6414         u8         syndrome[0x20];
6415 
6416         u8         reserved_at_40[0x40];
6417 
6418         u8         packet_headers_log[128][0x8];
6419 
6420         u8         packet_syndrome[64][0x8];
6421 };
6422 
6423 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6424         u8         opcode[0x10];
6425         u8         reserved_at_10[0x10];
6426 
6427         u8         reserved_at_20[0x10];
6428         u8         op_mod[0x10];
6429 
6430         u8         reserved_at_40[0x40];
6431 };
6432 
6433 struct mlx5_ifc_gen_eqe_in_bits {
6434         u8         opcode[0x10];
6435         u8         reserved_at_10[0x10];
6436 
6437         u8         reserved_at_20[0x10];
6438         u8         op_mod[0x10];
6439 
6440         u8         reserved_at_40[0x18];
6441         u8         eq_number[0x8];
6442 
6443         u8         reserved_at_60[0x20];
6444 
6445         u8         eqe[64][0x8];
6446 };
6447 
6448 struct mlx5_ifc_gen_eq_out_bits {
6449         u8         status[0x8];
6450         u8         reserved_at_8[0x18];
6451 
6452         u8         syndrome[0x20];
6453 
6454         u8         reserved_at_40[0x40];
6455 };
6456 
6457 struct mlx5_ifc_enable_hca_out_bits {
6458         u8         status[0x8];
6459         u8         reserved_at_8[0x18];
6460 
6461         u8         syndrome[0x20];
6462 
6463         u8         reserved_at_40[0x20];
6464 };
6465 
6466 struct mlx5_ifc_enable_hca_in_bits {
6467         u8         opcode[0x10];
6468         u8         reserved_at_10[0x10];
6469 
6470         u8         reserved_at_20[0x10];
6471         u8         op_mod[0x10];
6472 
6473         u8         embedded_cpu_function[0x1];
6474         u8         reserved_at_41[0xf];
6475         u8         function_id[0x10];
6476 
6477         u8         reserved_at_60[0x20];
6478 };
6479 
6480 struct mlx5_ifc_drain_dct_out_bits {
6481         u8         status[0x8];
6482         u8         reserved_at_8[0x18];
6483 
6484         u8         syndrome[0x20];
6485 
6486         u8         reserved_at_40[0x40];
6487 };
6488 
6489 struct mlx5_ifc_drain_dct_in_bits {
6490         u8         opcode[0x10];
6491         u8         uid[0x10];
6492 
6493         u8         reserved_at_20[0x10];
6494         u8         op_mod[0x10];
6495 
6496         u8         reserved_at_40[0x8];
6497         u8         dctn[0x18];
6498 
6499         u8         reserved_at_60[0x20];
6500 };
6501 
6502 struct mlx5_ifc_disable_hca_out_bits {
6503         u8         status[0x8];
6504         u8         reserved_at_8[0x18];
6505 
6506         u8         syndrome[0x20];
6507 
6508         u8         reserved_at_40[0x20];
6509 };
6510 
6511 struct mlx5_ifc_disable_hca_in_bits {
6512         u8         opcode[0x10];
6513         u8         reserved_at_10[0x10];
6514 
6515         u8         reserved_at_20[0x10];
6516         u8         op_mod[0x10];
6517 
6518         u8         embedded_cpu_function[0x1];
6519         u8         reserved_at_41[0xf];
6520         u8         function_id[0x10];
6521 
6522         u8         reserved_at_60[0x20];
6523 };
6524 
6525 struct mlx5_ifc_detach_from_mcg_out_bits {
6526         u8         status[0x8];
6527         u8         reserved_at_8[0x18];
6528 
6529         u8         syndrome[0x20];
6530 
6531         u8         reserved_at_40[0x40];
6532 };
6533 
6534 struct mlx5_ifc_detach_from_mcg_in_bits {
6535         u8         opcode[0x10];
6536         u8         uid[0x10];
6537 
6538         u8         reserved_at_20[0x10];
6539         u8         op_mod[0x10];
6540 
6541         u8         reserved_at_40[0x8];
6542         u8         qpn[0x18];
6543 
6544         u8         reserved_at_60[0x20];
6545 
6546         u8         multicast_gid[16][0x8];
6547 };
6548 
6549 struct mlx5_ifc_destroy_xrq_out_bits {
6550         u8         status[0x8];
6551         u8         reserved_at_8[0x18];
6552 
6553         u8         syndrome[0x20];
6554 
6555         u8         reserved_at_40[0x40];
6556 };
6557 
6558 struct mlx5_ifc_destroy_xrq_in_bits {
6559         u8         opcode[0x10];
6560         u8         uid[0x10];
6561 
6562         u8         reserved_at_20[0x10];
6563         u8         op_mod[0x10];
6564 
6565         u8         reserved_at_40[0x8];
6566         u8         xrqn[0x18];
6567 
6568         u8         reserved_at_60[0x20];
6569 };
6570 
6571 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6572         u8         status[0x8];
6573         u8         reserved_at_8[0x18];
6574 
6575         u8         syndrome[0x20];
6576 
6577         u8         reserved_at_40[0x40];
6578 };
6579 
6580 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6581         u8         opcode[0x10];
6582         u8         uid[0x10];
6583 
6584         u8         reserved_at_20[0x10];
6585         u8         op_mod[0x10];
6586 
6587         u8         reserved_at_40[0x8];
6588         u8         xrc_srqn[0x18];
6589 
6590         u8         reserved_at_60[0x20];
6591 };
6592 
6593 struct mlx5_ifc_destroy_tis_out_bits {
6594         u8         status[0x8];
6595         u8         reserved_at_8[0x18];
6596 
6597         u8         syndrome[0x20];
6598 
6599         u8         reserved_at_40[0x40];
6600 };
6601 
6602 struct mlx5_ifc_destroy_tis_in_bits {
6603         u8         opcode[0x10];
6604         u8         uid[0x10];
6605 
6606         u8         reserved_at_20[0x10];
6607         u8         op_mod[0x10];
6608 
6609         u8         reserved_at_40[0x8];
6610         u8         tisn[0x18];
6611 
6612         u8         reserved_at_60[0x20];
6613 };
6614 
6615 struct mlx5_ifc_destroy_tir_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618 
6619         u8         syndrome[0x20];
6620 
6621         u8         reserved_at_40[0x40];
6622 };
6623 
6624 struct mlx5_ifc_destroy_tir_in_bits {
6625         u8         opcode[0x10];
6626         u8         uid[0x10];
6627 
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630 
6631         u8         reserved_at_40[0x8];
6632         u8         tirn[0x18];
6633 
6634         u8         reserved_at_60[0x20];
6635 };
6636 
6637 struct mlx5_ifc_destroy_srq_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_at_8[0x18];
6640 
6641         u8         syndrome[0x20];
6642 
6643         u8         reserved_at_40[0x40];
6644 };
6645 
6646 struct mlx5_ifc_destroy_srq_in_bits {
6647         u8         opcode[0x10];
6648         u8         uid[0x10];
6649 
6650         u8         reserved_at_20[0x10];
6651         u8         op_mod[0x10];
6652 
6653         u8         reserved_at_40[0x8];
6654         u8         srqn[0x18];
6655 
6656         u8         reserved_at_60[0x20];
6657 };
6658 
6659 struct mlx5_ifc_destroy_sq_out_bits {
6660         u8         status[0x8];
6661         u8         reserved_at_8[0x18];
6662 
6663         u8         syndrome[0x20];
6664 
6665         u8         reserved_at_40[0x40];
6666 };
6667 
6668 struct mlx5_ifc_destroy_sq_in_bits {
6669         u8         opcode[0x10];
6670         u8         uid[0x10];
6671 
6672         u8         reserved_at_20[0x10];
6673         u8         op_mod[0x10];
6674 
6675         u8         reserved_at_40[0x8];
6676         u8         sqn[0x18];
6677 
6678         u8         reserved_at_60[0x20];
6679 };
6680 
6681 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6682         u8         status[0x8];
6683         u8         reserved_at_8[0x18];
6684 
6685         u8         syndrome[0x20];
6686 
6687         u8         reserved_at_40[0x1c0];
6688 };
6689 
6690 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6691         u8         opcode[0x10];
6692         u8         reserved_at_10[0x10];
6693 
6694         u8         reserved_at_20[0x10];
6695         u8         op_mod[0x10];
6696 
6697         u8         scheduling_hierarchy[0x8];
6698         u8         reserved_at_48[0x18];
6699 
6700         u8         scheduling_element_id[0x20];
6701 
6702         u8         reserved_at_80[0x180];
6703 };
6704 
6705 struct mlx5_ifc_destroy_rqt_out_bits {
6706         u8         status[0x8];
6707         u8         reserved_at_8[0x18];
6708 
6709         u8         syndrome[0x20];
6710 
6711         u8         reserved_at_40[0x40];
6712 };
6713 
6714 struct mlx5_ifc_destroy_rqt_in_bits {
6715         u8         opcode[0x10];
6716         u8         uid[0x10];
6717 
6718         u8         reserved_at_20[0x10];
6719         u8         op_mod[0x10];
6720 
6721         u8         reserved_at_40[0x8];
6722         u8         rqtn[0x18];
6723 
6724         u8         reserved_at_60[0x20];
6725 };
6726 
6727 struct mlx5_ifc_destroy_rq_out_bits {
6728         u8         status[0x8];
6729         u8         reserved_at_8[0x18];
6730 
6731         u8         syndrome[0x20];
6732 
6733         u8         reserved_at_40[0x40];
6734 };
6735 
6736 struct mlx5_ifc_destroy_rq_in_bits {
6737         u8         opcode[0x10];
6738         u8         uid[0x10];
6739 
6740         u8         reserved_at_20[0x10];
6741         u8         op_mod[0x10];
6742 
6743         u8         reserved_at_40[0x8];
6744         u8         rqn[0x18];
6745 
6746         u8         reserved_at_60[0x20];
6747 };
6748 
6749 struct mlx5_ifc_set_delay_drop_params_in_bits {
6750         u8         opcode[0x10];
6751         u8         reserved_at_10[0x10];
6752 
6753         u8         reserved_at_20[0x10];
6754         u8         op_mod[0x10];
6755 
6756         u8         reserved_at_40[0x20];
6757 
6758         u8         reserved_at_60[0x10];
6759         u8         delay_drop_timeout[0x10];
6760 };
6761 
6762 struct mlx5_ifc_set_delay_drop_params_out_bits {
6763         u8         status[0x8];
6764         u8         reserved_at_8[0x18];
6765 
6766         u8         syndrome[0x20];
6767 
6768         u8         reserved_at_40[0x40];
6769 };
6770 
6771 struct mlx5_ifc_destroy_rmp_out_bits {
6772         u8         status[0x8];
6773         u8         reserved_at_8[0x18];
6774 
6775         u8         syndrome[0x20];
6776 
6777         u8         reserved_at_40[0x40];
6778 };
6779 
6780 struct mlx5_ifc_destroy_rmp_in_bits {
6781         u8         opcode[0x10];
6782         u8         uid[0x10];
6783 
6784         u8         reserved_at_20[0x10];
6785         u8         op_mod[0x10];
6786 
6787         u8         reserved_at_40[0x8];
6788         u8         rmpn[0x18];
6789 
6790         u8         reserved_at_60[0x20];
6791 };
6792 
6793 struct mlx5_ifc_destroy_qp_out_bits {
6794         u8         status[0x8];
6795         u8         reserved_at_8[0x18];
6796 
6797         u8         syndrome[0x20];
6798 
6799         u8         reserved_at_40[0x40];
6800 };
6801 
6802 struct mlx5_ifc_destroy_qp_in_bits {
6803         u8         opcode[0x10];
6804         u8         uid[0x10];
6805 
6806         u8         reserved_at_20[0x10];
6807         u8         op_mod[0x10];
6808 
6809         u8         reserved_at_40[0x8];
6810         u8         qpn[0x18];
6811 
6812         u8         reserved_at_60[0x20];
6813 };
6814 
6815 struct mlx5_ifc_destroy_psv_out_bits {
6816         u8         status[0x8];
6817         u8         reserved_at_8[0x18];
6818 
6819         u8         syndrome[0x20];
6820 
6821         u8         reserved_at_40[0x40];
6822 };
6823 
6824 struct mlx5_ifc_destroy_psv_in_bits {
6825         u8         opcode[0x10];
6826         u8         reserved_at_10[0x10];
6827 
6828         u8         reserved_at_20[0x10];
6829         u8         op_mod[0x10];
6830 
6831         u8         reserved_at_40[0x8];
6832         u8         psvn[0x18];
6833 
6834         u8         reserved_at_60[0x20];
6835 };
6836 
6837 struct mlx5_ifc_destroy_mkey_out_bits {
6838         u8         status[0x8];
6839         u8         reserved_at_8[0x18];
6840 
6841         u8         syndrome[0x20];
6842 
6843         u8         reserved_at_40[0x40];
6844 };
6845 
6846 struct mlx5_ifc_destroy_mkey_in_bits {
6847         u8         opcode[0x10];
6848         u8         reserved_at_10[0x10];
6849 
6850         u8         reserved_at_20[0x10];
6851         u8         op_mod[0x10];
6852 
6853         u8         reserved_at_40[0x8];
6854         u8         mkey_index[0x18];
6855 
6856         u8         reserved_at_60[0x20];
6857 };
6858 
6859 struct mlx5_ifc_destroy_flow_table_out_bits {
6860         u8         status[0x8];
6861         u8         reserved_at_8[0x18];
6862 
6863         u8         syndrome[0x20];
6864 
6865         u8         reserved_at_40[0x40];
6866 };
6867 
6868 struct mlx5_ifc_destroy_flow_table_in_bits {
6869         u8         opcode[0x10];
6870         u8         reserved_at_10[0x10];
6871 
6872         u8         reserved_at_20[0x10];
6873         u8         op_mod[0x10];
6874 
6875         u8         other_vport[0x1];
6876         u8         reserved_at_41[0xf];
6877         u8         vport_number[0x10];
6878 
6879         u8         reserved_at_60[0x20];
6880 
6881         u8         table_type[0x8];
6882         u8         reserved_at_88[0x18];
6883 
6884         u8         reserved_at_a0[0x8];
6885         u8         table_id[0x18];
6886 
6887         u8         reserved_at_c0[0x140];
6888 };
6889 
6890 struct mlx5_ifc_destroy_flow_group_out_bits {
6891         u8         status[0x8];
6892         u8         reserved_at_8[0x18];
6893 
6894         u8         syndrome[0x20];
6895 
6896         u8         reserved_at_40[0x40];
6897 };
6898 
6899 struct mlx5_ifc_destroy_flow_group_in_bits {
6900         u8         opcode[0x10];
6901         u8         reserved_at_10[0x10];
6902 
6903         u8         reserved_at_20[0x10];
6904         u8         op_mod[0x10];
6905 
6906         u8         other_vport[0x1];
6907         u8         reserved_at_41[0xf];
6908         u8         vport_number[0x10];
6909 
6910         u8         reserved_at_60[0x20];
6911 
6912         u8         table_type[0x8];
6913         u8         reserved_at_88[0x18];
6914 
6915         u8         reserved_at_a0[0x8];
6916         u8         table_id[0x18];
6917 
6918         u8         group_id[0x20];
6919 
6920         u8         reserved_at_e0[0x120];
6921 };
6922 
6923 struct mlx5_ifc_destroy_eq_out_bits {
6924         u8         status[0x8];
6925         u8         reserved_at_8[0x18];
6926 
6927         u8         syndrome[0x20];
6928 
6929         u8         reserved_at_40[0x40];
6930 };
6931 
6932 struct mlx5_ifc_destroy_eq_in_bits {
6933         u8         opcode[0x10];
6934         u8         reserved_at_10[0x10];
6935 
6936         u8         reserved_at_20[0x10];
6937         u8         op_mod[0x10];
6938 
6939         u8         reserved_at_40[0x18];
6940         u8         eq_number[0x8];
6941 
6942         u8         reserved_at_60[0x20];
6943 };
6944 
6945 struct mlx5_ifc_destroy_dct_out_bits {
6946         u8         status[0x8];
6947         u8         reserved_at_8[0x18];
6948 
6949         u8         syndrome[0x20];
6950 
6951         u8         reserved_at_40[0x40];
6952 };
6953 
6954 struct mlx5_ifc_destroy_dct_in_bits {
6955         u8         opcode[0x10];
6956         u8         uid[0x10];
6957 
6958         u8         reserved_at_20[0x10];
6959         u8         op_mod[0x10];
6960 
6961         u8         reserved_at_40[0x8];
6962         u8         dctn[0x18];
6963 
6964         u8         reserved_at_60[0x20];
6965 };
6966 
6967 struct mlx5_ifc_destroy_cq_out_bits {
6968         u8         status[0x8];
6969         u8         reserved_at_8[0x18];
6970 
6971         u8         syndrome[0x20];
6972 
6973         u8         reserved_at_40[0x40];
6974 };
6975 
6976 struct mlx5_ifc_destroy_cq_in_bits {
6977         u8         opcode[0x10];
6978         u8         uid[0x10];
6979 
6980         u8         reserved_at_20[0x10];
6981         u8         op_mod[0x10];
6982 
6983         u8         reserved_at_40[0x8];
6984         u8         cqn[0x18];
6985 
6986         u8         reserved_at_60[0x20];
6987 };
6988 
6989 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6990         u8         status[0x8];
6991         u8         reserved_at_8[0x18];
6992 
6993         u8         syndrome[0x20];
6994 
6995         u8         reserved_at_40[0x40];
6996 };
6997 
6998 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6999         u8         opcode[0x10];
7000         u8         reserved_at_10[0x10];
7001 
7002         u8         reserved_at_20[0x10];
7003         u8         op_mod[0x10];
7004 
7005         u8         reserved_at_40[0x20];
7006 
7007         u8         reserved_at_60[0x10];
7008         u8         vxlan_udp_port[0x10];
7009 };
7010 
7011 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7012         u8         status[0x8];
7013         u8         reserved_at_8[0x18];
7014 
7015         u8         syndrome[0x20];
7016 
7017         u8         reserved_at_40[0x40];
7018 };
7019 
7020 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7021         u8         opcode[0x10];
7022         u8         reserved_at_10[0x10];
7023 
7024         u8         reserved_at_20[0x10];
7025         u8         op_mod[0x10];
7026 
7027         u8         reserved_at_40[0x60];
7028 
7029         u8         reserved_at_a0[0x8];
7030         u8         table_index[0x18];
7031 
7032         u8         reserved_at_c0[0x140];
7033 };
7034 
7035 struct mlx5_ifc_delete_fte_out_bits {
7036         u8         status[0x8];
7037         u8         reserved_at_8[0x18];
7038 
7039         u8         syndrome[0x20];
7040 
7041         u8         reserved_at_40[0x40];
7042 };
7043 
7044 struct mlx5_ifc_delete_fte_in_bits {
7045         u8         opcode[0x10];
7046         u8         reserved_at_10[0x10];
7047 
7048         u8         reserved_at_20[0x10];
7049         u8         op_mod[0x10];
7050 
7051         u8         other_vport[0x1];
7052         u8         reserved_at_41[0xf];
7053         u8         vport_number[0x10];
7054 
7055         u8         reserved_at_60[0x20];
7056 
7057         u8         table_type[0x8];
7058         u8         reserved_at_88[0x18];
7059 
7060         u8         reserved_at_a0[0x8];
7061         u8         table_id[0x18];
7062 
7063         u8         reserved_at_c0[0x40];
7064 
7065         u8         flow_index[0x20];
7066 
7067         u8         reserved_at_120[0xe0];
7068 };
7069 
7070 struct mlx5_ifc_dealloc_xrcd_out_bits {
7071         u8         status[0x8];
7072         u8         reserved_at_8[0x18];
7073 
7074         u8         syndrome[0x20];
7075 
7076         u8         reserved_at_40[0x40];
7077 };
7078 
7079 struct mlx5_ifc_dealloc_xrcd_in_bits {
7080         u8         opcode[0x10];
7081         u8         uid[0x10];
7082 
7083         u8         reserved_at_20[0x10];
7084         u8         op_mod[0x10];
7085 
7086         u8         reserved_at_40[0x8];
7087         u8         xrcd[0x18];
7088 
7089         u8         reserved_at_60[0x20];
7090 };
7091 
7092 struct mlx5_ifc_dealloc_uar_out_bits {
7093         u8         status[0x8];
7094         u8         reserved_at_8[0x18];
7095 
7096         u8         syndrome[0x20];
7097 
7098         u8         reserved_at_40[0x40];
7099 };
7100 
7101 struct mlx5_ifc_dealloc_uar_in_bits {
7102         u8         opcode[0x10];
7103         u8         reserved_at_10[0x10];
7104 
7105         u8         reserved_at_20[0x10];
7106         u8         op_mod[0x10];
7107 
7108         u8         reserved_at_40[0x8];
7109         u8         uar[0x18];
7110 
7111         u8         reserved_at_60[0x20];
7112 };
7113 
7114 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7115         u8         status[0x8];
7116         u8         reserved_at_8[0x18];
7117 
7118         u8         syndrome[0x20];
7119 
7120         u8         reserved_at_40[0x40];
7121 };
7122 
7123 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7124         u8         opcode[0x10];
7125         u8         uid[0x10];
7126 
7127         u8         reserved_at_20[0x10];
7128         u8         op_mod[0x10];
7129 
7130         u8         reserved_at_40[0x8];
7131         u8         transport_domain[0x18];
7132 
7133         u8         reserved_at_60[0x20];
7134 };
7135 
7136 struct mlx5_ifc_dealloc_q_counter_out_bits {
7137         u8         status[0x8];
7138         u8         reserved_at_8[0x18];
7139 
7140         u8         syndrome[0x20];
7141 
7142         u8         reserved_at_40[0x40];
7143 };
7144 
7145 struct mlx5_ifc_dealloc_q_counter_in_bits {
7146         u8         opcode[0x10];
7147         u8         reserved_at_10[0x10];
7148 
7149         u8         reserved_at_20[0x10];
7150         u8         op_mod[0x10];
7151 
7152         u8         reserved_at_40[0x18];
7153         u8         counter_set_id[0x8];
7154 
7155         u8         reserved_at_60[0x20];
7156 };
7157 
7158 struct mlx5_ifc_dealloc_pd_out_bits {
7159         u8         status[0x8];
7160         u8         reserved_at_8[0x18];
7161 
7162         u8         syndrome[0x20];
7163 
7164         u8         reserved_at_40[0x40];
7165 };
7166 
7167 struct mlx5_ifc_dealloc_pd_in_bits {
7168         u8         opcode[0x10];
7169         u8         uid[0x10];
7170 
7171         u8         reserved_at_20[0x10];
7172         u8         op_mod[0x10];
7173 
7174         u8         reserved_at_40[0x8];
7175         u8         pd[0x18];
7176 
7177         u8         reserved_at_60[0x20];
7178 };
7179 
7180 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7181         u8         status[0x8];
7182         u8         reserved_at_8[0x18];
7183 
7184         u8         syndrome[0x20];
7185 
7186         u8         reserved_at_40[0x40];
7187 };
7188 
7189 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7190         u8         opcode[0x10];
7191         u8         reserved_at_10[0x10];
7192 
7193         u8         reserved_at_20[0x10];
7194         u8         op_mod[0x10];
7195 
7196         u8         flow_counter_id[0x20];
7197 
7198         u8         reserved_at_60[0x20];
7199 };
7200 
7201 struct mlx5_ifc_create_xrq_out_bits {
7202         u8         status[0x8];
7203         u8         reserved_at_8[0x18];
7204 
7205         u8         syndrome[0x20];
7206 
7207         u8         reserved_at_40[0x8];
7208         u8         xrqn[0x18];
7209 
7210         u8         reserved_at_60[0x20];
7211 };
7212 
7213 struct mlx5_ifc_create_xrq_in_bits {
7214         u8         opcode[0x10];
7215         u8         uid[0x10];
7216 
7217         u8         reserved_at_20[0x10];
7218         u8         op_mod[0x10];
7219 
7220         u8         reserved_at_40[0x40];
7221 
7222         struct mlx5_ifc_xrqc_bits xrq_context;
7223 };
7224 
7225 struct mlx5_ifc_create_xrc_srq_out_bits {
7226         u8         status[0x8];
7227         u8         reserved_at_8[0x18];
7228 
7229         u8         syndrome[0x20];
7230 
7231         u8         reserved_at_40[0x8];
7232         u8         xrc_srqn[0x18];
7233 
7234         u8         reserved_at_60[0x20];
7235 };
7236 
7237 struct mlx5_ifc_create_xrc_srq_in_bits {
7238         u8         opcode[0x10];
7239         u8         uid[0x10];
7240 
7241         u8         reserved_at_20[0x10];
7242         u8         op_mod[0x10];
7243 
7244         u8         reserved_at_40[0x40];
7245 
7246         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7247 
7248         u8         reserved_at_280[0x60];
7249 
7250         u8         xrc_srq_umem_valid[0x1];
7251         u8         reserved_at_2e1[0x1f];
7252 
7253         u8         reserved_at_300[0x580];
7254 
7255         u8         pas[0][0x40];
7256 };
7257 
7258 struct mlx5_ifc_create_tis_out_bits {
7259         u8         status[0x8];
7260         u8         reserved_at_8[0x18];
7261 
7262         u8         syndrome[0x20];
7263 
7264         u8         reserved_at_40[0x8];
7265         u8         tisn[0x18];
7266 
7267         u8         reserved_at_60[0x20];
7268 };
7269 
7270 struct mlx5_ifc_create_tis_in_bits {
7271         u8         opcode[0x10];
7272         u8         uid[0x10];
7273 
7274         u8         reserved_at_20[0x10];
7275         u8         op_mod[0x10];
7276 
7277         u8         reserved_at_40[0xc0];
7278 
7279         struct mlx5_ifc_tisc_bits ctx;
7280 };
7281 
7282 struct mlx5_ifc_create_tir_out_bits {
7283         u8         status[0x8];
7284         u8         icm_address_63_40[0x18];
7285 
7286         u8         syndrome[0x20];
7287 
7288         u8         icm_address_39_32[0x8];
7289         u8         tirn[0x18];
7290 
7291         u8         icm_address_31_0[0x20];
7292 };
7293 
7294 struct mlx5_ifc_create_tir_in_bits {
7295         u8         opcode[0x10];
7296         u8         uid[0x10];
7297 
7298         u8         reserved_at_20[0x10];
7299         u8         op_mod[0x10];
7300 
7301         u8         reserved_at_40[0xc0];
7302 
7303         struct mlx5_ifc_tirc_bits ctx;
7304 };
7305 
7306 struct mlx5_ifc_create_srq_out_bits {
7307         u8         status[0x8];
7308         u8         reserved_at_8[0x18];
7309 
7310         u8         syndrome[0x20];
7311 
7312         u8         reserved_at_40[0x8];
7313         u8         srqn[0x18];
7314 
7315         u8         reserved_at_60[0x20];
7316 };
7317 
7318 struct mlx5_ifc_create_srq_in_bits {
7319         u8         opcode[0x10];
7320         u8         uid[0x10];
7321 
7322         u8         reserved_at_20[0x10];
7323         u8         op_mod[0x10];
7324 
7325         u8         reserved_at_40[0x40];
7326 
7327         struct mlx5_ifc_srqc_bits srq_context_entry;
7328 
7329         u8         reserved_at_280[0x600];
7330 
7331         u8         pas[0][0x40];
7332 };
7333 
7334 struct mlx5_ifc_create_sq_out_bits {
7335         u8         status[0x8];
7336         u8         reserved_at_8[0x18];
7337 
7338         u8         syndrome[0x20];
7339 
7340         u8         reserved_at_40[0x8];
7341         u8         sqn[0x18];
7342 
7343         u8         reserved_at_60[0x20];
7344 };
7345 
7346 struct mlx5_ifc_create_sq_in_bits {
7347         u8         opcode[0x10];
7348         u8         uid[0x10];
7349 
7350         u8         reserved_at_20[0x10];
7351         u8         op_mod[0x10];
7352 
7353         u8         reserved_at_40[0xc0];
7354 
7355         struct mlx5_ifc_sqc_bits ctx;
7356 };
7357 
7358 struct mlx5_ifc_create_scheduling_element_out_bits {
7359         u8         status[0x8];
7360         u8         reserved_at_8[0x18];
7361 
7362         u8         syndrome[0x20];
7363 
7364         u8         reserved_at_40[0x40];
7365 
7366         u8         scheduling_element_id[0x20];
7367 
7368         u8         reserved_at_a0[0x160];
7369 };
7370 
7371 struct mlx5_ifc_create_scheduling_element_in_bits {
7372         u8         opcode[0x10];
7373         u8         reserved_at_10[0x10];
7374 
7375         u8         reserved_at_20[0x10];
7376         u8         op_mod[0x10];
7377 
7378         u8         scheduling_hierarchy[0x8];
7379         u8         reserved_at_48[0x18];
7380 
7381         u8         reserved_at_60[0xa0];
7382 
7383         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7384 
7385         u8         reserved_at_300[0x100];
7386 };
7387 
7388 struct mlx5_ifc_create_rqt_out_bits {
7389         u8         status[0x8];
7390         u8         reserved_at_8[0x18];
7391 
7392         u8         syndrome[0x20];
7393 
7394         u8         reserved_at_40[0x8];
7395         u8         rqtn[0x18];
7396 
7397         u8         reserved_at_60[0x20];
7398 };
7399 
7400 struct mlx5_ifc_create_rqt_in_bits {
7401         u8         opcode[0x10];
7402         u8         uid[0x10];
7403 
7404         u8         reserved_at_20[0x10];
7405         u8         op_mod[0x10];
7406 
7407         u8         reserved_at_40[0xc0];
7408 
7409         struct mlx5_ifc_rqtc_bits rqt_context;
7410 };
7411 
7412 struct mlx5_ifc_create_rq_out_bits {
7413         u8         status[0x8];
7414         u8         reserved_at_8[0x18];
7415 
7416         u8         syndrome[0x20];
7417 
7418         u8         reserved_at_40[0x8];
7419         u8         rqn[0x18];
7420 
7421         u8         reserved_at_60[0x20];
7422 };
7423 
7424 struct mlx5_ifc_create_rq_in_bits {
7425         u8         opcode[0x10];
7426         u8         uid[0x10];
7427 
7428         u8         reserved_at_20[0x10];
7429         u8         op_mod[0x10];
7430 
7431         u8         reserved_at_40[0xc0];
7432 
7433         struct mlx5_ifc_rqc_bits ctx;
7434 };
7435 
7436 struct mlx5_ifc_create_rmp_out_bits {
7437         u8         status[0x8];
7438         u8         reserved_at_8[0x18];
7439 
7440         u8         syndrome[0x20];
7441 
7442         u8         reserved_at_40[0x8];
7443         u8         rmpn[0x18];
7444 
7445         u8         reserved_at_60[0x20];
7446 };
7447 
7448 struct mlx5_ifc_create_rmp_in_bits {
7449         u8         opcode[0x10];
7450         u8         uid[0x10];
7451 
7452         u8         reserved_at_20[0x10];
7453         u8         op_mod[0x10];
7454 
7455         u8         reserved_at_40[0xc0];
7456 
7457         struct mlx5_ifc_rmpc_bits ctx;
7458 };
7459 
7460 struct mlx5_ifc_create_qp_out_bits {
7461         u8         status[0x8];
7462         u8         reserved_at_8[0x18];
7463 
7464         u8         syndrome[0x20];
7465 
7466         u8         reserved_at_40[0x8];
7467         u8         qpn[0x18];
7468 
7469         u8         reserved_at_60[0x20];
7470 };
7471 
7472 struct mlx5_ifc_create_qp_in_bits {
7473         u8         opcode[0x10];
7474         u8         uid[0x10];
7475 
7476         u8         reserved_at_20[0x10];
7477         u8         op_mod[0x10];
7478 
7479         u8         reserved_at_40[0x40];
7480 
7481         u8         opt_param_mask[0x20];
7482 
7483         u8         reserved_at_a0[0x20];
7484 
7485         struct mlx5_ifc_qpc_bits qpc;
7486 
7487         u8         reserved_at_800[0x60];
7488 
7489         u8         wq_umem_valid[0x1];
7490         u8         reserved_at_861[0x1f];
7491 
7492         u8         pas[0][0x40];
7493 };
7494 
7495 struct mlx5_ifc_create_psv_out_bits {
7496         u8         status[0x8];
7497         u8         reserved_at_8[0x18];
7498 
7499         u8         syndrome[0x20];
7500 
7501         u8         reserved_at_40[0x40];
7502 
7503         u8         reserved_at_80[0x8];
7504         u8         psv0_index[0x18];
7505 
7506         u8         reserved_at_a0[0x8];
7507         u8         psv1_index[0x18];
7508 
7509         u8         reserved_at_c0[0x8];
7510         u8         psv2_index[0x18];
7511 
7512         u8         reserved_at_e0[0x8];
7513         u8         psv3_index[0x18];
7514 };
7515 
7516 struct mlx5_ifc_create_psv_in_bits {
7517         u8         opcode[0x10];
7518         u8         reserved_at_10[0x10];
7519 
7520         u8         reserved_at_20[0x10];
7521         u8         op_mod[0x10];
7522 
7523         u8         num_psv[0x4];
7524         u8         reserved_at_44[0x4];
7525         u8         pd[0x18];
7526 
7527         u8         reserved_at_60[0x20];
7528 };
7529 
7530 struct mlx5_ifc_create_mkey_out_bits {
7531         u8         status[0x8];
7532         u8         reserved_at_8[0x18];
7533 
7534         u8         syndrome[0x20];
7535 
7536         u8         reserved_at_40[0x8];
7537         u8         mkey_index[0x18];
7538 
7539         u8         reserved_at_60[0x20];
7540 };
7541 
7542 struct mlx5_ifc_create_mkey_in_bits {
7543         u8         opcode[0x10];
7544         u8         reserved_at_10[0x10];
7545 
7546         u8         reserved_at_20[0x10];
7547         u8         op_mod[0x10];
7548 
7549         u8         reserved_at_40[0x20];
7550 
7551         u8         pg_access[0x1];
7552         u8         mkey_umem_valid[0x1];
7553         u8         reserved_at_62[0x1e];
7554 
7555         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7556 
7557         u8         reserved_at_280[0x80];
7558 
7559         u8         translations_octword_actual_size[0x20];
7560 
7561         u8         reserved_at_320[0x560];
7562 
7563         u8         klm_pas_mtt[0][0x20];
7564 };
7565 
7566 enum {
7567         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7568         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7569         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7570         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7571         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7572         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7573         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7574 };
7575 
7576 struct mlx5_ifc_create_flow_table_out_bits {
7577         u8         status[0x8];
7578         u8         icm_address_63_40[0x18];
7579 
7580         u8         syndrome[0x20];
7581 
7582         u8         icm_address_39_32[0x8];
7583         u8         table_id[0x18];
7584 
7585         u8         icm_address_31_0[0x20];
7586 };
7587 
7588 struct mlx5_ifc_create_flow_table_in_bits {
7589         u8         opcode[0x10];
7590         u8         reserved_at_10[0x10];
7591 
7592         u8         reserved_at_20[0x10];
7593         u8         op_mod[0x10];
7594 
7595         u8         other_vport[0x1];
7596         u8         reserved_at_41[0xf];
7597         u8         vport_number[0x10];
7598 
7599         u8         reserved_at_60[0x20];
7600 
7601         u8         table_type[0x8];
7602         u8         reserved_at_88[0x18];
7603 
7604         u8         reserved_at_a0[0x20];
7605 
7606         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7607 };
7608 
7609 struct mlx5_ifc_create_flow_group_out_bits {
7610         u8         status[0x8];
7611         u8         reserved_at_8[0x18];
7612 
7613         u8         syndrome[0x20];
7614 
7615         u8         reserved_at_40[0x8];
7616         u8         group_id[0x18];
7617 
7618         u8         reserved_at_60[0x20];
7619 };
7620 
7621 enum {
7622         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7623         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7624         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7625         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7626 };
7627 
7628 struct mlx5_ifc_create_flow_group_in_bits {
7629         u8         opcode[0x10];
7630         u8         reserved_at_10[0x10];
7631 
7632         u8         reserved_at_20[0x10];
7633         u8         op_mod[0x10];
7634 
7635         u8         other_vport[0x1];
7636         u8         reserved_at_41[0xf];
7637         u8         vport_number[0x10];
7638 
7639         u8         reserved_at_60[0x20];
7640 
7641         u8         table_type[0x8];
7642         u8         reserved_at_88[0x18];
7643 
7644         u8         reserved_at_a0[0x8];
7645         u8         table_id[0x18];
7646 
7647         u8         source_eswitch_owner_vhca_id_valid[0x1];
7648 
7649         u8         reserved_at_c1[0x1f];
7650 
7651         u8         start_flow_index[0x20];
7652 
7653         u8         reserved_at_100[0x20];
7654 
7655         u8         end_flow_index[0x20];
7656 
7657         u8         reserved_at_140[0xa0];
7658 
7659         u8         reserved_at_1e0[0x18];
7660         u8         match_criteria_enable[0x8];
7661 
7662         struct mlx5_ifc_fte_match_param_bits match_criteria;
7663 
7664         u8         reserved_at_1200[0xe00];
7665 };
7666 
7667 struct mlx5_ifc_create_eq_out_bits {
7668         u8         status[0x8];
7669         u8         reserved_at_8[0x18];
7670 
7671         u8         syndrome[0x20];
7672 
7673         u8         reserved_at_40[0x18];
7674         u8         eq_number[0x8];
7675 
7676         u8         reserved_at_60[0x20];
7677 };
7678 
7679 struct mlx5_ifc_create_eq_in_bits {
7680         u8         opcode[0x10];
7681         u8         uid[0x10];
7682 
7683         u8         reserved_at_20[0x10];
7684         u8         op_mod[0x10];
7685 
7686         u8         reserved_at_40[0x40];
7687 
7688         struct mlx5_ifc_eqc_bits eq_context_entry;
7689 
7690         u8         reserved_at_280[0x40];
7691 
7692         u8         event_bitmask[4][0x40];
7693 
7694         u8         reserved_at_3c0[0x4c0];
7695 
7696         u8         pas[0][0x40];
7697 };
7698 
7699 struct mlx5_ifc_create_dct_out_bits {
7700         u8         status[0x8];
7701         u8         reserved_at_8[0x18];
7702 
7703         u8         syndrome[0x20];
7704 
7705         u8         reserved_at_40[0x8];
7706         u8         dctn[0x18];
7707 
7708         u8         reserved_at_60[0x20];
7709 };
7710 
7711 struct mlx5_ifc_create_dct_in_bits {
7712         u8         opcode[0x10];
7713         u8         uid[0x10];
7714 
7715         u8         reserved_at_20[0x10];
7716         u8         op_mod[0x10];
7717 
7718         u8         reserved_at_40[0x40];
7719 
7720         struct mlx5_ifc_dctc_bits dct_context_entry;
7721 
7722         u8         reserved_at_280[0x180];
7723 };
7724 
7725 struct mlx5_ifc_create_cq_out_bits {
7726         u8         status[0x8];
7727         u8         reserved_at_8[0x18];
7728 
7729         u8         syndrome[0x20];
7730 
7731         u8         reserved_at_40[0x8];
7732         u8         cqn[0x18];
7733 
7734         u8         reserved_at_60[0x20];
7735 };
7736 
7737 struct mlx5_ifc_create_cq_in_bits {
7738         u8         opcode[0x10];
7739         u8         uid[0x10];
7740 
7741         u8         reserved_at_20[0x10];
7742         u8         op_mod[0x10];
7743 
7744         u8         reserved_at_40[0x40];
7745 
7746         struct mlx5_ifc_cqc_bits cq_context;
7747 
7748         u8         reserved_at_280[0x60];
7749 
7750         u8         cq_umem_valid[0x1];
7751         u8         reserved_at_2e1[0x59f];
7752 
7753         u8         pas[0][0x40];
7754 };
7755 
7756 struct mlx5_ifc_config_int_moderation_out_bits {
7757         u8         status[0x8];
7758         u8         reserved_at_8[0x18];
7759 
7760         u8         syndrome[0x20];
7761 
7762         u8         reserved_at_40[0x4];
7763         u8         min_delay[0xc];
7764         u8         int_vector[0x10];
7765 
7766         u8         reserved_at_60[0x20];
7767 };
7768 
7769 enum {
7770         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7771         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7772 };
7773 
7774 struct mlx5_ifc_config_int_moderation_in_bits {
7775         u8         opcode[0x10];
7776         u8         reserved_at_10[0x10];
7777 
7778         u8         reserved_at_20[0x10];
7779         u8         op_mod[0x10];
7780 
7781         u8         reserved_at_40[0x4];
7782         u8         min_delay[0xc];
7783         u8         int_vector[0x10];
7784 
7785         u8         reserved_at_60[0x20];
7786 };
7787 
7788 struct mlx5_ifc_attach_to_mcg_out_bits {
7789         u8         status[0x8];
7790         u8         reserved_at_8[0x18];
7791 
7792         u8         syndrome[0x20];
7793 
7794         u8         reserved_at_40[0x40];
7795 };
7796 
7797 struct mlx5_ifc_attach_to_mcg_in_bits {
7798         u8         opcode[0x10];
7799         u8         uid[0x10];
7800 
7801         u8         reserved_at_20[0x10];
7802         u8         op_mod[0x10];
7803 
7804         u8         reserved_at_40[0x8];
7805         u8         qpn[0x18];
7806 
7807         u8         reserved_at_60[0x20];
7808 
7809         u8         multicast_gid[16][0x8];
7810 };
7811 
7812 struct mlx5_ifc_arm_xrq_out_bits {
7813         u8         status[0x8];
7814         u8         reserved_at_8[0x18];
7815 
7816         u8         syndrome[0x20];
7817 
7818         u8         reserved_at_40[0x40];
7819 };
7820 
7821 struct mlx5_ifc_arm_xrq_in_bits {
7822         u8         opcode[0x10];
7823         u8         reserved_at_10[0x10];
7824 
7825         u8         reserved_at_20[0x10];
7826         u8         op_mod[0x10];
7827 
7828         u8         reserved_at_40[0x8];
7829         u8         xrqn[0x18];
7830 
7831         u8         reserved_at_60[0x10];
7832         u8         lwm[0x10];
7833 };
7834 
7835 struct mlx5_ifc_arm_xrc_srq_out_bits {
7836         u8         status[0x8];
7837         u8         reserved_at_8[0x18];
7838 
7839         u8         syndrome[0x20];
7840 
7841         u8         reserved_at_40[0x40];
7842 };
7843 
7844 enum {
7845         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7846 };
7847 
7848 struct mlx5_ifc_arm_xrc_srq_in_bits {
7849         u8         opcode[0x10];
7850         u8         uid[0x10];
7851 
7852         u8         reserved_at_20[0x10];
7853         u8         op_mod[0x10];
7854 
7855         u8         reserved_at_40[0x8];
7856         u8         xrc_srqn[0x18];
7857 
7858         u8         reserved_at_60[0x10];
7859         u8         lwm[0x10];
7860 };
7861 
7862 struct mlx5_ifc_arm_rq_out_bits {
7863         u8         status[0x8];
7864         u8         reserved_at_8[0x18];
7865 
7866         u8         syndrome[0x20];
7867 
7868         u8         reserved_at_40[0x40];
7869 };
7870 
7871 enum {
7872         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7873         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7874 };
7875 
7876 struct mlx5_ifc_arm_rq_in_bits {
7877         u8         opcode[0x10];
7878         u8         uid[0x10];
7879 
7880         u8         reserved_at_20[0x10];
7881         u8         op_mod[0x10];
7882 
7883         u8         reserved_at_40[0x8];
7884         u8         srq_number[0x18];
7885 
7886         u8         reserved_at_60[0x10];
7887         u8         lwm[0x10];
7888 };
7889 
7890 struct mlx5_ifc_arm_dct_out_bits {
7891         u8         status[0x8];
7892         u8         reserved_at_8[0x18];
7893 
7894         u8         syndrome[0x20];
7895 
7896         u8         reserved_at_40[0x40];
7897 };
7898 
7899 struct mlx5_ifc_arm_dct_in_bits {
7900         u8         opcode[0x10];
7901         u8         reserved_at_10[0x10];
7902 
7903         u8         reserved_at_20[0x10];
7904         u8         op_mod[0x10];
7905 
7906         u8         reserved_at_40[0x8];
7907         u8         dct_number[0x18];
7908 
7909         u8         reserved_at_60[0x20];
7910 };
7911 
7912 struct mlx5_ifc_alloc_xrcd_out_bits {
7913         u8         status[0x8];
7914         u8         reserved_at_8[0x18];
7915 
7916         u8         syndrome[0x20];
7917 
7918         u8         reserved_at_40[0x8];
7919         u8         xrcd[0x18];
7920 
7921         u8         reserved_at_60[0x20];
7922 };
7923 
7924 struct mlx5_ifc_alloc_xrcd_in_bits {
7925         u8         opcode[0x10];
7926         u8         uid[0x10];
7927 
7928         u8         reserved_at_20[0x10];
7929         u8         op_mod[0x10];
7930 
7931         u8         reserved_at_40[0x40];
7932 };
7933 
7934 struct mlx5_ifc_alloc_uar_out_bits {
7935         u8         status[0x8];
7936         u8         reserved_at_8[0x18];
7937 
7938         u8         syndrome[0x20];
7939 
7940         u8         reserved_at_40[0x8];
7941         u8         uar[0x18];
7942 
7943         u8         reserved_at_60[0x20];
7944 };
7945 
7946 struct mlx5_ifc_alloc_uar_in_bits {
7947         u8         opcode[0x10];
7948         u8         reserved_at_10[0x10];
7949 
7950         u8         reserved_at_20[0x10];
7951         u8         op_mod[0x10];
7952 
7953         u8         reserved_at_40[0x40];
7954 };
7955 
7956 struct mlx5_ifc_alloc_transport_domain_out_bits {
7957         u8         status[0x8];
7958         u8         reserved_at_8[0x18];
7959 
7960         u8         syndrome[0x20];
7961 
7962         u8         reserved_at_40[0x8];
7963         u8         transport_domain[0x18];
7964 
7965         u8         reserved_at_60[0x20];
7966 };
7967 
7968 struct mlx5_ifc_alloc_transport_domain_in_bits {
7969         u8         opcode[0x10];
7970         u8         uid[0x10];
7971 
7972         u8         reserved_at_20[0x10];
7973         u8         op_mod[0x10];
7974 
7975         u8         reserved_at_40[0x40];
7976 };
7977 
7978 struct mlx5_ifc_alloc_q_counter_out_bits {
7979         u8         status[0x8];
7980         u8         reserved_at_8[0x18];
7981 
7982         u8         syndrome[0x20];
7983 
7984         u8         reserved_at_40[0x18];
7985         u8         counter_set_id[0x8];
7986 
7987         u8         reserved_at_60[0x20];
7988 };
7989 
7990 struct mlx5_ifc_alloc_q_counter_in_bits {
7991         u8         opcode[0x10];
7992         u8         uid[0x10];
7993 
7994         u8         reserved_at_20[0x10];
7995         u8         op_mod[0x10];
7996 
7997         u8         reserved_at_40[0x40];
7998 };
7999 
8000 struct mlx5_ifc_alloc_pd_out_bits {
8001         u8         status[0x8];
8002         u8         reserved_at_8[0x18];
8003 
8004         u8         syndrome[0x20];
8005 
8006         u8         reserved_at_40[0x8];
8007         u8         pd[0x18];
8008 
8009         u8         reserved_at_60[0x20];
8010 };
8011 
8012 struct mlx5_ifc_alloc_pd_in_bits {
8013         u8         opcode[0x10];
8014         u8         uid[0x10];
8015 
8016         u8         reserved_at_20[0x10];
8017         u8         op_mod[0x10];
8018 
8019         u8         reserved_at_40[0x40];
8020 };
8021 
8022 struct mlx5_ifc_alloc_flow_counter_out_bits {
8023         u8         status[0x8];
8024         u8         reserved_at_8[0x18];
8025 
8026         u8         syndrome[0x20];
8027 
8028         u8         flow_counter_id[0x20];
8029 
8030         u8         reserved_at_60[0x20];
8031 };
8032 
8033 struct mlx5_ifc_alloc_flow_counter_in_bits {
8034         u8         opcode[0x10];
8035         u8         reserved_at_10[0x10];
8036 
8037         u8         reserved_at_20[0x10];
8038         u8         op_mod[0x10];
8039 
8040         u8         reserved_at_40[0x38];
8041         u8         flow_counter_bulk[0x8];
8042 };
8043 
8044 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8045         u8         status[0x8];
8046         u8         reserved_at_8[0x18];
8047 
8048         u8         syndrome[0x20];
8049 
8050         u8         reserved_at_40[0x40];
8051 };
8052 
8053 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8054         u8         opcode[0x10];
8055         u8         reserved_at_10[0x10];
8056 
8057         u8         reserved_at_20[0x10];
8058         u8         op_mod[0x10];
8059 
8060         u8         reserved_at_40[0x20];
8061 
8062         u8         reserved_at_60[0x10];
8063         u8         vxlan_udp_port[0x10];
8064 };
8065 
8066 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8067         u8         status[0x8];
8068         u8         reserved_at_8[0x18];
8069 
8070         u8         syndrome[0x20];
8071 
8072         u8         reserved_at_40[0x40];
8073 };
8074 
8075 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8076         u8         opcode[0x10];
8077         u8         reserved_at_10[0x10];
8078 
8079         u8         reserved_at_20[0x10];
8080         u8         op_mod[0x10];
8081 
8082         u8         reserved_at_40[0x10];
8083         u8         rate_limit_index[0x10];
8084 
8085         u8         reserved_at_60[0x20];
8086 
8087         u8         rate_limit[0x20];
8088 
8089         u8         burst_upper_bound[0x20];
8090 
8091         u8         reserved_at_c0[0x10];
8092         u8         typical_packet_size[0x10];
8093 
8094         u8         reserved_at_e0[0x120];
8095 };
8096 
8097 struct mlx5_ifc_access_register_out_bits {
8098         u8         status[0x8];
8099         u8         reserved_at_8[0x18];
8100 
8101         u8         syndrome[0x20];
8102 
8103         u8         reserved_at_40[0x40];
8104 
8105         u8         register_data[0][0x20];
8106 };
8107 
8108 enum {
8109         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8110         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8111 };
8112 
8113 struct mlx5_ifc_access_register_in_bits {
8114         u8         opcode[0x10];
8115         u8         reserved_at_10[0x10];
8116 
8117         u8         reserved_at_20[0x10];
8118         u8         op_mod[0x10];
8119 
8120         u8         reserved_at_40[0x10];
8121         u8         register_id[0x10];
8122 
8123         u8         argument[0x20];
8124 
8125         u8         register_data[0][0x20];
8126 };
8127 
8128 struct mlx5_ifc_sltp_reg_bits {
8129         u8         status[0x4];
8130         u8         version[0x4];
8131         u8         local_port[0x8];
8132         u8         pnat[0x2];
8133         u8         reserved_at_12[0x2];
8134         u8         lane[0x4];
8135         u8         reserved_at_18[0x8];
8136 
8137         u8         reserved_at_20[0x20];
8138 
8139         u8         reserved_at_40[0x7];
8140         u8         polarity[0x1];
8141         u8         ob_tap0[0x8];
8142         u8         ob_tap1[0x8];
8143         u8         ob_tap2[0x8];
8144 
8145         u8         reserved_at_60[0xc];
8146         u8         ob_preemp_mode[0x4];
8147         u8         ob_reg[0x8];
8148         u8         ob_bias[0x8];
8149 
8150         u8         reserved_at_80[0x20];
8151 };
8152 
8153 struct mlx5_ifc_slrg_reg_bits {
8154         u8         status[0x4];
8155         u8         version[0x4];
8156         u8         local_port[0x8];
8157         u8         pnat[0x2];
8158         u8         reserved_at_12[0x2];
8159         u8         lane[0x4];
8160         u8         reserved_at_18[0x8];
8161 
8162         u8         time_to_link_up[0x10];
8163         u8         reserved_at_30[0xc];
8164         u8         grade_lane_speed[0x4];
8165 
8166         u8         grade_version[0x8];
8167         u8         grade[0x18];
8168 
8169         u8         reserved_at_60[0x4];
8170         u8         height_grade_type[0x4];
8171         u8         height_grade[0x18];
8172 
8173         u8         height_dz[0x10];
8174         u8         height_dv[0x10];
8175 
8176         u8         reserved_at_a0[0x10];
8177         u8         height_sigma[0x10];
8178 
8179         u8         reserved_at_c0[0x20];
8180 
8181         u8         reserved_at_e0[0x4];
8182         u8         phase_grade_type[0x4];
8183         u8         phase_grade[0x18];
8184 
8185         u8         reserved_at_100[0x8];
8186         u8         phase_eo_pos[0x8];
8187         u8         reserved_at_110[0x8];
8188         u8         phase_eo_neg[0x8];
8189 
8190         u8         ffe_set_tested[0x10];
8191         u8         test_errors_per_lane[0x10];
8192 };
8193 
8194 struct mlx5_ifc_pvlc_reg_bits {
8195         u8         reserved_at_0[0x8];
8196         u8         local_port[0x8];
8197         u8         reserved_at_10[0x10];
8198 
8199         u8         reserved_at_20[0x1c];
8200         u8         vl_hw_cap[0x4];
8201 
8202         u8         reserved_at_40[0x1c];
8203         u8         vl_admin[0x4];
8204 
8205         u8         reserved_at_60[0x1c];
8206         u8         vl_operational[0x4];
8207 };
8208 
8209 struct mlx5_ifc_pude_reg_bits {
8210         u8         swid[0x8];
8211         u8         local_port[0x8];
8212         u8         reserved_at_10[0x4];
8213         u8         admin_status[0x4];
8214         u8         reserved_at_18[0x4];
8215         u8         oper_status[0x4];
8216 
8217         u8         reserved_at_20[0x60];
8218 };
8219 
8220 struct mlx5_ifc_ptys_reg_bits {
8221         u8         reserved_at_0[0x1];
8222         u8         an_disable_admin[0x1];
8223         u8         an_disable_cap[0x1];
8224         u8         reserved_at_3[0x5];
8225         u8         local_port[0x8];
8226         u8         reserved_at_10[0xd];
8227         u8         proto_mask[0x3];
8228 
8229         u8         an_status[0x4];
8230         u8         reserved_at_24[0x1c];
8231 
8232         u8         ext_eth_proto_capability[0x20];
8233 
8234         u8         eth_proto_capability[0x20];
8235 
8236         u8         ib_link_width_capability[0x10];
8237         u8         ib_proto_capability[0x10];
8238 
8239         u8         ext_eth_proto_admin[0x20];
8240 
8241         u8         eth_proto_admin[0x20];
8242 
8243         u8         ib_link_width_admin[0x10];
8244         u8         ib_proto_admin[0x10];
8245 
8246         u8         ext_eth_proto_oper[0x20];
8247 
8248         u8         eth_proto_oper[0x20];
8249 
8250         u8         ib_link_width_oper[0x10];
8251         u8         ib_proto_oper[0x10];
8252 
8253         u8         reserved_at_160[0x1c];
8254         u8         connector_type[0x4];
8255 
8256         u8         eth_proto_lp_advertise[0x20];
8257 
8258         u8         reserved_at_1a0[0x60];
8259 };
8260 
8261 struct mlx5_ifc_mlcr_reg_bits {
8262         u8         reserved_at_0[0x8];
8263         u8         local_port[0x8];
8264         u8         reserved_at_10[0x20];
8265 
8266         u8         beacon_duration[0x10];
8267         u8         reserved_at_40[0x10];
8268 
8269         u8         beacon_remain[0x10];
8270 };
8271 
8272 struct mlx5_ifc_ptas_reg_bits {
8273         u8         reserved_at_0[0x20];
8274 
8275         u8         algorithm_options[0x10];
8276         u8         reserved_at_30[0x4];
8277         u8         repetitions_mode[0x4];
8278         u8         num_of_repetitions[0x8];
8279 
8280         u8         grade_version[0x8];
8281         u8         height_grade_type[0x4];
8282         u8         phase_grade_type[0x4];
8283         u8         height_grade_weight[0x8];
8284         u8         phase_grade_weight[0x8];
8285 
8286         u8         gisim_measure_bits[0x10];
8287         u8         adaptive_tap_measure_bits[0x10];
8288 
8289         u8         ber_bath_high_error_threshold[0x10];
8290         u8         ber_bath_mid_error_threshold[0x10];
8291 
8292         u8         ber_bath_low_error_threshold[0x10];
8293         u8         one_ratio_high_threshold[0x10];
8294 
8295         u8         one_ratio_high_mid_threshold[0x10];
8296         u8         one_ratio_low_mid_threshold[0x10];
8297 
8298         u8         one_ratio_low_threshold[0x10];
8299         u8         ndeo_error_threshold[0x10];
8300 
8301         u8         mixer_offset_step_size[0x10];
8302         u8         reserved_at_110[0x8];
8303         u8         mix90_phase_for_voltage_bath[0x8];
8304 
8305         u8         mixer_offset_start[0x10];
8306         u8         mixer_offset_end[0x10];
8307 
8308         u8         reserved_at_140[0x15];
8309         u8         ber_test_time[0xb];
8310 };
8311 
8312 struct mlx5_ifc_pspa_reg_bits {
8313         u8         swid[0x8];
8314         u8         local_port[0x8];
8315         u8         sub_port[0x8];
8316         u8         reserved_at_18[0x8];
8317 
8318         u8         reserved_at_20[0x20];
8319 };
8320 
8321 struct mlx5_ifc_pqdr_reg_bits {
8322         u8         reserved_at_0[0x8];
8323         u8         local_port[0x8];
8324         u8         reserved_at_10[0x5];
8325         u8         prio[0x3];
8326         u8         reserved_at_18[0x6];
8327         u8         mode[0x2];
8328 
8329         u8         reserved_at_20[0x20];
8330 
8331         u8         reserved_at_40[0x10];
8332         u8         min_threshold[0x10];
8333 
8334         u8         reserved_at_60[0x10];
8335         u8         max_threshold[0x10];
8336 
8337         u8         reserved_at_80[0x10];
8338         u8         mark_probability_denominator[0x10];
8339 
8340         u8         reserved_at_a0[0x60];
8341 };
8342 
8343 struct mlx5_ifc_ppsc_reg_bits {
8344         u8         reserved_at_0[0x8];
8345         u8         local_port[0x8];
8346         u8         reserved_at_10[0x10];
8347 
8348         u8         reserved_at_20[0x60];
8349 
8350         u8         reserved_at_80[0x1c];
8351         u8         wrps_admin[0x4];
8352 
8353         u8         reserved_at_a0[0x1c];
8354         u8         wrps_status[0x4];
8355 
8356         u8         reserved_at_c0[0x8];
8357         u8         up_threshold[0x8];
8358         u8         reserved_at_d0[0x8];
8359         u8         down_threshold[0x8];
8360 
8361         u8         reserved_at_e0[0x20];
8362 
8363         u8         reserved_at_100[0x1c];
8364         u8         srps_admin[0x4];
8365 
8366         u8         reserved_at_120[0x1c];
8367         u8         srps_status[0x4];
8368 
8369         u8         reserved_at_140[0x40];
8370 };
8371 
8372 struct mlx5_ifc_pplr_reg_bits {
8373         u8         reserved_at_0[0x8];
8374         u8         local_port[0x8];
8375         u8         reserved_at_10[0x10];
8376 
8377         u8         reserved_at_20[0x8];
8378         u8         lb_cap[0x8];
8379         u8         reserved_at_30[0x8];
8380         u8         lb_en[0x8];
8381 };
8382 
8383 struct mlx5_ifc_pplm_reg_bits {
8384         u8         reserved_at_0[0x8];
8385         u8         local_port[0x8];
8386         u8         reserved_at_10[0x10];
8387 
8388         u8         reserved_at_20[0x20];
8389 
8390         u8         port_profile_mode[0x8];
8391         u8         static_port_profile[0x8];
8392         u8         active_port_profile[0x8];
8393         u8         reserved_at_58[0x8];
8394 
8395         u8         retransmission_active[0x8];
8396         u8         fec_mode_active[0x18];
8397 
8398         u8         rs_fec_correction_bypass_cap[0x4];
8399         u8         reserved_at_84[0x8];
8400         u8         fec_override_cap_56g[0x4];
8401         u8         fec_override_cap_100g[0x4];
8402         u8         fec_override_cap_50g[0x4];
8403         u8         fec_override_cap_25g[0x4];
8404         u8         fec_override_cap_10g_40g[0x4];
8405 
8406         u8         rs_fec_correction_bypass_admin[0x4];
8407         u8         reserved_at_a4[0x8];
8408         u8         fec_override_admin_56g[0x4];
8409         u8         fec_override_admin_100g[0x4];
8410         u8         fec_override_admin_50g[0x4];
8411         u8         fec_override_admin_25g[0x4];
8412         u8         fec_override_admin_10g_40g[0x4];
8413 };
8414 
8415 struct mlx5_ifc_ppcnt_reg_bits {
8416         u8         swid[0x8];
8417         u8         local_port[0x8];
8418         u8         pnat[0x2];
8419         u8         reserved_at_12[0x8];
8420         u8         grp[0x6];
8421 
8422         u8         clr[0x1];
8423         u8         reserved_at_21[0x1c];
8424         u8         prio_tc[0x3];
8425 
8426         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8427 };
8428 
8429 struct mlx5_ifc_mpein_reg_bits {
8430         u8         reserved_at_0[0x2];
8431         u8         depth[0x6];
8432         u8         pcie_index[0x8];
8433         u8         node[0x8];
8434         u8         reserved_at_18[0x8];
8435 
8436         u8         capability_mask[0x20];
8437 
8438         u8         reserved_at_40[0x8];
8439         u8         link_width_enabled[0x8];
8440         u8         link_speed_enabled[0x10];
8441 
8442         u8         lane0_physical_position[0x8];
8443         u8         link_width_active[0x8];
8444         u8         link_speed_active[0x10];
8445 
8446         u8         num_of_pfs[0x10];
8447         u8         num_of_vfs[0x10];
8448 
8449         u8         bdf0[0x10];
8450         u8         reserved_at_b0[0x10];
8451 
8452         u8         max_read_request_size[0x4];
8453         u8         max_payload_size[0x4];
8454         u8         reserved_at_c8[0x5];
8455         u8         pwr_status[0x3];
8456         u8         port_type[0x4];
8457         u8         reserved_at_d4[0xb];
8458         u8         lane_reversal[0x1];
8459 
8460         u8         reserved_at_e0[0x14];
8461         u8         pci_power[0xc];
8462 
8463         u8         reserved_at_100[0x20];
8464 
8465         u8         device_status[0x10];
8466         u8         port_state[0x8];
8467         u8         reserved_at_138[0x8];
8468 
8469         u8         reserved_at_140[0x10];
8470         u8         receiver_detect_result[0x10];
8471 
8472         u8         reserved_at_160[0x20];
8473 };
8474 
8475 struct mlx5_ifc_mpcnt_reg_bits {
8476         u8         reserved_at_0[0x8];
8477         u8         pcie_index[0x8];
8478         u8         reserved_at_10[0xa];
8479         u8         grp[0x6];
8480 
8481         u8         clr[0x1];
8482         u8         reserved_at_21[0x1f];
8483 
8484         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8485 };
8486 
8487 struct mlx5_ifc_ppad_reg_bits {
8488         u8         reserved_at_0[0x3];
8489         u8         single_mac[0x1];
8490         u8         reserved_at_4[0x4];
8491         u8         local_port[0x8];
8492         u8         mac_47_32[0x10];
8493 
8494         u8         mac_31_0[0x20];
8495 
8496         u8         reserved_at_40[0x40];
8497 };
8498 
8499 struct mlx5_ifc_pmtu_reg_bits {
8500         u8         reserved_at_0[0x8];
8501         u8         local_port[0x8];
8502         u8         reserved_at_10[0x10];
8503 
8504         u8         max_mtu[0x10];
8505         u8         reserved_at_30[0x10];
8506 
8507         u8         admin_mtu[0x10];
8508         u8         reserved_at_50[0x10];
8509 
8510         u8         oper_mtu[0x10];
8511         u8         reserved_at_70[0x10];
8512 };
8513 
8514 struct mlx5_ifc_pmpr_reg_bits {
8515         u8         reserved_at_0[0x8];
8516         u8         module[0x8];
8517         u8         reserved_at_10[0x10];
8518 
8519         u8         reserved_at_20[0x18];
8520         u8         attenuation_5g[0x8];
8521 
8522         u8         reserved_at_40[0x18];
8523         u8         attenuation_7g[0x8];
8524 
8525         u8         reserved_at_60[0x18];
8526         u8         attenuation_12g[0x8];
8527 };
8528 
8529 struct mlx5_ifc_pmpe_reg_bits {
8530         u8         reserved_at_0[0x8];
8531         u8         module[0x8];
8532         u8         reserved_at_10[0xc];
8533         u8         module_status[0x4];
8534 
8535         u8         reserved_at_20[0x60];
8536 };
8537 
8538 struct mlx5_ifc_pmpc_reg_bits {
8539         u8         module_state_updated[32][0x8];
8540 };
8541 
8542 struct mlx5_ifc_pmlpn_reg_bits {
8543         u8         reserved_at_0[0x4];
8544         u8         mlpn_status[0x4];
8545         u8         local_port[0x8];
8546         u8         reserved_at_10[0x10];
8547 
8548         u8         e[0x1];
8549         u8         reserved_at_21[0x1f];
8550 };
8551 
8552 struct mlx5_ifc_pmlp_reg_bits {
8553         u8         rxtx[0x1];
8554         u8         reserved_at_1[0x7];
8555         u8         local_port[0x8];
8556         u8         reserved_at_10[0x8];
8557         u8         width[0x8];
8558 
8559         u8         lane0_module_mapping[0x20];
8560 
8561         u8         lane1_module_mapping[0x20];
8562 
8563         u8         lane2_module_mapping[0x20];
8564 
8565         u8         lane3_module_mapping[0x20];
8566 
8567         u8         reserved_at_a0[0x160];
8568 };
8569 
8570 struct mlx5_ifc_pmaos_reg_bits {
8571         u8         reserved_at_0[0x8];
8572         u8         module[0x8];
8573         u8         reserved_at_10[0x4];
8574         u8         admin_status[0x4];
8575         u8         reserved_at_18[0x4];
8576         u8         oper_status[0x4];
8577 
8578         u8         ase[0x1];
8579         u8         ee[0x1];
8580         u8         reserved_at_22[0x1c];
8581         u8         e[0x2];
8582 
8583         u8         reserved_at_40[0x40];
8584 };
8585 
8586 struct mlx5_ifc_plpc_reg_bits {
8587         u8         reserved_at_0[0x4];
8588         u8         profile_id[0xc];
8589         u8         reserved_at_10[0x4];
8590         u8         proto_mask[0x4];
8591         u8         reserved_at_18[0x8];
8592 
8593         u8         reserved_at_20[0x10];
8594         u8         lane_speed[0x10];
8595 
8596         u8         reserved_at_40[0x17];
8597         u8         lpbf[0x1];
8598         u8         fec_mode_policy[0x8];
8599 
8600         u8         retransmission_capability[0x8];
8601         u8         fec_mode_capability[0x18];
8602 
8603         u8         retransmission_support_admin[0x8];
8604         u8         fec_mode_support_admin[0x18];
8605 
8606         u8         retransmission_request_admin[0x8];
8607         u8         fec_mode_request_admin[0x18];
8608 
8609         u8         reserved_at_c0[0x80];
8610 };
8611 
8612 struct mlx5_ifc_plib_reg_bits {
8613         u8         reserved_at_0[0x8];
8614         u8         local_port[0x8];
8615         u8         reserved_at_10[0x8];
8616         u8         ib_port[0x8];
8617 
8618         u8         reserved_at_20[0x60];
8619 };
8620 
8621 struct mlx5_ifc_plbf_reg_bits {
8622         u8         reserved_at_0[0x8];
8623         u8         local_port[0x8];
8624         u8         reserved_at_10[0xd];
8625         u8         lbf_mode[0x3];
8626 
8627         u8         reserved_at_20[0x20];
8628 };
8629 
8630 struct mlx5_ifc_pipg_reg_bits {
8631         u8         reserved_at_0[0x8];
8632         u8         local_port[0x8];
8633         u8         reserved_at_10[0x10];
8634 
8635         u8         dic[0x1];
8636         u8         reserved_at_21[0x19];
8637         u8         ipg[0x4];
8638         u8         reserved_at_3e[0x2];
8639 };
8640 
8641 struct mlx5_ifc_pifr_reg_bits {
8642         u8         reserved_at_0[0x8];
8643         u8         local_port[0x8];
8644         u8         reserved_at_10[0x10];
8645 
8646         u8         reserved_at_20[0xe0];
8647 
8648         u8         port_filter[8][0x20];
8649 
8650         u8         port_filter_update_en[8][0x20];
8651 };
8652 
8653 struct mlx5_ifc_pfcc_reg_bits {
8654         u8         reserved_at_0[0x8];
8655         u8         local_port[0x8];
8656         u8         reserved_at_10[0xb];
8657         u8         ppan_mask_n[0x1];
8658         u8         minor_stall_mask[0x1];
8659         u8         critical_stall_mask[0x1];
8660         u8         reserved_at_1e[0x2];
8661 
8662         u8         ppan[0x4];
8663         u8         reserved_at_24[0x4];
8664         u8         prio_mask_tx[0x8];
8665         u8         reserved_at_30[0x8];
8666         u8         prio_mask_rx[0x8];
8667 
8668         u8         pptx[0x1];
8669         u8         aptx[0x1];
8670         u8         pptx_mask_n[0x1];
8671         u8         reserved_at_43[0x5];
8672         u8         pfctx[0x8];
8673         u8         reserved_at_50[0x10];
8674 
8675         u8         pprx[0x1];
8676         u8         aprx[0x1];
8677         u8         pprx_mask_n[0x1];
8678         u8         reserved_at_63[0x5];
8679         u8         pfcrx[0x8];
8680         u8         reserved_at_70[0x10];
8681 
8682         u8         device_stall_minor_watermark[0x10];
8683         u8         device_stall_critical_watermark[0x10];
8684 
8685         u8         reserved_at_a0[0x60];
8686 };
8687 
8688 struct mlx5_ifc_pelc_reg_bits {
8689         u8         op[0x4];
8690         u8         reserved_at_4[0x4];
8691         u8         local_port[0x8];
8692         u8         reserved_at_10[0x10];
8693 
8694         u8         op_admin[0x8];
8695         u8         op_capability[0x8];
8696         u8         op_request[0x8];
8697         u8         op_active[0x8];
8698 
8699         u8         admin[0x40];
8700 
8701         u8         capability[0x40];
8702 
8703         u8         request[0x40];
8704 
8705         u8         active[0x40];
8706 
8707         u8         reserved_at_140[0x80];
8708 };
8709 
8710 struct mlx5_ifc_peir_reg_bits {
8711         u8         reserved_at_0[0x8];
8712         u8         local_port[0x8];
8713         u8         reserved_at_10[0x10];
8714 
8715         u8         reserved_at_20[0xc];
8716         u8         error_count[0x4];
8717         u8         reserved_at_30[0x10];
8718 
8719         u8         reserved_at_40[0xc];
8720         u8         lane[0x4];
8721         u8         reserved_at_50[0x8];
8722         u8         error_type[0x8];
8723 };
8724 
8725 struct mlx5_ifc_mpegc_reg_bits {
8726         u8         reserved_at_0[0x30];
8727         u8         field_select[0x10];
8728 
8729         u8         tx_overflow_sense[0x1];
8730         u8         mark_cqe[0x1];
8731         u8         mark_cnp[0x1];
8732         u8         reserved_at_43[0x1b];
8733         u8         tx_lossy_overflow_oper[0x2];
8734 
8735         u8         reserved_at_60[0x100];
8736 };
8737 
8738 struct mlx5_ifc_pcam_enhanced_features_bits {
8739         u8         reserved_at_0[0x6d];
8740         u8         rx_icrc_encapsulated_counter[0x1];
8741         u8         reserved_at_6e[0x4];
8742         u8         ptys_extended_ethernet[0x1];
8743         u8         reserved_at_73[0x3];
8744         u8         pfcc_mask[0x1];
8745         u8         reserved_at_77[0x3];
8746         u8         per_lane_error_counters[0x1];
8747         u8         rx_buffer_fullness_counters[0x1];
8748         u8         ptys_connector_type[0x1];
8749         u8         reserved_at_7d[0x1];
8750         u8         ppcnt_discard_group[0x1];
8751         u8         ppcnt_statistical_group[0x1];
8752 };
8753 
8754 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8755         u8         port_access_reg_cap_mask_127_to_96[0x20];
8756         u8         port_access_reg_cap_mask_95_to_64[0x20];
8757 
8758         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8759         u8         pplm[0x1];
8760         u8         port_access_reg_cap_mask_34_to_32[0x3];
8761 
8762         u8         port_access_reg_cap_mask_31_to_13[0x13];
8763         u8         pbmc[0x1];
8764         u8         pptb[0x1];
8765         u8         port_access_reg_cap_mask_10_to_09[0x2];
8766         u8         ppcnt[0x1];
8767         u8         port_access_reg_cap_mask_07_to_00[0x8];
8768 };
8769 
8770 struct mlx5_ifc_pcam_reg_bits {
8771         u8         reserved_at_0[0x8];
8772         u8         feature_group[0x8];
8773         u8         reserved_at_10[0x8];
8774         u8         access_reg_group[0x8];
8775 
8776         u8         reserved_at_20[0x20];
8777 
8778         union {
8779                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8780                 u8         reserved_at_0[0x80];
8781         } port_access_reg_cap_mask;
8782 
8783         u8         reserved_at_c0[0x80];
8784 
8785         union {
8786                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8787                 u8         reserved_at_0[0x80];
8788         } feature_cap_mask;
8789 
8790         u8         reserved_at_1c0[0xc0];
8791 };
8792 
8793 struct mlx5_ifc_mcam_enhanced_features_bits {
8794         u8         reserved_at_0[0x6e];
8795         u8         pci_status_and_power[0x1];
8796         u8         reserved_at_6f[0x5];
8797         u8         mark_tx_action_cnp[0x1];
8798         u8         mark_tx_action_cqe[0x1];
8799         u8         dynamic_tx_overflow[0x1];
8800         u8         reserved_at_77[0x4];
8801         u8         pcie_outbound_stalled[0x1];
8802         u8         tx_overflow_buffer_pkt[0x1];
8803         u8         mtpps_enh_out_per_adj[0x1];
8804         u8         mtpps_fs[0x1];
8805         u8         pcie_performance_group[0x1];
8806 };
8807 
8808 struct mlx5_ifc_mcam_access_reg_bits {
8809         u8         reserved_at_0[0x1c];
8810         u8         mcda[0x1];
8811         u8         mcc[0x1];
8812         u8         mcqi[0x1];
8813         u8         mcqs[0x1];
8814 
8815         u8         regs_95_to_87[0x9];
8816         u8         mpegc[0x1];
8817         u8         regs_85_to_68[0x12];
8818         u8         tracer_registers[0x4];
8819 
8820         u8         regs_63_to_32[0x20];
8821         u8         regs_31_to_0[0x20];
8822 };
8823 
8824 struct mlx5_ifc_mcam_reg_bits {
8825         u8         reserved_at_0[0x8];
8826         u8         feature_group[0x8];
8827         u8         reserved_at_10[0x8];
8828         u8         access_reg_group[0x8];
8829 
8830         u8         reserved_at_20[0x20];
8831 
8832         union {
8833                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8834                 u8         reserved_at_0[0x80];
8835         } mng_access_reg_cap_mask;
8836 
8837         u8         reserved_at_c0[0x80];
8838 
8839         union {
8840                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8841                 u8         reserved_at_0[0x80];
8842         } mng_feature_cap_mask;
8843 
8844         u8         reserved_at_1c0[0x80];
8845 };
8846 
8847 struct mlx5_ifc_qcam_access_reg_cap_mask {
8848         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8849         u8         qpdpm[0x1];
8850         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8851         u8         qdpm[0x1];
8852         u8         qpts[0x1];
8853         u8         qcap[0x1];
8854         u8         qcam_access_reg_cap_mask_0[0x1];
8855 };
8856 
8857 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8858         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8859         u8         qpts_trust_both[0x1];
8860 };
8861 
8862 struct mlx5_ifc_qcam_reg_bits {
8863         u8         reserved_at_0[0x8];
8864         u8         feature_group[0x8];
8865         u8         reserved_at_10[0x8];
8866         u8         access_reg_group[0x8];
8867         u8         reserved_at_20[0x20];
8868 
8869         union {
8870                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8871                 u8  reserved_at_0[0x80];
8872         } qos_access_reg_cap_mask;
8873 
8874         u8         reserved_at_c0[0x80];
8875 
8876         union {
8877                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8878                 u8  reserved_at_0[0x80];
8879         } qos_feature_cap_mask;
8880 
8881         u8         reserved_at_1c0[0x80];
8882 };
8883 
8884 struct mlx5_ifc_core_dump_reg_bits {
8885         u8         reserved_at_0[0x18];
8886         u8         core_dump_type[0x8];
8887 
8888         u8         reserved_at_20[0x30];
8889         u8         vhca_id[0x10];
8890 
8891         u8         reserved_at_60[0x8];
8892         u8         qpn[0x18];
8893         u8         reserved_at_80[0x180];
8894 };
8895 
8896 struct mlx5_ifc_pcap_reg_bits {
8897         u8         reserved_at_0[0x8];
8898         u8         local_port[0x8];
8899         u8         reserved_at_10[0x10];
8900 
8901         u8         port_capability_mask[4][0x20];
8902 };
8903 
8904 struct mlx5_ifc_paos_reg_bits {
8905         u8         swid[0x8];
8906         u8         local_port[0x8];
8907         u8         reserved_at_10[0x4];
8908         u8         admin_status[0x4];
8909         u8         reserved_at_18[0x4];
8910         u8         oper_status[0x4];
8911 
8912         u8         ase[0x1];
8913         u8         ee[0x1];
8914         u8         reserved_at_22[0x1c];
8915         u8         e[0x2];
8916 
8917         u8         reserved_at_40[0x40];
8918 };
8919 
8920 struct mlx5_ifc_pamp_reg_bits {
8921         u8         reserved_at_0[0x8];
8922         u8         opamp_group[0x8];
8923         u8         reserved_at_10[0xc];
8924         u8         opamp_group_type[0x4];
8925 
8926         u8         start_index[0x10];
8927         u8         reserved_at_30[0x4];
8928         u8         num_of_indices[0xc];
8929 
8930         u8         index_data[18][0x10];
8931 };
8932 
8933 struct mlx5_ifc_pcmr_reg_bits {
8934         u8         reserved_at_0[0x8];
8935         u8         local_port[0x8];
8936         u8         reserved_at_10[0x10];
8937         u8         entropy_force_cap[0x1];
8938         u8         entropy_calc_cap[0x1];
8939         u8         entropy_gre_calc_cap[0x1];
8940         u8         reserved_at_23[0x1b];
8941         u8         fcs_cap[0x1];
8942         u8         reserved_at_3f[0x1];
8943         u8         entropy_force[0x1];
8944         u8         entropy_calc[0x1];
8945         u8         entropy_gre_calc[0x1];
8946         u8         reserved_at_43[0x1b];
8947         u8         fcs_chk[0x1];
8948         u8         reserved_at_5f[0x1];
8949 };
8950 
8951 struct mlx5_ifc_lane_2_module_mapping_bits {
8952         u8         reserved_at_0[0x6];
8953         u8         rx_lane[0x2];
8954         u8         reserved_at_8[0x6];
8955         u8         tx_lane[0x2];
8956         u8         reserved_at_10[0x8];
8957         u8         module[0x8];
8958 };
8959 
8960 struct mlx5_ifc_bufferx_reg_bits {
8961         u8         reserved_at_0[0x6];
8962         u8         lossy[0x1];
8963         u8         epsb[0x1];
8964         u8         reserved_at_8[0xc];
8965         u8         size[0xc];
8966 
8967         u8         xoff_threshold[0x10];
8968         u8         xon_threshold[0x10];
8969 };
8970 
8971 struct mlx5_ifc_set_node_in_bits {
8972         u8         node_description[64][0x8];
8973 };
8974 
8975 struct mlx5_ifc_register_power_settings_bits {
8976         u8         reserved_at_0[0x18];
8977         u8         power_settings_level[0x8];
8978 
8979         u8         reserved_at_20[0x60];
8980 };
8981 
8982 struct mlx5_ifc_register_host_endianness_bits {
8983         u8         he[0x1];
8984         u8         reserved_at_1[0x1f];
8985 
8986         u8         reserved_at_20[0x60];
8987 };
8988 
8989 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8990         u8         reserved_at_0[0x20];
8991 
8992         u8         mkey[0x20];
8993 
8994         u8         addressh_63_32[0x20];
8995 
8996         u8         addressl_31_0[0x20];
8997 };
8998 
8999 struct mlx5_ifc_ud_adrs_vector_bits {
9000         u8         dc_key[0x40];
9001 
9002         u8         ext[0x1];
9003         u8         reserved_at_41[0x7];
9004         u8         destination_qp_dct[0x18];
9005 
9006         u8         static_rate[0x4];
9007         u8         sl_eth_prio[0x4];
9008         u8         fl[0x1];
9009         u8         mlid[0x7];
9010         u8         rlid_udp_sport[0x10];
9011 
9012         u8         reserved_at_80[0x20];
9013 
9014         u8         rmac_47_16[0x20];
9015 
9016         u8         rmac_15_0[0x10];
9017         u8         tclass[0x8];
9018         u8         hop_limit[0x8];
9019 
9020         u8         reserved_at_e0[0x1];
9021         u8         grh[0x1];
9022         u8         reserved_at_e2[0x2];
9023         u8         src_addr_index[0x8];
9024         u8         flow_label[0x14];
9025 
9026         u8         rgid_rip[16][0x8];
9027 };
9028 
9029 struct mlx5_ifc_pages_req_event_bits {
9030         u8         reserved_at_0[0x10];
9031         u8         function_id[0x10];
9032 
9033         u8         num_pages[0x20];
9034 
9035         u8         reserved_at_40[0xa0];
9036 };
9037 
9038 struct mlx5_ifc_eqe_bits {
9039         u8         reserved_at_0[0x8];
9040         u8         event_type[0x8];
9041         u8         reserved_at_10[0x8];
9042         u8         event_sub_type[0x8];
9043 
9044         u8         reserved_at_20[0xe0];
9045 
9046         union mlx5_ifc_event_auto_bits event_data;
9047 
9048         u8         reserved_at_1e0[0x10];
9049         u8         signature[0x8];
9050         u8         reserved_at_1f8[0x7];
9051         u8         owner[0x1];
9052 };
9053 
9054 enum {
9055         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9056 };
9057 
9058 struct mlx5_ifc_cmd_queue_entry_bits {
9059         u8         type[0x8];
9060         u8         reserved_at_8[0x18];
9061 
9062         u8         input_length[0x20];
9063 
9064         u8         input_mailbox_pointer_63_32[0x20];
9065 
9066         u8         input_mailbox_pointer_31_9[0x17];
9067         u8         reserved_at_77[0x9];
9068 
9069         u8         command_input_inline_data[16][0x8];
9070 
9071         u8         command_output_inline_data[16][0x8];
9072 
9073         u8         output_mailbox_pointer_63_32[0x20];
9074 
9075         u8         output_mailbox_pointer_31_9[0x17];
9076         u8         reserved_at_1b7[0x9];
9077 
9078         u8         output_length[0x20];
9079 
9080         u8         token[0x8];
9081         u8         signature[0x8];
9082         u8         reserved_at_1f0[0x8];
9083         u8         status[0x7];
9084         u8         ownership[0x1];
9085 };
9086 
9087 struct mlx5_ifc_cmd_out_bits {
9088         u8         status[0x8];
9089         u8         reserved_at_8[0x18];
9090 
9091         u8         syndrome[0x20];
9092 
9093         u8         command_output[0x20];
9094 };
9095 
9096 struct mlx5_ifc_cmd_in_bits {
9097         u8         opcode[0x10];
9098         u8         reserved_at_10[0x10];
9099 
9100         u8         reserved_at_20[0x10];
9101         u8         op_mod[0x10];
9102 
9103         u8         command[0][0x20];
9104 };
9105 
9106 struct mlx5_ifc_cmd_if_box_bits {
9107         u8         mailbox_data[512][0x8];
9108 
9109         u8         reserved_at_1000[0x180];
9110 
9111         u8         next_pointer_63_32[0x20];
9112 
9113         u8         next_pointer_31_10[0x16];
9114         u8         reserved_at_11b6[0xa];
9115 
9116         u8         block_number[0x20];
9117 
9118         u8         reserved_at_11e0[0x8];
9119         u8         token[0x8];
9120         u8         ctrl_signature[0x8];
9121         u8         signature[0x8];
9122 };
9123 
9124 struct mlx5_ifc_mtt_bits {
9125         u8         ptag_63_32[0x20];
9126 
9127         u8         ptag_31_8[0x18];
9128         u8         reserved_at_38[0x6];
9129         u8         wr_en[0x1];
9130         u8         rd_en[0x1];
9131 };
9132 
9133 struct mlx5_ifc_query_wol_rol_out_bits {
9134         u8         status[0x8];
9135         u8         reserved_at_8[0x18];
9136 
9137         u8         syndrome[0x20];
9138 
9139         u8         reserved_at_40[0x10];
9140         u8         rol_mode[0x8];
9141         u8         wol_mode[0x8];
9142 
9143         u8         reserved_at_60[0x20];
9144 };
9145 
9146 struct mlx5_ifc_query_wol_rol_in_bits {
9147         u8         opcode[0x10];
9148         u8         reserved_at_10[0x10];
9149 
9150         u8         reserved_at_20[0x10];
9151         u8         op_mod[0x10];
9152 
9153         u8         reserved_at_40[0x40];
9154 };
9155 
9156 struct mlx5_ifc_set_wol_rol_out_bits {
9157         u8         status[0x8];
9158         u8         reserved_at_8[0x18];
9159 
9160         u8         syndrome[0x20];
9161 
9162         u8         reserved_at_40[0x40];
9163 };
9164 
9165 struct mlx5_ifc_set_wol_rol_in_bits {
9166         u8         opcode[0x10];
9167         u8         reserved_at_10[0x10];
9168 
9169         u8         reserved_at_20[0x10];
9170         u8         op_mod[0x10];
9171 
9172         u8         rol_mode_valid[0x1];
9173         u8         wol_mode_valid[0x1];
9174         u8         reserved_at_42[0xe];
9175         u8         rol_mode[0x8];
9176         u8         wol_mode[0x8];
9177 
9178         u8         reserved_at_60[0x20];
9179 };
9180 
9181 enum {
9182         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9183         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9184         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9185 };
9186 
9187 enum {
9188         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9189         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9190         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9191 };
9192 
9193 enum {
9194         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9195         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9196         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9197         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9198         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9199         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9200         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9201         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9202         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9203         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9204         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9205 };
9206 
9207 struct mlx5_ifc_initial_seg_bits {
9208         u8         fw_rev_minor[0x10];
9209         u8         fw_rev_major[0x10];
9210 
9211         u8         cmd_interface_rev[0x10];
9212         u8         fw_rev_subminor[0x10];
9213 
9214         u8         reserved_at_40[0x40];
9215 
9216         u8         cmdq_phy_addr_63_32[0x20];
9217 
9218         u8         cmdq_phy_addr_31_12[0x14];
9219         u8         reserved_at_b4[0x2];
9220         u8         nic_interface[0x2];
9221         u8         log_cmdq_size[0x4];
9222         u8         log_cmdq_stride[0x4];
9223 
9224         u8         command_doorbell_vector[0x20];
9225 
9226         u8         reserved_at_e0[0xf00];
9227 
9228         u8         initializing[0x1];
9229         u8         reserved_at_fe1[0x4];
9230         u8         nic_interface_supported[0x3];
9231         u8         embedded_cpu[0x1];
9232         u8         reserved_at_fe9[0x17];
9233 
9234         struct mlx5_ifc_health_buffer_bits health_buffer;
9235 
9236         u8         no_dram_nic_offset[0x20];
9237 
9238         u8         reserved_at_1220[0x6e40];
9239 
9240         u8         reserved_at_8060[0x1f];
9241         u8         clear_int[0x1];
9242 
9243         u8         health_syndrome[0x8];
9244         u8         health_counter[0x18];
9245 
9246         u8         reserved_at_80a0[0x17fc0];
9247 };
9248 
9249 struct mlx5_ifc_mtpps_reg_bits {
9250         u8         reserved_at_0[0xc];
9251         u8         cap_number_of_pps_pins[0x4];
9252         u8         reserved_at_10[0x4];
9253         u8         cap_max_num_of_pps_in_pins[0x4];
9254         u8         reserved_at_18[0x4];
9255         u8         cap_max_num_of_pps_out_pins[0x4];
9256 
9257         u8         reserved_at_20[0x24];
9258         u8         cap_pin_3_mode[0x4];
9259         u8         reserved_at_48[0x4];
9260         u8         cap_pin_2_mode[0x4];
9261         u8         reserved_at_50[0x4];
9262         u8         cap_pin_1_mode[0x4];
9263         u8         reserved_at_58[0x4];
9264         u8         cap_pin_0_mode[0x4];
9265 
9266         u8         reserved_at_60[0x4];
9267         u8         cap_pin_7_mode[0x4];
9268         u8         reserved_at_68[0x4];
9269         u8         cap_pin_6_mode[0x4];
9270         u8         reserved_at_70[0x4];
9271         u8         cap_pin_5_mode[0x4];
9272         u8         reserved_at_78[0x4];
9273         u8         cap_pin_4_mode[0x4];
9274 
9275         u8         field_select[0x20];
9276         u8         reserved_at_a0[0x60];
9277 
9278         u8         enable[0x1];
9279         u8         reserved_at_101[0xb];
9280         u8         pattern[0x4];
9281         u8         reserved_at_110[0x4];
9282         u8         pin_mode[0x4];
9283         u8         pin[0x8];
9284 
9285         u8         reserved_at_120[0x20];
9286 
9287         u8         time_stamp[0x40];
9288 
9289         u8         out_pulse_duration[0x10];
9290         u8         out_periodic_adjustment[0x10];
9291         u8         enhanced_out_periodic_adjustment[0x20];
9292 
9293         u8         reserved_at_1c0[0x20];
9294 };
9295 
9296 struct mlx5_ifc_mtppse_reg_bits {
9297         u8         reserved_at_0[0x18];
9298         u8         pin[0x8];
9299         u8         event_arm[0x1];
9300         u8         reserved_at_21[0x1b];
9301         u8         event_generation_mode[0x4];
9302         u8         reserved_at_40[0x40];
9303 };
9304 
9305 struct mlx5_ifc_mcqs_reg_bits {
9306         u8         last_index_flag[0x1];
9307         u8         reserved_at_1[0x7];
9308         u8         fw_device[0x8];
9309         u8         component_index[0x10];
9310 
9311         u8         reserved_at_20[0x10];
9312         u8         identifier[0x10];
9313 
9314         u8         reserved_at_40[0x17];
9315         u8         component_status[0x5];
9316         u8         component_update_state[0x4];
9317 
9318         u8         last_update_state_changer_type[0x4];
9319         u8         last_update_state_changer_host_id[0x4];
9320         u8         reserved_at_68[0x18];
9321 };
9322 
9323 struct mlx5_ifc_mcqi_cap_bits {
9324         u8         supported_info_bitmask[0x20];
9325 
9326         u8         component_size[0x20];
9327 
9328         u8         max_component_size[0x20];
9329 
9330         u8         log_mcda_word_size[0x4];
9331         u8         reserved_at_64[0xc];
9332         u8         mcda_max_write_size[0x10];
9333 
9334         u8         rd_en[0x1];
9335         u8         reserved_at_81[0x1];
9336         u8         match_chip_id[0x1];
9337         u8         match_psid[0x1];
9338         u8         check_user_timestamp[0x1];
9339         u8         match_base_guid_mac[0x1];
9340         u8         reserved_at_86[0x1a];
9341 };
9342 
9343 struct mlx5_ifc_mcqi_version_bits {
9344         u8         reserved_at_0[0x2];
9345         u8         build_time_valid[0x1];
9346         u8         user_defined_time_valid[0x1];
9347         u8         reserved_at_4[0x14];
9348         u8         version_string_length[0x8];
9349 
9350         u8         version[0x20];
9351 
9352         u8         build_time[0x40];
9353 
9354         u8         user_defined_time[0x40];
9355 
9356         u8         build_tool_version[0x20];
9357 
9358         u8         reserved_at_e0[0x20];
9359 
9360         u8         version_string[92][0x8];
9361 };
9362 
9363 struct mlx5_ifc_mcqi_activation_method_bits {
9364         u8         pending_server_ac_power_cycle[0x1];
9365         u8         pending_server_dc_power_cycle[0x1];
9366         u8         pending_server_reboot[0x1];
9367         u8         pending_fw_reset[0x1];
9368         u8         auto_activate[0x1];
9369         u8         all_hosts_sync[0x1];
9370         u8         device_hw_reset[0x1];
9371         u8         reserved_at_7[0x19];
9372 };
9373 
9374 union mlx5_ifc_mcqi_reg_data_bits {
9375         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9376         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9377         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9378 };
9379 
9380 struct mlx5_ifc_mcqi_reg_bits {
9381         u8         read_pending_component[0x1];
9382         u8         reserved_at_1[0xf];
9383         u8         component_index[0x10];
9384 
9385         u8         reserved_at_20[0x20];
9386 
9387         u8         reserved_at_40[0x1b];
9388         u8         info_type[0x5];
9389 
9390         u8         info_size[0x20];
9391 
9392         u8         offset[0x20];
9393 
9394         u8         reserved_at_a0[0x10];
9395         u8         data_size[0x10];
9396 
9397         union mlx5_ifc_mcqi_reg_data_bits data[0];
9398 };
9399 
9400 struct mlx5_ifc_mcc_reg_bits {
9401         u8         reserved_at_0[0x4];
9402         u8         time_elapsed_since_last_cmd[0xc];
9403         u8         reserved_at_10[0x8];
9404         u8         instruction[0x8];
9405 
9406         u8         reserved_at_20[0x10];
9407         u8         component_index[0x10];
9408 
9409         u8         reserved_at_40[0x8];
9410         u8         update_handle[0x18];
9411 
9412         u8         handle_owner_type[0x4];
9413         u8         handle_owner_host_id[0x4];
9414         u8         reserved_at_68[0x1];
9415         u8         control_progress[0x7];
9416         u8         error_code[0x8];
9417         u8         reserved_at_78[0x4];
9418         u8         control_state[0x4];
9419 
9420         u8         component_size[0x20];
9421 
9422         u8         reserved_at_a0[0x60];
9423 };
9424 
9425 struct mlx5_ifc_mcda_reg_bits {
9426         u8         reserved_at_0[0x8];
9427         u8         update_handle[0x18];
9428 
9429         u8         offset[0x20];
9430 
9431         u8         reserved_at_40[0x10];
9432         u8         size[0x10];
9433 
9434         u8         reserved_at_60[0x20];
9435 
9436         u8         data[0][0x20];
9437 };
9438 
9439 union mlx5_ifc_ports_control_registers_document_bits {
9440         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9441         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9442         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9443         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9444         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9445         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9446         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9447         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9448         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9449         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9450         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9451         struct mlx5_ifc_paos_reg_bits paos_reg;
9452         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9453         struct mlx5_ifc_peir_reg_bits peir_reg;
9454         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9455         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9456         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9457         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9458         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9459         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9460         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9461         struct mlx5_ifc_plib_reg_bits plib_reg;
9462         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9463         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9464         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9465         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9466         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9467         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9468         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9469         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9470         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9471         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9472         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9473         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9474         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9475         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9476         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9477         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9478         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9479         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9480         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9481         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9482         struct mlx5_ifc_pude_reg_bits pude_reg;
9483         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9484         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9485         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9486         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9487         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9488         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9489         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9490         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9491         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9492         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9493         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9494         u8         reserved_at_0[0x60e0];
9495 };
9496 
9497 union mlx5_ifc_debug_enhancements_document_bits {
9498         struct mlx5_ifc_health_buffer_bits health_buffer;
9499         u8         reserved_at_0[0x200];
9500 };
9501 
9502 union mlx5_ifc_uplink_pci_interface_document_bits {
9503         struct mlx5_ifc_initial_seg_bits initial_seg;
9504         u8         reserved_at_0[0x20060];
9505 };
9506 
9507 struct mlx5_ifc_set_flow_table_root_out_bits {
9508         u8         status[0x8];
9509         u8         reserved_at_8[0x18];
9510 
9511         u8         syndrome[0x20];
9512 
9513         u8         reserved_at_40[0x40];
9514 };
9515 
9516 struct mlx5_ifc_set_flow_table_root_in_bits {
9517         u8         opcode[0x10];
9518         u8         reserved_at_10[0x10];
9519 
9520         u8         reserved_at_20[0x10];
9521         u8         op_mod[0x10];
9522 
9523         u8         other_vport[0x1];
9524         u8         reserved_at_41[0xf];
9525         u8         vport_number[0x10];
9526 
9527         u8         reserved_at_60[0x20];
9528 
9529         u8         table_type[0x8];
9530         u8         reserved_at_88[0x18];
9531 
9532         u8         reserved_at_a0[0x8];
9533         u8         table_id[0x18];
9534 
9535         u8         reserved_at_c0[0x8];
9536         u8         underlay_qpn[0x18];
9537         u8         reserved_at_e0[0x120];
9538 };
9539 
9540 enum {
9541         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9542         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9543 };
9544 
9545 struct mlx5_ifc_modify_flow_table_out_bits {
9546         u8         status[0x8];
9547         u8         reserved_at_8[0x18];
9548 
9549         u8         syndrome[0x20];
9550 
9551         u8         reserved_at_40[0x40];
9552 };
9553 
9554 struct mlx5_ifc_modify_flow_table_in_bits {
9555         u8         opcode[0x10];
9556         u8         reserved_at_10[0x10];
9557 
9558         u8         reserved_at_20[0x10];
9559         u8         op_mod[0x10];
9560 
9561         u8         other_vport[0x1];
9562         u8         reserved_at_41[0xf];
9563         u8         vport_number[0x10];
9564 
9565         u8         reserved_at_60[0x10];
9566         u8         modify_field_select[0x10];
9567 
9568         u8         table_type[0x8];
9569         u8         reserved_at_88[0x18];
9570 
9571         u8         reserved_at_a0[0x8];
9572         u8         table_id[0x18];
9573 
9574         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9575 };
9576 
9577 struct mlx5_ifc_ets_tcn_config_reg_bits {
9578         u8         g[0x1];
9579         u8         b[0x1];
9580         u8         r[0x1];
9581         u8         reserved_at_3[0x9];
9582         u8         group[0x4];
9583         u8         reserved_at_10[0x9];
9584         u8         bw_allocation[0x7];
9585 
9586         u8         reserved_at_20[0xc];
9587         u8         max_bw_units[0x4];
9588         u8         reserved_at_30[0x8];
9589         u8         max_bw_value[0x8];
9590 };
9591 
9592 struct mlx5_ifc_ets_global_config_reg_bits {
9593         u8         reserved_at_0[0x2];
9594         u8         r[0x1];
9595         u8         reserved_at_3[0x1d];
9596 
9597         u8         reserved_at_20[0xc];
9598         u8         max_bw_units[0x4];
9599         u8         reserved_at_30[0x8];
9600         u8         max_bw_value[0x8];
9601 };
9602 
9603 struct mlx5_ifc_qetc_reg_bits {
9604         u8                                         reserved_at_0[0x8];
9605         u8                                         port_number[0x8];
9606         u8                                         reserved_at_10[0x30];
9607 
9608         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9609         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9610 };
9611 
9612 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9613         u8         e[0x1];
9614         u8         reserved_at_01[0x0b];
9615         u8         prio[0x04];
9616 };
9617 
9618 struct mlx5_ifc_qpdpm_reg_bits {
9619         u8                                     reserved_at_0[0x8];
9620         u8                                     local_port[0x8];
9621         u8                                     reserved_at_10[0x10];
9622         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9623 };
9624 
9625 struct mlx5_ifc_qpts_reg_bits {
9626         u8         reserved_at_0[0x8];
9627         u8         local_port[0x8];
9628         u8         reserved_at_10[0x2d];
9629         u8         trust_state[0x3];
9630 };
9631 
9632 struct mlx5_ifc_pptb_reg_bits {
9633         u8         reserved_at_0[0x2];
9634         u8         mm[0x2];
9635         u8         reserved_at_4[0x4];
9636         u8         local_port[0x8];
9637         u8         reserved_at_10[0x6];
9638         u8         cm[0x1];
9639         u8         um[0x1];
9640         u8         pm[0x8];
9641 
9642         u8         prio_x_buff[0x20];
9643 
9644         u8         pm_msb[0x8];
9645         u8         reserved_at_48[0x10];
9646         u8         ctrl_buff[0x4];
9647         u8         untagged_buff[0x4];
9648 };
9649 
9650 struct mlx5_ifc_pbmc_reg_bits {
9651         u8         reserved_at_0[0x8];
9652         u8         local_port[0x8];
9653         u8         reserved_at_10[0x10];
9654 
9655         u8         xoff_timer_value[0x10];
9656         u8         xoff_refresh[0x10];
9657 
9658         u8         reserved_at_40[0x9];
9659         u8         fullness_threshold[0x7];
9660         u8         port_buffer_size[0x10];
9661 
9662         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9663 
9664         u8         reserved_at_2e0[0x40];
9665 };
9666 
9667 struct mlx5_ifc_qtct_reg_bits {
9668         u8         reserved_at_0[0x8];
9669         u8         port_number[0x8];
9670         u8         reserved_at_10[0xd];
9671         u8         prio[0x3];
9672 
9673         u8         reserved_at_20[0x1d];
9674         u8         tclass[0x3];
9675 };
9676 
9677 struct mlx5_ifc_mcia_reg_bits {
9678         u8         l[0x1];
9679         u8         reserved_at_1[0x7];
9680         u8         module[0x8];
9681         u8         reserved_at_10[0x8];
9682         u8         status[0x8];
9683 
9684         u8         i2c_device_address[0x8];
9685         u8         page_number[0x8];
9686         u8         device_address[0x10];
9687 
9688         u8         reserved_at_40[0x10];
9689         u8         size[0x10];
9690 
9691         u8         reserved_at_60[0x20];
9692 
9693         u8         dword_0[0x20];
9694         u8         dword_1[0x20];
9695         u8         dword_2[0x20];
9696         u8         dword_3[0x20];
9697         u8         dword_4[0x20];
9698         u8         dword_5[0x20];
9699         u8         dword_6[0x20];
9700         u8         dword_7[0x20];
9701         u8         dword_8[0x20];
9702         u8         dword_9[0x20];
9703         u8         dword_10[0x20];
9704         u8         dword_11[0x20];
9705 };
9706 
9707 struct mlx5_ifc_dcbx_param_bits {
9708         u8         dcbx_cee_cap[0x1];
9709         u8         dcbx_ieee_cap[0x1];
9710         u8         dcbx_standby_cap[0x1];
9711         u8         reserved_at_3[0x5];
9712         u8         port_number[0x8];
9713         u8         reserved_at_10[0xa];
9714         u8         max_application_table_size[6];
9715         u8         reserved_at_20[0x15];
9716         u8         version_oper[0x3];
9717         u8         reserved_at_38[5];
9718         u8         version_admin[0x3];
9719         u8         willing_admin[0x1];
9720         u8         reserved_at_41[0x3];
9721         u8         pfc_cap_oper[0x4];
9722         u8         reserved_at_48[0x4];
9723         u8         pfc_cap_admin[0x4];
9724         u8         reserved_at_50[0x4];
9725         u8         num_of_tc_oper[0x4];
9726         u8         reserved_at_58[0x4];
9727         u8         num_of_tc_admin[0x4];
9728         u8         remote_willing[0x1];
9729         u8         reserved_at_61[3];
9730         u8         remote_pfc_cap[4];
9731         u8         reserved_at_68[0x14];
9732         u8         remote_num_of_tc[0x4];
9733         u8         reserved_at_80[0x18];
9734         u8         error[0x8];
9735         u8         reserved_at_a0[0x160];
9736 };
9737 
9738 struct mlx5_ifc_lagc_bits {
9739         u8         reserved_at_0[0x1d];
9740         u8         lag_state[0x3];
9741 
9742         u8         reserved_at_20[0x14];
9743         u8         tx_remap_affinity_2[0x4];
9744         u8         reserved_at_38[0x4];
9745         u8         tx_remap_affinity_1[0x4];
9746 };
9747 
9748 struct mlx5_ifc_create_lag_out_bits {
9749         u8         status[0x8];
9750         u8         reserved_at_8[0x18];
9751 
9752         u8         syndrome[0x20];
9753 
9754         u8         reserved_at_40[0x40];
9755 };
9756 
9757 struct mlx5_ifc_create_lag_in_bits {
9758         u8         opcode[0x10];
9759         u8         reserved_at_10[0x10];
9760 
9761         u8         reserved_at_20[0x10];
9762         u8         op_mod[0x10];
9763 
9764         struct mlx5_ifc_lagc_bits ctx;
9765 };
9766 
9767 struct mlx5_ifc_modify_lag_out_bits {
9768         u8         status[0x8];
9769         u8         reserved_at_8[0x18];
9770 
9771         u8         syndrome[0x20];
9772 
9773         u8         reserved_at_40[0x40];
9774 };
9775 
9776 struct mlx5_ifc_modify_lag_in_bits {
9777         u8         opcode[0x10];
9778         u8         reserved_at_10[0x10];
9779 
9780         u8         reserved_at_20[0x10];
9781         u8         op_mod[0x10];
9782 
9783         u8         reserved_at_40[0x20];
9784         u8         field_select[0x20];
9785 
9786         struct mlx5_ifc_lagc_bits ctx;
9787 };
9788 
9789 struct mlx5_ifc_query_lag_out_bits {
9790         u8         status[0x8];
9791         u8         reserved_at_8[0x18];
9792 
9793         u8         syndrome[0x20];
9794 
9795         struct mlx5_ifc_lagc_bits ctx;
9796 };
9797 
9798 struct mlx5_ifc_query_lag_in_bits {
9799         u8         opcode[0x10];
9800         u8         reserved_at_10[0x10];
9801 
9802         u8         reserved_at_20[0x10];
9803         u8         op_mod[0x10];
9804 
9805         u8         reserved_at_40[0x40];
9806 };
9807 
9808 struct mlx5_ifc_destroy_lag_out_bits {
9809         u8         status[0x8];
9810         u8         reserved_at_8[0x18];
9811 
9812         u8         syndrome[0x20];
9813 
9814         u8         reserved_at_40[0x40];
9815 };
9816 
9817 struct mlx5_ifc_destroy_lag_in_bits {
9818         u8         opcode[0x10];
9819         u8         reserved_at_10[0x10];
9820 
9821         u8         reserved_at_20[0x10];
9822         u8         op_mod[0x10];
9823 
9824         u8         reserved_at_40[0x40];
9825 };
9826 
9827 struct mlx5_ifc_create_vport_lag_out_bits {
9828         u8         status[0x8];
9829         u8         reserved_at_8[0x18];
9830 
9831         u8         syndrome[0x20];
9832 
9833         u8         reserved_at_40[0x40];
9834 };
9835 
9836 struct mlx5_ifc_create_vport_lag_in_bits {
9837         u8         opcode[0x10];
9838         u8         reserved_at_10[0x10];
9839 
9840         u8         reserved_at_20[0x10];
9841         u8         op_mod[0x10];
9842 
9843         u8         reserved_at_40[0x40];
9844 };
9845 
9846 struct mlx5_ifc_destroy_vport_lag_out_bits {
9847         u8         status[0x8];
9848         u8         reserved_at_8[0x18];
9849 
9850         u8         syndrome[0x20];
9851 
9852         u8         reserved_at_40[0x40];
9853 };
9854 
9855 struct mlx5_ifc_destroy_vport_lag_in_bits {
9856         u8         opcode[0x10];
9857         u8         reserved_at_10[0x10];
9858 
9859         u8         reserved_at_20[0x10];
9860         u8         op_mod[0x10];
9861 
9862         u8         reserved_at_40[0x40];
9863 };
9864 
9865 struct mlx5_ifc_alloc_memic_in_bits {
9866         u8         opcode[0x10];
9867         u8         reserved_at_10[0x10];
9868 
9869         u8         reserved_at_20[0x10];
9870         u8         op_mod[0x10];
9871 
9872         u8         reserved_at_30[0x20];
9873 
9874         u8         reserved_at_40[0x18];
9875         u8         log_memic_addr_alignment[0x8];
9876 
9877         u8         range_start_addr[0x40];
9878 
9879         u8         range_size[0x20];
9880 
9881         u8         memic_size[0x20];
9882 };
9883 
9884 struct mlx5_ifc_alloc_memic_out_bits {
9885         u8         status[0x8];
9886         u8         reserved_at_8[0x18];
9887 
9888         u8         syndrome[0x20];
9889 
9890         u8         memic_start_addr[0x40];
9891 };
9892 
9893 struct mlx5_ifc_dealloc_memic_in_bits {
9894         u8         opcode[0x10];
9895         u8         reserved_at_10[0x10];
9896 
9897         u8         reserved_at_20[0x10];
9898         u8         op_mod[0x10];
9899 
9900         u8         reserved_at_40[0x40];
9901 
9902         u8         memic_start_addr[0x40];
9903 
9904         u8         memic_size[0x20];
9905 
9906         u8         reserved_at_e0[0x20];
9907 };
9908 
9909 struct mlx5_ifc_dealloc_memic_out_bits {
9910         u8         status[0x8];
9911         u8         reserved_at_8[0x18];
9912 
9913         u8         syndrome[0x20];
9914 
9915         u8         reserved_at_40[0x40];
9916 };
9917 
9918 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9919         u8         opcode[0x10];
9920         u8         uid[0x10];
9921 
9922         u8         vhca_tunnel_id[0x10];
9923         u8         obj_type[0x10];
9924 
9925         u8         obj_id[0x20];
9926 
9927         u8         reserved_at_60[0x20];
9928 };
9929 
9930 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9931         u8         status[0x8];
9932         u8         reserved_at_8[0x18];
9933 
9934         u8         syndrome[0x20];
9935 
9936         u8         obj_id[0x20];
9937 
9938         u8         reserved_at_60[0x20];
9939 };
9940 
9941 struct mlx5_ifc_umem_bits {
9942         u8         reserved_at_0[0x80];
9943 
9944         u8         reserved_at_80[0x1b];
9945         u8         log_page_size[0x5];
9946 
9947         u8         page_offset[0x20];
9948 
9949         u8         num_of_mtt[0x40];
9950 
9951         struct mlx5_ifc_mtt_bits  mtt[0];
9952 };
9953 
9954 struct mlx5_ifc_uctx_bits {
9955         u8         cap[0x20];
9956 
9957         u8         reserved_at_20[0x160];
9958 };
9959 
9960 struct mlx5_ifc_sw_icm_bits {
9961         u8         modify_field_select[0x40];
9962 
9963         u8         reserved_at_40[0x18];
9964         u8         log_sw_icm_size[0x8];
9965 
9966         u8         reserved_at_60[0x20];
9967 
9968         u8         sw_icm_start_addr[0x40];
9969 
9970         u8         reserved_at_c0[0x140];
9971 };
9972 
9973 struct mlx5_ifc_geneve_tlv_option_bits {
9974         u8         modify_field_select[0x40];
9975 
9976         u8         reserved_at_40[0x18];
9977         u8         geneve_option_fte_index[0x8];
9978 
9979         u8         option_class[0x10];
9980         u8         option_type[0x8];
9981         u8         reserved_at_78[0x3];
9982         u8         option_data_length[0x5];
9983 
9984         u8         reserved_at_80[0x180];
9985 };
9986 
9987 struct mlx5_ifc_create_umem_in_bits {
9988         u8         opcode[0x10];
9989         u8         uid[0x10];
9990 
9991         u8         reserved_at_20[0x10];
9992         u8         op_mod[0x10];
9993 
9994         u8         reserved_at_40[0x40];
9995 
9996         struct mlx5_ifc_umem_bits  umem;
9997 };
9998 
9999 struct mlx5_ifc_create_uctx_in_bits {
10000         u8         opcode[0x10];
10001         u8         reserved_at_10[0x10];
10002 
10003         u8         reserved_at_20[0x10];
10004         u8         op_mod[0x10];
10005 
10006         u8         reserved_at_40[0x40];
10007 
10008         struct mlx5_ifc_uctx_bits  uctx;
10009 };
10010 
10011 struct mlx5_ifc_destroy_uctx_in_bits {
10012         u8         opcode[0x10];
10013         u8         reserved_at_10[0x10];
10014 
10015         u8         reserved_at_20[0x10];
10016         u8         op_mod[0x10];
10017 
10018         u8         reserved_at_40[0x10];
10019         u8         uid[0x10];
10020 
10021         u8         reserved_at_60[0x20];
10022 };
10023 
10024 struct mlx5_ifc_create_sw_icm_in_bits {
10025         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10026         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10027 };
10028 
10029 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10030         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10031         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10032 };
10033 
10034 struct mlx5_ifc_mtrc_string_db_param_bits {
10035         u8         string_db_base_address[0x20];
10036 
10037         u8         reserved_at_20[0x8];
10038         u8         string_db_size[0x18];
10039 };
10040 
10041 struct mlx5_ifc_mtrc_cap_bits {
10042         u8         trace_owner[0x1];
10043         u8         trace_to_memory[0x1];
10044         u8         reserved_at_2[0x4];
10045         u8         trc_ver[0x2];
10046         u8         reserved_at_8[0x14];
10047         u8         num_string_db[0x4];
10048 
10049         u8         first_string_trace[0x8];
10050         u8         num_string_trace[0x8];
10051         u8         reserved_at_30[0x28];
10052 
10053         u8         log_max_trace_buffer_size[0x8];
10054 
10055         u8         reserved_at_60[0x20];
10056 
10057         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10058 
10059         u8         reserved_at_280[0x180];
10060 };
10061 
10062 struct mlx5_ifc_mtrc_conf_bits {
10063         u8         reserved_at_0[0x1c];
10064         u8         trace_mode[0x4];
10065         u8         reserved_at_20[0x18];
10066         u8         log_trace_buffer_size[0x8];
10067         u8         trace_mkey[0x20];
10068         u8         reserved_at_60[0x3a0];
10069 };
10070 
10071 struct mlx5_ifc_mtrc_stdb_bits {
10072         u8         string_db_index[0x4];
10073         u8         reserved_at_4[0x4];
10074         u8         read_size[0x18];
10075         u8         start_offset[0x20];
10076         u8         string_db_data[0];
10077 };
10078 
10079 struct mlx5_ifc_mtrc_ctrl_bits {
10080         u8         trace_status[0x2];
10081         u8         reserved_at_2[0x2];
10082         u8         arm_event[0x1];
10083         u8         reserved_at_5[0xb];
10084         u8         modify_field_select[0x10];
10085         u8         reserved_at_20[0x2b];
10086         u8         current_timestamp52_32[0x15];
10087         u8         current_timestamp31_0[0x20];
10088         u8         reserved_at_80[0x180];
10089 };
10090 
10091 struct mlx5_ifc_host_params_context_bits {
10092         u8         host_number[0x8];
10093         u8         reserved_at_8[0x7];
10094         u8         host_pf_disabled[0x1];
10095         u8         host_num_of_vfs[0x10];
10096 
10097         u8         host_total_vfs[0x10];
10098         u8         host_pci_bus[0x10];
10099 
10100         u8         reserved_at_40[0x10];
10101         u8         host_pci_device[0x10];
10102 
10103         u8         reserved_at_60[0x10];
10104         u8         host_pci_function[0x10];
10105 
10106         u8         reserved_at_80[0x180];
10107 };
10108 
10109 struct mlx5_ifc_query_esw_functions_in_bits {
10110         u8         opcode[0x10];
10111         u8         reserved_at_10[0x10];
10112 
10113         u8         reserved_at_20[0x10];
10114         u8         op_mod[0x10];
10115 
10116         u8         reserved_at_40[0x40];
10117 };
10118 
10119 struct mlx5_ifc_query_esw_functions_out_bits {
10120         u8         status[0x8];
10121         u8         reserved_at_8[0x18];
10122 
10123         u8         syndrome[0x20];
10124 
10125         u8         reserved_at_40[0x40];
10126 
10127         struct mlx5_ifc_host_params_context_bits host_params_context;
10128 
10129         u8         reserved_at_280[0x180];
10130         u8         host_sf_enable[0][0x40];
10131 };
10132 
10133 struct mlx5_ifc_sf_partition_bits {
10134         u8         reserved_at_0[0x10];
10135         u8         log_num_sf[0x8];
10136         u8         log_sf_bar_size[0x8];
10137 };
10138 
10139 struct mlx5_ifc_query_sf_partitions_out_bits {
10140         u8         status[0x8];
10141         u8         reserved_at_8[0x18];
10142 
10143         u8         syndrome[0x20];
10144 
10145         u8         reserved_at_40[0x18];
10146         u8         num_sf_partitions[0x8];
10147 
10148         u8         reserved_at_60[0x20];
10149 
10150         struct mlx5_ifc_sf_partition_bits sf_partition[0];
10151 };
10152 
10153 struct mlx5_ifc_query_sf_partitions_in_bits {
10154         u8         opcode[0x10];
10155         u8         reserved_at_10[0x10];
10156 
10157         u8         reserved_at_20[0x10];
10158         u8         op_mod[0x10];
10159 
10160         u8         reserved_at_40[0x40];
10161 };
10162 
10163 struct mlx5_ifc_dealloc_sf_out_bits {
10164         u8         status[0x8];
10165         u8         reserved_at_8[0x18];
10166 
10167         u8         syndrome[0x20];
10168 
10169         u8         reserved_at_40[0x40];
10170 };
10171 
10172 struct mlx5_ifc_dealloc_sf_in_bits {
10173         u8         opcode[0x10];
10174         u8         reserved_at_10[0x10];
10175 
10176         u8         reserved_at_20[0x10];
10177         u8         op_mod[0x10];
10178 
10179         u8         reserved_at_40[0x10];
10180         u8         function_id[0x10];
10181 
10182         u8         reserved_at_60[0x20];
10183 };
10184 
10185 struct mlx5_ifc_alloc_sf_out_bits {
10186         u8         status[0x8];
10187         u8         reserved_at_8[0x18];
10188 
10189         u8         syndrome[0x20];
10190 
10191         u8         reserved_at_40[0x40];
10192 };
10193 
10194 struct mlx5_ifc_alloc_sf_in_bits {
10195         u8         opcode[0x10];
10196         u8         reserved_at_10[0x10];
10197 
10198         u8         reserved_at_20[0x10];
10199         u8         op_mod[0x10];
10200 
10201         u8         reserved_at_40[0x10];
10202         u8         function_id[0x10];
10203 
10204         u8         reserved_at_60[0x20];
10205 };
10206 
10207 struct mlx5_ifc_affiliated_event_header_bits {
10208         u8         reserved_at_0[0x10];
10209         u8         obj_type[0x10];
10210 
10211         u8         obj_id[0x20];
10212 };
10213 
10214 enum {
10215         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10216 };
10217 
10218 enum {
10219         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10220 };
10221 
10222 struct mlx5_ifc_encryption_key_obj_bits {
10223         u8         modify_field_select[0x40];
10224 
10225         u8         reserved_at_40[0x14];
10226         u8         key_size[0x4];
10227         u8         reserved_at_58[0x4];
10228         u8         key_type[0x4];
10229 
10230         u8         reserved_at_60[0x8];
10231         u8         pd[0x18];
10232 
10233         u8         reserved_at_80[0x180];
10234         u8         key[8][0x20];
10235 
10236         u8         reserved_at_300[0x500];
10237 };
10238 
10239 struct mlx5_ifc_create_encryption_key_in_bits {
10240         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10241         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10242 };
10243 
10244 enum {
10245         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10246         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10247 };
10248 
10249 enum {
10250         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10251 };
10252 
10253 struct mlx5_ifc_tls_static_params_bits {
10254         u8         const_2[0x2];
10255         u8         tls_version[0x4];
10256         u8         const_1[0x2];
10257         u8         reserved_at_8[0x14];
10258         u8         encryption_standard[0x4];
10259 
10260         u8         reserved_at_20[0x20];
10261 
10262         u8         initial_record_number[0x40];
10263 
10264         u8         resync_tcp_sn[0x20];
10265 
10266         u8         gcm_iv[0x20];
10267 
10268         u8         implicit_iv[0x40];
10269 
10270         u8         reserved_at_100[0x8];
10271         u8         dek_index[0x18];
10272 
10273         u8         reserved_at_120[0xe0];
10274 };
10275 
10276 struct mlx5_ifc_tls_progress_params_bits {
10277         u8         reserved_at_0[0x8];
10278         u8         tisn[0x18];
10279 
10280         u8         next_record_tcp_sn[0x20];
10281 
10282         u8         hw_resync_tcp_sn[0x20];
10283 
10284         u8         record_tracker_state[0x2];
10285         u8         auth_state[0x2];
10286         u8         reserved_at_64[0x4];
10287         u8         hw_offset_record_number[0x18];
10288 };
10289 
10290 #endif /* MLX5_IFC_H */

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