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33 #ifndef __MLX5_PORT_H__
34 #define __MLX5_PORT_H__
35
36 #include <linux/mlx5/driver.h>
37
38 enum mlx5_beacon_duration {
39 MLX5_BEACON_DURATION_OFF = 0x0,
40 MLX5_BEACON_DURATION_INF = 0xffff,
41 };
42
43 enum mlx5_module_id {
44 MLX5_MODULE_ID_SFP = 0x3,
45 MLX5_MODULE_ID_QSFP = 0xC,
46 MLX5_MODULE_ID_QSFP_PLUS = 0xD,
47 MLX5_MODULE_ID_QSFP28 = 0x11,
48 };
49
50 enum mlx5_an_status {
51 MLX5_AN_UNAVAILABLE = 0,
52 MLX5_AN_COMPLETE = 1,
53 MLX5_AN_FAILED = 2,
54 MLX5_AN_LINK_UP = 3,
55 MLX5_AN_LINK_DOWN = 4,
56 };
57
58 #define MLX5_EEPROM_MAX_BYTES 32
59 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
60 #define MLX5_I2C_ADDR_LOW 0x50
61 #define MLX5_I2C_ADDR_HIGH 0x51
62 #define MLX5_EEPROM_PAGE_LENGTH 256
63 #define MLX5_EEPROM_HIGH_PAGE_LENGTH 128
64
65 enum mlx5e_link_mode {
66 MLX5E_1000BASE_CX_SGMII = 0,
67 MLX5E_1000BASE_KX = 1,
68 MLX5E_10GBASE_CX4 = 2,
69 MLX5E_10GBASE_KX4 = 3,
70 MLX5E_10GBASE_KR = 4,
71 MLX5E_20GBASE_KR2 = 5,
72 MLX5E_40GBASE_CR4 = 6,
73 MLX5E_40GBASE_KR4 = 7,
74 MLX5E_56GBASE_R4 = 8,
75 MLX5E_10GBASE_CR = 12,
76 MLX5E_10GBASE_SR = 13,
77 MLX5E_10GBASE_ER = 14,
78 MLX5E_40GBASE_SR4 = 15,
79 MLX5E_40GBASE_LR4 = 16,
80 MLX5E_50GBASE_SR2 = 18,
81 MLX5E_100GBASE_CR4 = 20,
82 MLX5E_100GBASE_SR4 = 21,
83 MLX5E_100GBASE_KR4 = 22,
84 MLX5E_100GBASE_LR4 = 23,
85 MLX5E_100BASE_TX = 24,
86 MLX5E_1000BASE_T = 25,
87 MLX5E_10GBASE_T = 26,
88 MLX5E_25GBASE_CR = 27,
89 MLX5E_25GBASE_KR = 28,
90 MLX5E_25GBASE_SR = 29,
91 MLX5E_50GBASE_CR2 = 30,
92 MLX5E_50GBASE_KR2 = 31,
93 MLX5E_LINK_MODES_NUMBER,
94 };
95
96 enum mlx5e_ext_link_mode {
97 MLX5E_SGMII_100M = 0,
98 MLX5E_1000BASE_X_SGMII = 1,
99 MLX5E_5GBASE_R = 3,
100 MLX5E_10GBASE_XFI_XAUI_1 = 4,
101 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
102 MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
103 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
104 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
105 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
106 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
107 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
108 MLX5E_400GAUI_8 = 15,
109 MLX5E_EXT_LINK_MODES_NUMBER,
110 };
111
112 enum mlx5e_connector_type {
113 MLX5E_PORT_UNKNOWN = 0,
114 MLX5E_PORT_NONE = 1,
115 MLX5E_PORT_TP = 2,
116 MLX5E_PORT_AUI = 3,
117 MLX5E_PORT_BNC = 4,
118 MLX5E_PORT_MII = 5,
119 MLX5E_PORT_FIBRE = 6,
120 MLX5E_PORT_DA = 7,
121 MLX5E_PORT_OTHER = 8,
122 MLX5E_CONNECTOR_TYPE_NUMBER,
123 };
124
125 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
126 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
127 (ext ? MLX5_GET(reg, out, ext_##field) : \
128 MLX5_GET(reg, out, field))
129
130 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
131 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
132 int ptys_size, int proto_mask, u8 local_port);
133 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
134 u8 *link_width_oper, u8 local_port);
135 int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
136 u8 *proto_oper, u8 local_port);
137 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
138 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
139 enum mlx5_port_status status);
140 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
141 enum mlx5_port_status *status);
142 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
143
144 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
145 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
146 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
147 u8 port);
148
149 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
150 u8 *vl_hw_cap, u8 local_port);
151
152 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
153 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
154 u32 *rx_pause, u32 *tx_pause);
155
156 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
157 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
158 u8 *pfc_en_rx);
159
160 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
161 u16 stall_critical_watermark,
162 u16 stall_minor_watermark);
163 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
164 u16 *stall_critical_watermark, u16 *stall_minor_watermark);
165
166 int mlx5_max_tc(struct mlx5_core_dev *mdev);
167
168 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
169 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
170 u8 prio, u8 *tc);
171 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
172 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
173 u8 tc, u8 *tc_group);
174 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
175 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
176 u8 tc, u8 *bw_pct);
177 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
178 u8 *max_bw_value,
179 u8 *max_bw_unit);
180 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
181 u8 *max_bw_value,
182 u8 *max_bw_unit);
183 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
184 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
185
186 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
187 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
188 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
189 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
190 bool *enabled);
191 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
192 u16 offset, u16 size, u8 *data);
193
194 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
195 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
196
197 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
198 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
199 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
200 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
201 #endif