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6 #ifndef __FCOE_COMMON__
7 #define __FCOE_COMMON__
8
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10
11
12
13 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
14
15
16 struct protection_info_ctx {
17 __le16 flags;
18 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
19 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
20 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
21 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
22 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
23 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
24 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
25 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
26 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
27 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
28 #define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
29 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
30 u8 dix_block_size;
31 u8 dst_size;
32 };
33
34
35 union protection_info_union_ctx {
36 struct protection_info_ctx info;
37 __le32 value;
38 };
39
40
41 struct fcoe_fcp_cmd_payload {
42 __le32 opaque[8];
43 };
44
45
46 struct fcoe_fcp_rsp_payload {
47 __le32 opaque[6];
48 };
49
50
51 struct fcp_rsp_payload_padded {
52 struct fcoe_fcp_rsp_payload rsp_payload;
53 __le32 reserved[2];
54 };
55
56
57 struct fcoe_fcp_xfer_payload {
58 __le32 opaque[3];
59 };
60
61
62 struct fcp_xfer_payload_padded {
63 struct fcoe_fcp_xfer_payload xfer_payload;
64 __le32 reserved[5];
65 };
66
67
68 struct fcoe_tx_data_params {
69 __le32 data_offset;
70 __le32 offset_in_io;
71 u8 flags;
72 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
73 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
74 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
75 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
76 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
77 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
78 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
79 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
80 u8 dif_residual;
81 __le16 seq_cnt;
82 __le16 single_sge_saved_offset;
83 __le16 next_dif_offset;
84 __le16 seq_id;
85 __le16 reserved3;
86 };
87
88
89 struct fcoe_tx_mid_path_params {
90 __le32 parameter;
91 u8 r_ctl;
92 u8 type;
93 u8 cs_ctl;
94 u8 df_ctl;
95 __le16 rx_id;
96 __le16 ox_id;
97 };
98
99
100 struct fcoe_tx_params {
101 struct fcoe_tx_data_params data;
102 struct fcoe_tx_mid_path_params mid_path;
103 };
104
105
106 union fcoe_tx_info_union_ctx {
107 struct fcoe_fcp_cmd_payload fcp_cmd_payload;
108 struct fcp_rsp_payload_padded fcp_rsp_payload;
109 struct fcp_xfer_payload_padded fcp_xfer_payload;
110 struct fcoe_tx_params tx_params;
111 };
112
113
114 struct fcoe_slow_sgl_ctx {
115 struct regpair base_sgl_addr;
116 __le16 curr_sge_off;
117 __le16 remainder_num_sges;
118 __le16 curr_sgl_index;
119 __le16 reserved;
120 };
121
122
123 union fcoe_dix_desc_ctx {
124 struct fcoe_slow_sgl_ctx dix_sgl;
125 struct scsi_sge cached_dix_sge;
126 };
127
128
129 struct ystorm_fcoe_task_st_ctx {
130 u8 task_type;
131 u8 sgl_mode;
132 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
133 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
134 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
135 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
136 u8 cached_dix_sge;
137 u8 expect_first_xfer;
138 __le32 num_pbf_zero_write;
139 union protection_info_union_ctx protection_info_union;
140 __le32 data_2_trns_rem;
141 struct scsi_sgl_params sgl_params;
142 u8 reserved1[12];
143 union fcoe_tx_info_union_ctx tx_info_union;
144 union fcoe_dix_desc_ctx dix_desc;
145 struct scsi_cached_sges data_desc;
146 __le16 ox_id;
147 __le16 rx_id;
148 __le32 task_rety_identifier;
149 u8 reserved2[8];
150 };
151
152 struct e4_ystorm_fcoe_task_ag_ctx {
153 u8 byte0;
154 u8 byte1;
155 __le16 word0;
156 u8 flags0;
157 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
158 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
159 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
160 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
161 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
162 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
163 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
164 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
165 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
166 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
167 u8 flags1;
168 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
169 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
170 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
171 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
172 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
173 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
174 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
175 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
176 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
177 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
178 u8 flags2;
179 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
180 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
181 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
182 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
183 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
184 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
185 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
186 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
187 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
188 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
189 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
190 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
191 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
192 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
193 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
194 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
195 u8 byte2;
196 __le32 reg0;
197 u8 byte3;
198 u8 byte4;
199 __le16 rx_id;
200 __le16 word2;
201 __le16 word3;
202 __le16 word4;
203 __le16 word5;
204 __le32 reg1;
205 __le32 reg2;
206 };
207
208 struct e4_tstorm_fcoe_task_ag_ctx {
209 u8 reserved;
210 u8 byte1;
211 __le16 icid;
212 u8 flags0;
213 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
214 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
215 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
216 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
217 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
218 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
219 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
220 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
221 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
222 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
223 u8 flags1;
224 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
225 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
226 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
227 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
228 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
229 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
230 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
231 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
232 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
233 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
234 u8 flags2;
235 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
236 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
237 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
238 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
239 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
240 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
241 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
242 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
243 u8 flags3;
244 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
245 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
246 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
247 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
248 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
249 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
250 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
251 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
252 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
253 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
254 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
255 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
256 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
257 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
258 u8 flags4;
259 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
260 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
261 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
262 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
263 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
264 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
265 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
266 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
267 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
268 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
269 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
270 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
271 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
272 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
273 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
274 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
275 u8 cleanup_state;
276 __le16 last_sent_tid;
277 __le32 rec_rr_tov_exp_timeout;
278 u8 byte3;
279 u8 byte4;
280 __le16 word2;
281 __le16 word3;
282 __le16 word4;
283 __le32 data_offset_end_of_seq;
284 __le32 data_offset_next;
285 };
286
287
288 struct fcoe_exp_ro {
289 __le32 data_offset;
290 __le32 reserved;
291 };
292
293
294 union fcoe_cleanup_addr_exp_ro_union {
295 struct regpair abts_rsp_fc_payload_hi;
296 struct fcoe_exp_ro exp_ro;
297 };
298
299
300 struct fcoe_abts_pkt {
301 __le32 abts_rsp_fc_payload_lo;
302 __le16 abts_rsp_rx_id;
303 u8 abts_rsp_rctl;
304 u8 reserved2;
305 };
306
307
308 struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
309 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
310 __le16 flags;
311 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
312 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
313 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
314 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
315 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
316 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
317 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
318 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
319 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
320 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
321 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
322 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
323 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
324 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
325 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
326 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
327 __le16 seq_cnt;
328 u8 seq_id;
329 u8 ooo_rx_seq_id;
330 __le16 rx_id;
331 struct fcoe_abts_pkt abts_data;
332 __le32 e_d_tov_exp_timeout_val;
333 __le16 ooo_rx_seq_cnt;
334 __le16 reserved1;
335 };
336
337
338 struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
339 u8 task_type;
340 u8 dev_type;
341 u8 conf_supported;
342 u8 glbl_q_num;
343 __le32 cid;
344 __le32 fcp_cmd_trns_size;
345 __le32 rsrv;
346 };
347
348
349 struct tstorm_fcoe_task_st_ctx {
350 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
351 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
352 };
353
354 struct e4_mstorm_fcoe_task_ag_ctx {
355 u8 byte0;
356 u8 byte1;
357 __le16 icid;
358 u8 flags0;
359 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
360 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
361 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
362 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
363 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
364 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
365 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
366 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
367 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
368 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
369 u8 flags1;
370 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
371 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
372 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
373 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
374 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
375 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
376 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
377 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
378 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
379 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
380 u8 flags2;
381 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
382 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
383 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
384 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
385 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
386 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
387 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
388 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
389 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
390 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
391 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
392 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
393 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
394 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
395 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
396 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
397 u8 cleanup_state;
398 __le32 received_bytes;
399 u8 byte3;
400 u8 glbl_q_num;
401 __le16 word1;
402 __le16 tid_to_xfer;
403 __le16 word3;
404 __le16 word4;
405 __le16 word5;
406 __le32 expected_bytes;
407 __le32 reg2;
408 };
409
410
411 struct mstorm_fcoe_task_st_ctx {
412 struct regpair rsp_buf_addr;
413 __le32 rsrv[2];
414 struct scsi_sgl_params sgl_params;
415 __le32 data_2_trns_rem;
416 __le32 data_buffer_offset;
417 __le16 parent_id;
418 __le16 flags;
419 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
420 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
421 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
422 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
423 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
424 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
425 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
426 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
427 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
428 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
429 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
430 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
431 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
432 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
433 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
434 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
435 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
436 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
437 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
438 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
439 struct scsi_cached_sges data_desc;
440 };
441
442 struct e4_ustorm_fcoe_task_ag_ctx {
443 u8 reserved;
444 u8 byte1;
445 __le16 icid;
446 u8 flags0;
447 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
448 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
449 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
450 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
451 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
452 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
453 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
454 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
455 u8 flags1;
456 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
457 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
458 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
459 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
460 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
461 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
462 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
463 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
464 u8 flags2;
465 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
466 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
467 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
468 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
469 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
470 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
471 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
472 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
473 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
474 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
475 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
476 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
477 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
478 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
479 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
480 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
481 u8 flags3;
482 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
483 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
484 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
485 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
486 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
487 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
488 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
489 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
490 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
491 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
492 __le32 dif_err_intervals;
493 __le32 dif_error_1st_interval;
494 __le32 global_cq_num;
495 __le32 reg3;
496 __le32 reg4;
497 __le32 reg5;
498 };
499
500
501 struct e4_fcoe_task_context {
502 struct ystorm_fcoe_task_st_ctx ystorm_st_context;
503 struct regpair ystorm_st_padding[2];
504 struct tdif_task_context tdif_context;
505 struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context;
506 struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context;
507 struct timers_context timer_context;
508 struct tstorm_fcoe_task_st_ctx tstorm_st_context;
509 struct regpair tstorm_st_padding[2];
510 struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context;
511 struct mstorm_fcoe_task_st_ctx mstorm_st_context;
512 struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context;
513 struct rdif_task_context rdif_context;
514 };
515
516
517 union fcoe_additional_info_union {
518 __le32 previous_tid;
519 __le32 parent_tid;
520 __le32 burst_length;
521 __le32 seq_rec_updated_offset;
522 };
523
524
525 enum fcoe_completion_status {
526 FCOE_COMPLETION_STATUS_SUCCESS,
527 FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
528 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
529 MAX_FCOE_COMPLETION_STATUS
530 };
531
532
533 struct fc_addr_nw {
534 u8 addr_lo;
535 u8 addr_mid;
536 u8 addr_hi;
537 };
538
539
540 struct fcoe_conn_offload_ramrod_data {
541 struct regpair sq_pbl_addr;
542 struct regpair sq_curr_page_addr;
543 struct regpair sq_next_page_addr;
544 struct regpair xferq_pbl_addr;
545 struct regpair xferq_curr_page_addr;
546 struct regpair xferq_next_page_addr;
547 struct regpair respq_pbl_addr;
548 struct regpair respq_curr_page_addr;
549 struct regpair respq_next_page_addr;
550 __le16 dst_mac_addr_lo;
551 __le16 dst_mac_addr_mid;
552 __le16 dst_mac_addr_hi;
553 __le16 src_mac_addr_lo;
554 __le16 src_mac_addr_mid;
555 __le16 src_mac_addr_hi;
556 __le16 tx_max_fc_pay_len;
557 __le16 e_d_tov_timer_val;
558 __le16 rx_max_fc_pay_len;
559 __le16 vlan_tag;
560 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
561 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
562 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
563 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
564 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
565 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
566 __le16 physical_q0;
567 __le16 rec_rr_tov_timer_val;
568 struct fc_addr_nw s_id;
569 u8 max_conc_seqs_c3;
570 struct fc_addr_nw d_id;
571 u8 flags;
572 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
573 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
574 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
575 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
576 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
577 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
578 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
579 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
580 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_MASK 0x1
581 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_SHIFT 4
582 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
583 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 5
584 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x1
585 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 7
586 __le16 conn_id;
587 u8 def_q_idx;
588 u8 reserved[5];
589 };
590
591
592 struct fcoe_conn_terminate_ramrod_data {
593 struct regpair terminate_params_addr;
594 };
595
596
597 enum fcoe_device_type {
598 FCOE_TASK_DEV_TYPE_DISK,
599 FCOE_TASK_DEV_TYPE_TAPE,
600 MAX_FCOE_DEVICE_TYPE
601 };
602
603
604 struct fcoe_fast_sgl_ctx {
605 struct regpair sgl_start_addr;
606 __le32 sgl_byte_offset;
607 __le16 task_reuse_cnt;
608 __le16 init_offset_in_first_sge;
609 };
610
611
612 struct fcoe_init_func_ramrod_data {
613 struct scsi_init_func_params func_params;
614 struct scsi_init_func_queues q_params;
615 __le16 mtu;
616 __le16 sq_num_pages_in_pbl;
617 __le32 reserved[3];
618 };
619
620
621 enum fcoe_mode_type {
622 FCOE_INITIATOR_MODE = 0x0,
623 FCOE_TARGET_MODE = 0x1,
624 FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
625 MAX_FCOE_MODE_TYPE
626 };
627
628
629 struct fcoe_rx_stat {
630 struct regpair fcoe_rx_byte_cnt;
631 struct regpair fcoe_rx_data_pkt_cnt;
632 struct regpair fcoe_rx_xfer_pkt_cnt;
633 struct regpair fcoe_rx_other_pkt_cnt;
634 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
635 __le32 fcoe_silent_drop_pkt_rq_full_cnt;
636 __le32 fcoe_silent_drop_pkt_crc_error_cnt;
637 __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
638 __le32 fcoe_silent_drop_total_pkt_cnt;
639 __le32 rsrv;
640 };
641
642
643 enum fcoe_sqe_request_type {
644 SEND_FCOE_CMD,
645 SEND_FCOE_MIDPATH,
646 SEND_FCOE_ABTS_REQUEST,
647 FCOE_EXCHANGE_CLEANUP,
648 FCOE_SEQUENCE_RECOVERY,
649 SEND_FCOE_XFER_RDY,
650 SEND_FCOE_RSP,
651 SEND_FCOE_RSP_WITH_SENSE_DATA,
652 SEND_FCOE_TARGET_DATA,
653 SEND_FCOE_INITIATOR_DATA,
654 SEND_FCOE_XFER_CONTINUATION_RDY,
655 SEND_FCOE_TARGET_ABTS_RSP,
656 MAX_FCOE_SQE_REQUEST_TYPE
657 };
658
659
660 struct fcoe_stat_ramrod_data {
661 struct regpair stat_params_addr;
662 };
663
664
665 enum fcoe_task_type {
666 FCOE_TASK_TYPE_WRITE_INITIATOR,
667 FCOE_TASK_TYPE_READ_INITIATOR,
668 FCOE_TASK_TYPE_MIDPATH,
669 FCOE_TASK_TYPE_UNSOLICITED,
670 FCOE_TASK_TYPE_ABTS,
671 FCOE_TASK_TYPE_EXCHANGE_CLEANUP,
672 FCOE_TASK_TYPE_SEQUENCE_CLEANUP,
673 FCOE_TASK_TYPE_WRITE_TARGET,
674 FCOE_TASK_TYPE_READ_TARGET,
675 FCOE_TASK_TYPE_RSP,
676 FCOE_TASK_TYPE_RSP_SENSE_DATA,
677 FCOE_TASK_TYPE_ABTS_TARGET,
678 FCOE_TASK_TYPE_ENUM_SIZE,
679 MAX_FCOE_TASK_TYPE
680 };
681
682
683 struct fcoe_tx_stat {
684 struct regpair fcoe_tx_byte_cnt;
685 struct regpair fcoe_tx_data_pkt_cnt;
686 struct regpair fcoe_tx_xfer_pkt_cnt;
687 struct regpair fcoe_tx_other_pkt_cnt;
688 };
689
690
691 struct fcoe_wqe {
692 __le16 task_id;
693 __le16 flags;
694 #define FCOE_WQE_REQ_TYPE_MASK 0xF
695 #define FCOE_WQE_REQ_TYPE_SHIFT 0
696 #define FCOE_WQE_SGL_MODE_MASK 0x1
697 #define FCOE_WQE_SGL_MODE_SHIFT 4
698 #define FCOE_WQE_CONTINUATION_MASK 0x1
699 #define FCOE_WQE_CONTINUATION_SHIFT 5
700 #define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
701 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
702 #define FCOE_WQE_RESERVED_MASK 0x1
703 #define FCOE_WQE_RESERVED_SHIFT 7
704 #define FCOE_WQE_NUM_SGES_MASK 0xF
705 #define FCOE_WQE_NUM_SGES_SHIFT 8
706 #define FCOE_WQE_RESERVED1_MASK 0xF
707 #define FCOE_WQE_RESERVED1_SHIFT 12
708 union fcoe_additional_info_union additional_info_union;
709 };
710
711
712 struct xfrqe_prot_flags {
713 u8 flags;
714 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
715 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
716 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
717 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
718 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
719 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
720 #define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
721 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
722 };
723
724
725 struct fcoe_db_data {
726 u8 params;
727 #define FCOE_DB_DATA_DEST_MASK 0x3
728 #define FCOE_DB_DATA_DEST_SHIFT 0
729 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3
730 #define FCOE_DB_DATA_AGG_CMD_SHIFT 2
731 #define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
732 #define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
733 #define FCOE_DB_DATA_RESERVED_MASK 0x1
734 #define FCOE_DB_DATA_RESERVED_SHIFT 5
735 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
736 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
737 u8 agg_flags;
738 __le16 sq_prod;
739 };
740
741 #endif