1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * AD9523 SPI Low Jitter Clock Generator
4 *
5 * Copyright 2012 Analog Devices Inc.
6 */
7
8 #ifndef IIO_FREQUENCY_AD9523_H_
9 #define IIO_FREQUENCY_AD9523_H_
10
11 enum outp_drv_mode {
12 TRISTATE,
13 LVPECL_8mA,
14 LVDS_4mA,
15 LVDS_7mA,
16 HSTL0_16mA,
17 HSTL1_8mA,
18 CMOS_CONF1,
19 CMOS_CONF2,
20 CMOS_CONF3,
21 CMOS_CONF4,
22 CMOS_CONF5,
23 CMOS_CONF6,
24 CMOS_CONF7,
25 CMOS_CONF8,
26 CMOS_CONF9
27 };
28
29 enum ref_sel_mode {
30 NONEREVERTIVE_STAY_ON_REFB,
31 REVERT_TO_REFA,
32 SELECT_REFA,
33 SELECT_REFB,
34 EXT_REF_SEL
35 };
36
37 /**
38 * struct ad9523_channel_spec - Output channel configuration
39 *
40 * @channel_num: Output channel number.
41 * @divider_output_invert_en: Invert the polarity of the output clock.
42 * @sync_ignore_en: Ignore chip-level SYNC signal.
43 * @low_power_mode_en: Reduce power used in the differential output modes.
44 * @use_alt_clock_src: Channel divider uses alternative clk source.
45 * @output_dis: Disables, powers down the entire channel.
46 * @driver_mode: Output driver mode (logic level family).
47 * @divider_phase: Divider initial phase after a SYNC. Range 0..63
48 LSB = 1/2 of a period of the divider input clock.
49 * @channel_divider: 10-bit channel divider.
50 * @extended_name: Optional descriptive channel name.
51 */
52
53 struct ad9523_channel_spec {
54 unsigned channel_num;
55 bool divider_output_invert_en;
56 bool sync_ignore_en;
57 bool low_power_mode_en;
58 /* CH0..CH3 VCXO, CH4..CH9 VCO2 */
59 bool use_alt_clock_src;
60 bool output_dis;
61 enum outp_drv_mode driver_mode;
62 unsigned char divider_phase;
63 unsigned short channel_divider;
64 char extended_name[16];
65 };
66
67 enum pll1_rzero_resistor {
68 RZERO_883_OHM,
69 RZERO_677_OHM,
70 RZERO_341_OHM,
71 RZERO_135_OHM,
72 RZERO_10_OHM,
73 RZERO_USE_EXT_RES = 8,
74 };
75
76 enum rpole2_resistor {
77 RPOLE2_900_OHM,
78 RPOLE2_450_OHM,
79 RPOLE2_300_OHM,
80 RPOLE2_225_OHM,
81 };
82
83 enum rzero_resistor {
84 RZERO_3250_OHM,
85 RZERO_2750_OHM,
86 RZERO_2250_OHM,
87 RZERO_2100_OHM,
88 RZERO_3000_OHM,
89 RZERO_2500_OHM,
90 RZERO_2000_OHM,
91 RZERO_1850_OHM,
92 };
93
94 enum cpole1_capacitor {
95 CPOLE1_0_PF,
96 CPOLE1_8_PF,
97 CPOLE1_16_PF,
98 CPOLE1_24_PF,
99 _CPOLE1_24_PF, /* place holder */
100 CPOLE1_32_PF,
101 CPOLE1_40_PF,
102 CPOLE1_48_PF,
103 };
104
105 /**
106 * struct ad9523_platform_data - platform specific information
107 *
108 * @vcxo_freq: External VCXO frequency in Hz
109 * @refa_diff_rcv_en: REFA differential/single-ended input selection.
110 * @refb_diff_rcv_en: REFB differential/single-ended input selection.
111 * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
112 * @osc_in_diff_en: OSC differential/ single-ended input selection.
113 * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
114 * @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
115 * @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
116 * @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
117 * @refa_r_div: PLL1 10-bit REFA R divider.
118 * @refb_r_div: PLL1 10-bit REFB R divider.
119 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
120 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
121 * @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection.
122 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
123 * the OSC_IN receiver or zero delay mode
124 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
125 * @ref_mode: Reference selection mode.
126 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
127 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
129 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
130 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
131 * @pll2_vco_div_m1: VCO1 divider, range 3..5.
132 * @pll2_vco_div_m2: VCO2 divider, range 3..5.
133 * @rpole2: PLL2 loop filter Rpole resistor value.
134 * @rzero: PLL2 loop filter Rzero resistor value.
135 * @cpole1: PLL2 loop filter Cpole capacitor value.
136 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
137 * @num_channels: Array size of struct ad9523_channel_spec.
138 * @channels: Pointer to channel array.
139 * @name: Optional alternative iio device name.
140 */
141
142 struct ad9523_platform_data {
143 unsigned long vcxo_freq;
144
145 /* Differential/ Single-Ended Input Configuration */
146 bool refa_diff_rcv_en;
147 bool refb_diff_rcv_en;
148 bool zd_in_diff_en;
149 bool osc_in_diff_en;
150
151 /*
152 * Valid if differential input disabled
153 * if false defaults to pos input
154 */
155 bool refa_cmos_neg_inp_en;
156 bool refb_cmos_neg_inp_en;
157 bool zd_in_cmos_neg_inp_en;
158 bool osc_in_cmos_neg_inp_en;
159
160 /* PLL1 Setting */
161 unsigned short refa_r_div;
162 unsigned short refb_r_div;
163 unsigned short pll1_feedback_div;
164 unsigned short pll1_charge_pump_current_nA;
165 bool zero_delay_mode_internal_en;
166 bool osc_in_feedback_en;
167 enum pll1_rzero_resistor pll1_loop_filter_rzero;
168
169 /* Reference */
170 enum ref_sel_mode ref_mode;
171
172 /* PLL2 Setting */
173 unsigned int pll2_charge_pump_current_nA;
174 unsigned char pll2_ndiv_a_cnt;
175 unsigned char pll2_ndiv_b_cnt;
176 bool pll2_freq_doubler_en;
177 unsigned char pll2_r2_div;
178 unsigned char pll2_vco_div_m1; /* 3..5 */
179 unsigned char pll2_vco_div_m2; /* 3..5 */
180
181 /* Loop Filter PLL2 */
182 enum rpole2_resistor rpole2;
183 enum rzero_resistor rzero;
184 enum cpole1_capacitor cpole1;
185 bool rzero_bypass_en;
186
187 /* Output Channel Configuration */
188 int num_channels;
189 struct ad9523_channel_spec *channels;
190
191 char name[SPI_NAME_SIZE];
192 };
193
194 #endif /* IIO_FREQUENCY_AD9523_H_ */