1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * board initialization code should put one of these into dev->platform_data
4 * and place the isp1362 onto platform_bus.
5 */
6
7 #ifndef __LINUX_USB_ISP1362_H__
8 #define __LINUX_USB_ISP1362_H__
9
10 struct isp1362_platform_data {
11 /* Enable internal pulldown resistors on downstream ports */
12 unsigned sel15Kres:1;
13 /* Clock cannot be stopped */
14 unsigned clknotstop:1;
15 /* On-chip overcurrent protection */
16 unsigned oc_enable:1;
17 /* INT output polarity */
18 unsigned int_act_high:1;
19 /* INT edge or level triggered */
20 unsigned int_edge_triggered:1;
21 /* DREQ output polarity */
22 unsigned dreq_act_high:1;
23 /* DACK input polarity */
24 unsigned dack_act_high:1;
25 /* chip can be resumed via H_WAKEUP pin */
26 unsigned remote_wakeup_connected:1;
27 /* Switch or not to switch (keep always powered) */
28 unsigned no_power_switching:1;
29 /* Ganged port power switching (0) or individual port power switching (1) */
30 unsigned power_switching_mode:1;
31 /* Given port_power, msec/2 after power on till power good */
32 u8 potpg;
33 /* Hardware reset set/clear */
34 void (*reset) (struct device *dev, int set);
35 /* Clock start/stop */
36 void (*clock) (struct device *dev, int start);
37 /* Inter-io delay (ns). The chip is picky about access timings; it
38 * expects at least:
39 * 110ns delay between consecutive accesses to DATA_REG,
40 * 300ns delay between access to ADDR_REG and DATA_REG (registers)
41 * 462ns delay between access to ADDR_REG and DATA_REG (buffer memory)
42 * WE MUST NOT be activated during these intervals (even without CS!)
43 */
44 void (*delay) (struct device *dev, unsigned int delay);
45 };
46
47 #endif