1 /* SPDX-License-Identifier: GPL-2.0-or-later
2 *
3 * Copyright (C) 2005 David Brownell
4 */
5
6 #ifndef __LINUX_SPI_H
7 #define __LINUX_SPI_H
8
9 #include <linux/device.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/slab.h>
12 #include <linux/kthread.h>
13 #include <linux/completion.h>
14 #include <linux/scatterlist.h>
15 #include <linux/gpio/consumer.h>
16
17 struct dma_chan;
18 struct property_entry;
19 struct spi_controller;
20 struct spi_transfer;
21 struct spi_controller_mem_ops;
22
23 /*
24 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
25 * and SPI infrastructure.
26 */
27 extern struct bus_type spi_bus_type;
28
29 /**
30 * struct spi_statistics - statistics for spi transfers
31 * @lock: lock protecting this structure
32 *
33 * @messages: number of spi-messages handled
34 * @transfers: number of spi_transfers handled
35 * @errors: number of errors during spi_transfer
36 * @timedout: number of timeouts during spi_transfer
37 *
38 * @spi_sync: number of times spi_sync is used
39 * @spi_sync_immediate:
40 * number of times spi_sync is executed immediately
41 * in calling context without queuing and scheduling
42 * @spi_async: number of times spi_async is used
43 *
44 * @bytes: number of bytes transferred to/from device
45 * @bytes_tx: number of bytes sent to device
46 * @bytes_rx: number of bytes received from device
47 *
48 * @transfer_bytes_histo:
49 * transfer bytes histogramm
50 *
51 * @transfers_split_maxsize:
52 * number of transfers that have been split because of
53 * maxsize limit
54 */
55 struct spi_statistics {
56 spinlock_t lock; /* lock for the whole structure */
57
58 unsigned long messages;
59 unsigned long transfers;
60 unsigned long errors;
61 unsigned long timedout;
62
63 unsigned long spi_sync;
64 unsigned long spi_sync_immediate;
65 unsigned long spi_async;
66
67 unsigned long long bytes;
68 unsigned long long bytes_rx;
69 unsigned long long bytes_tx;
70
71 #define SPI_STATISTICS_HISTO_SIZE 17
72 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
73
74 unsigned long transfers_split_maxsize;
75 };
76
77 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
78 struct spi_transfer *xfer,
79 struct spi_controller *ctlr);
80
81 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
82 do { \
83 unsigned long flags; \
84 spin_lock_irqsave(&(stats)->lock, flags); \
85 (stats)->field += count; \
86 spin_unlock_irqrestore(&(stats)->lock, flags); \
87 } while (0)
88
89 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
90 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
91
92 /**
93 * struct spi_device - Controller side proxy for an SPI slave device
94 * @dev: Driver model representation of the device.
95 * @controller: SPI controller used with the device.
96 * @master: Copy of controller, for backwards compatibility.
97 * @max_speed_hz: Maximum clock rate to be used with this chip
98 * (on this board); may be changed by the device's driver.
99 * The spi_transfer.speed_hz can override this for each transfer.
100 * @chip_select: Chipselect, distinguishing chips handled by @controller.
101 * @mode: The spi mode defines how data is clocked out and in.
102 * This may be changed by the device's driver.
103 * The "active low" default for chipselect mode can be overridden
104 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
105 * each word in a transfer (by specifying SPI_LSB_FIRST).
106 * @bits_per_word: Data transfers involve one or more words; word sizes
107 * like eight or 12 bits are common. In-memory wordsizes are
108 * powers of two bytes (e.g. 20 bit samples use 32 bits).
109 * This may be changed by the device's driver, or left at the
110 * default (0) indicating protocol words are eight bit bytes.
111 * The spi_transfer.bits_per_word can override this for each transfer.
112 * @rt: Make the pump thread real time priority.
113 * @irq: Negative, or the number passed to request_irq() to receive
114 * interrupts from this device.
115 * @controller_state: Controller's runtime state
116 * @controller_data: Board-specific definitions for controller, such as
117 * FIFO initialization parameters; from board_info.controller_data
118 * @modalias: Name of the driver to use with this device, or an alias
119 * for that name. This appears in the sysfs "modalias" attribute
120 * for driver coldplugging, and in uevents used for hotplugging
121 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when
122 * not using a GPIO line) use cs_gpiod in new drivers by opting in on
123 * the spi_master.
124 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when
125 * not using a GPIO line)
126 * @word_delay_usecs: microsecond delay to be inserted between consecutive
127 * words of a transfer
128 *
129 * @statistics: statistics for the spi_device
130 *
131 * A @spi_device is used to interchange data between an SPI slave
132 * (usually a discrete chip) and CPU memory.
133 *
134 * In @dev, the platform_data is used to hold information about this
135 * device that's meaningful to the device's protocol driver, but not
136 * to its controller. One example might be an identifier for a chip
137 * variant with slightly different functionality; another might be
138 * information about how this particular board wires the chip's pins.
139 */
140 struct spi_device {
141 struct device dev;
142 struct spi_controller *controller;
143 struct spi_controller *master; /* compatibility layer */
144 u32 max_speed_hz;
145 u8 chip_select;
146 u8 bits_per_word;
147 bool rt;
148 u32 mode;
149 #define SPI_CPHA 0x01 /* clock phase */
150 #define SPI_CPOL 0x02 /* clock polarity */
151 #define SPI_MODE_0 (0|0) /* (original MicroWire) */
152 #define SPI_MODE_1 (0|SPI_CPHA)
153 #define SPI_MODE_2 (SPI_CPOL|0)
154 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
155 #define SPI_CS_HIGH 0x04 /* chipselect active high? */
156 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
157 #define SPI_3WIRE 0x10 /* SI/SO signals shared */
158 #define SPI_LOOP 0x20 /* loopback mode */
159 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
160 #define SPI_READY 0x80 /* slave pulls low to pause */
161 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
162 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
163 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
164 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
165 #define SPI_CS_WORD 0x1000 /* toggle cs after each word */
166 #define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
167 #define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
168 #define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */
169 int irq;
170 void *controller_state;
171 void *controller_data;
172 char modalias[SPI_NAME_SIZE];
173 const char *driver_override;
174 int cs_gpio; /* LEGACY: chip select gpio */
175 struct gpio_desc *cs_gpiod; /* chip select gpio desc */
176 uint8_t word_delay_usecs; /* inter-word delay */
177
178 /* the statistics */
179 struct spi_statistics statistics;
180
181 /*
182 * likely need more hooks for more protocol options affecting how
183 * the controller talks to each chip, like:
184 * - memory packing (12 bit samples into low bits, others zeroed)
185 * - priority
186 * - chipselect delays
187 * - ...
188 */
189 };
190
191 static inline struct spi_device *to_spi_device(struct device *dev)
192 {
193 return dev ? container_of(dev, struct spi_device, dev) : NULL;
194 }
195
196 /* most drivers won't need to care about device refcounting */
197 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
198 {
199 return (spi && get_device(&spi->dev)) ? spi : NULL;
200 }
201
202 static inline void spi_dev_put(struct spi_device *spi)
203 {
204 if (spi)
205 put_device(&spi->dev);
206 }
207
208 /* ctldata is for the bus_controller driver's runtime state */
209 static inline void *spi_get_ctldata(struct spi_device *spi)
210 {
211 return spi->controller_state;
212 }
213
214 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
215 {
216 spi->controller_state = state;
217 }
218
219 /* device driver data */
220
221 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
222 {
223 dev_set_drvdata(&spi->dev, data);
224 }
225
226 static inline void *spi_get_drvdata(struct spi_device *spi)
227 {
228 return dev_get_drvdata(&spi->dev);
229 }
230
231 struct spi_message;
232 struct spi_transfer;
233
234 /**
235 * struct spi_driver - Host side "protocol" driver
236 * @id_table: List of SPI devices supported by this driver
237 * @probe: Binds this driver to the spi device. Drivers can verify
238 * that the device is actually present, and may need to configure
239 * characteristics (such as bits_per_word) which weren't needed for
240 * the initial configuration done during system setup.
241 * @remove: Unbinds this driver from the spi device
242 * @shutdown: Standard shutdown callback used during system state
243 * transitions such as powerdown/halt and kexec
244 * @driver: SPI device drivers should initialize the name and owner
245 * field of this structure.
246 *
247 * This represents the kind of device driver that uses SPI messages to
248 * interact with the hardware at the other end of a SPI link. It's called
249 * a "protocol" driver because it works through messages rather than talking
250 * directly to SPI hardware (which is what the underlying SPI controller
251 * driver does to pass those messages). These protocols are defined in the
252 * specification for the device(s) supported by the driver.
253 *
254 * As a rule, those device protocols represent the lowest level interface
255 * supported by a driver, and it will support upper level interfaces too.
256 * Examples of such upper levels include frameworks like MTD, networking,
257 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
258 */
259 struct spi_driver {
260 const struct spi_device_id *id_table;
261 int (*probe)(struct spi_device *spi);
262 int (*remove)(struct spi_device *spi);
263 void (*shutdown)(struct spi_device *spi);
264 struct device_driver driver;
265 };
266
267 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
268 {
269 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
270 }
271
272 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
273
274 /**
275 * spi_unregister_driver - reverse effect of spi_register_driver
276 * @sdrv: the driver to unregister
277 * Context: can sleep
278 */
279 static inline void spi_unregister_driver(struct spi_driver *sdrv)
280 {
281 if (sdrv)
282 driver_unregister(&sdrv->driver);
283 }
284
285 /* use a define to avoid include chaining to get THIS_MODULE */
286 #define spi_register_driver(driver) \
287 __spi_register_driver(THIS_MODULE, driver)
288
289 /**
290 * module_spi_driver() - Helper macro for registering a SPI driver
291 * @__spi_driver: spi_driver struct
292 *
293 * Helper macro for SPI drivers which do not do anything special in module
294 * init/exit. This eliminates a lot of boilerplate. Each module may only
295 * use this macro once, and calling it replaces module_init() and module_exit()
296 */
297 #define module_spi_driver(__spi_driver) \
298 module_driver(__spi_driver, spi_register_driver, \
299 spi_unregister_driver)
300
301 /**
302 * struct spi_controller - interface to SPI master or slave controller
303 * @dev: device interface to this driver
304 * @list: link with the global spi_controller list
305 * @bus_num: board-specific (and often SOC-specific) identifier for a
306 * given SPI controller.
307 * @num_chipselect: chipselects are used to distinguish individual
308 * SPI slaves, and are numbered from zero to num_chipselects.
309 * each slave has a chipselect signal, but it's common that not
310 * every chipselect is connected to a slave.
311 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
312 * @mode_bits: flags understood by this controller driver
313 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
314 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
315 * supported. If set, the SPI core will reject any transfer with an
316 * unsupported bits_per_word. If not set, this value is simply ignored,
317 * and it's up to the individual driver to perform any validation.
318 * @min_speed_hz: Lowest supported transfer speed
319 * @max_speed_hz: Highest supported transfer speed
320 * @flags: other constraints relevant to this driver
321 * @slave: indicates that this is an SPI slave controller
322 * @max_transfer_size: function that returns the max transfer size for
323 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
324 * @max_message_size: function that returns the max message size for
325 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
326 * @io_mutex: mutex for physical bus access
327 * @bus_lock_spinlock: spinlock for SPI bus locking
328 * @bus_lock_mutex: mutex for exclusion of multiple callers
329 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
330 * @setup: updates the device mode and clocking records used by a
331 * device's SPI controller; protocol code may call this. This
332 * must fail if an unrecognized or unsupported mode is requested.
333 * It's always safe to call this unless transfers are pending on
334 * the device whose settings are being modified.
335 * @set_cs_timing: optional hook for SPI devices to request SPI master
336 * controller for configuring specific CS setup time, hold time and inactive
337 * delay interms of clock counts
338 * @transfer: adds a message to the controller's transfer queue.
339 * @cleanup: frees controller-specific state
340 * @can_dma: determine whether this controller supports DMA
341 * @queued: whether this controller is providing an internal message queue
342 * @kworker: thread struct for message pump
343 * @kworker_task: pointer to task for message pump kworker thread
344 * @pump_messages: work struct for scheduling work to the message pump
345 * @queue_lock: spinlock to syncronise access to message queue
346 * @queue: message queue
347 * @idling: the device is entering idle state
348 * @cur_msg: the currently in-flight message
349 * @cur_msg_prepared: spi_prepare_message was called for the currently
350 * in-flight message
351 * @cur_msg_mapped: message has been mapped for DMA
352 * @xfer_completion: used by core transfer_one_message()
353 * @busy: message pump is busy
354 * @running: message pump is running
355 * @rt: whether this queue is set to run as a realtime task
356 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
357 * while the hardware is prepared, using the parent
358 * device for the spidev
359 * @max_dma_len: Maximum length of a DMA transfer for the device.
360 * @prepare_transfer_hardware: a message will soon arrive from the queue
361 * so the subsystem requests the driver to prepare the transfer hardware
362 * by issuing this call
363 * @transfer_one_message: the subsystem calls the driver to transfer a single
364 * message while queuing transfers that arrive in the meantime. When the
365 * driver is finished with this message, it must call
366 * spi_finalize_current_message() so the subsystem can issue the next
367 * message
368 * @unprepare_transfer_hardware: there are currently no more messages on the
369 * queue so the subsystem notifies the driver that it may relax the
370 * hardware by issuing this call
371 *
372 * @set_cs: set the logic level of the chip select line. May be called
373 * from interrupt context.
374 * @prepare_message: set up the controller to transfer a single message,
375 * for example doing DMA mapping. Called from threaded
376 * context.
377 * @transfer_one: transfer a single spi_transfer.
378 * - return 0 if the transfer is finished,
379 * - return 1 if the transfer is still in progress. When
380 * the driver is finished with this transfer it must
381 * call spi_finalize_current_transfer() so the subsystem
382 * can issue the next transfer. Note: transfer_one and
383 * transfer_one_message are mutually exclusive; when both
384 * are set, the generic subsystem does not call your
385 * transfer_one callback.
386 * @handle_err: the subsystem calls the driver to handle an error that occurs
387 * in the generic implementation of transfer_one_message().
388 * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
389 * This field is optional and should only be implemented if the
390 * controller has native support for memory like operations.
391 * @unprepare_message: undo any work done by prepare_message().
392 * @slave_abort: abort the ongoing transfer request on an SPI slave controller
393 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
394 * CS number. Any individual value may be -ENOENT for CS lines that
395 * are not GPIOs (driven by the SPI controller itself). Use the cs_gpiods
396 * in new drivers.
397 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
398 * number. Any individual value may be NULL for CS lines that
399 * are not GPIOs (driven by the SPI controller itself).
400 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab
401 * GPIO descriptors rather than using global GPIO numbers grabbed by the
402 * driver. This will fill in @cs_gpiods and @cs_gpios should not be used,
403 * and SPI devices will have the cs_gpiod assigned rather than cs_gpio.
404 * @statistics: statistics for the spi_controller
405 * @dma_tx: DMA transmit channel
406 * @dma_rx: DMA receive channel
407 * @dummy_rx: dummy receive buffer for full-duplex devices
408 * @dummy_tx: dummy transmit buffer for full-duplex devices
409 * @fw_translate_cs: If the boot firmware uses different numbering scheme
410 * what Linux expects, this optional hook can be used to translate
411 * between the two.
412 *
413 * Each SPI controller can communicate with one or more @spi_device
414 * children. These make a small bus, sharing MOSI, MISO and SCK signals
415 * but not chip select signals. Each device may be configured to use a
416 * different clock rate, since those shared signals are ignored unless
417 * the chip is selected.
418 *
419 * The driver for an SPI controller manages access to those devices through
420 * a queue of spi_message transactions, copying data between CPU memory and
421 * an SPI slave device. For each such message it queues, it calls the
422 * message's completion function when the transaction completes.
423 */
424 struct spi_controller {
425 struct device dev;
426
427 struct list_head list;
428
429 /* other than negative (== assign one dynamically), bus_num is fully
430 * board-specific. usually that simplifies to being SOC-specific.
431 * example: one SOC has three SPI controllers, numbered 0..2,
432 * and one board's schematics might show it using SPI-2. software
433 * would normally use bus_num=2 for that controller.
434 */
435 s16 bus_num;
436
437 /* chipselects will be integral to many controllers; some others
438 * might use board-specific GPIOs.
439 */
440 u16 num_chipselect;
441
442 /* some SPI controllers pose alignment requirements on DMAable
443 * buffers; let protocol drivers know about these requirements.
444 */
445 u16 dma_alignment;
446
447 /* spi_device.mode flags understood by this controller driver */
448 u32 mode_bits;
449
450 /* bitmask of supported bits_per_word for transfers */
451 u32 bits_per_word_mask;
452 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
453 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
454
455 /* limits on transfer speed */
456 u32 min_speed_hz;
457 u32 max_speed_hz;
458
459 /* other constraints relevant to this driver */
460 u16 flags;
461 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */
462 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */
463 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */
464 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */
465 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */
466
467 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
468
469 /* flag indicating this is an SPI slave controller */
470 bool slave;
471
472 /*
473 * on some hardware transfer / message size may be constrained
474 * the limit may depend on device transfer settings
475 */
476 size_t (*max_transfer_size)(struct spi_device *spi);
477 size_t (*max_message_size)(struct spi_device *spi);
478
479 /* I/O mutex */
480 struct mutex io_mutex;
481
482 /* lock and mutex for SPI bus locking */
483 spinlock_t bus_lock_spinlock;
484 struct mutex bus_lock_mutex;
485
486 /* flag indicating that the SPI bus is locked for exclusive use */
487 bool bus_lock_flag;
488
489 /* Setup mode and clock, etc (spi driver may call many times).
490 *
491 * IMPORTANT: this may be called when transfers to another
492 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
493 * which could break those transfers.
494 */
495 int (*setup)(struct spi_device *spi);
496
497 /*
498 * set_cs_timing() method is for SPI controllers that supports
499 * configuring CS timing.
500 *
501 * This hook allows SPI client drivers to request SPI controllers
502 * to configure specific CS timing through spi_set_cs_timing() after
503 * spi_setup().
504 */
505 void (*set_cs_timing)(struct spi_device *spi, u8 setup_clk_cycles,
506 u8 hold_clk_cycles, u8 inactive_clk_cycles);
507
508 /* bidirectional bulk transfers
509 *
510 * + The transfer() method may not sleep; its main role is
511 * just to add the message to the queue.
512 * + For now there's no remove-from-queue operation, or
513 * any other request management
514 * + To a given spi_device, message queueing is pure fifo
515 *
516 * + The controller's main job is to process its message queue,
517 * selecting a chip (for masters), then transferring data
518 * + If there are multiple spi_device children, the i/o queue
519 * arbitration algorithm is unspecified (round robin, fifo,
520 * priority, reservations, preemption, etc)
521 *
522 * + Chipselect stays active during the entire message
523 * (unless modified by spi_transfer.cs_change != 0).
524 * + The message transfers use clock and SPI mode parameters
525 * previously established by setup() for this device
526 */
527 int (*transfer)(struct spi_device *spi,
528 struct spi_message *mesg);
529
530 /* called on release() to free memory provided by spi_controller */
531 void (*cleanup)(struct spi_device *spi);
532
533 /*
534 * Used to enable core support for DMA handling, if can_dma()
535 * exists and returns true then the transfer will be mapped
536 * prior to transfer_one() being called. The driver should
537 * not modify or store xfer and dma_tx and dma_rx must be set
538 * while the device is prepared.
539 */
540 bool (*can_dma)(struct spi_controller *ctlr,
541 struct spi_device *spi,
542 struct spi_transfer *xfer);
543
544 /*
545 * These hooks are for drivers that want to use the generic
546 * controller transfer queueing mechanism. If these are used, the
547 * transfer() function above must NOT be specified by the driver.
548 * Over time we expect SPI drivers to be phased over to this API.
549 */
550 bool queued;
551 struct kthread_worker kworker;
552 struct task_struct *kworker_task;
553 struct kthread_work pump_messages;
554 spinlock_t queue_lock;
555 struct list_head queue;
556 struct spi_message *cur_msg;
557 bool idling;
558 bool busy;
559 bool running;
560 bool rt;
561 bool auto_runtime_pm;
562 bool cur_msg_prepared;
563 bool cur_msg_mapped;
564 struct completion xfer_completion;
565 size_t max_dma_len;
566
567 int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
568 int (*transfer_one_message)(struct spi_controller *ctlr,
569 struct spi_message *mesg);
570 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
571 int (*prepare_message)(struct spi_controller *ctlr,
572 struct spi_message *message);
573 int (*unprepare_message)(struct spi_controller *ctlr,
574 struct spi_message *message);
575 int (*slave_abort)(struct spi_controller *ctlr);
576
577 /*
578 * These hooks are for drivers that use a generic implementation
579 * of transfer_one_message() provied by the core.
580 */
581 void (*set_cs)(struct spi_device *spi, bool enable);
582 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
583 struct spi_transfer *transfer);
584 void (*handle_err)(struct spi_controller *ctlr,
585 struct spi_message *message);
586
587 /* Optimized handlers for SPI memory-like operations. */
588 const struct spi_controller_mem_ops *mem_ops;
589
590 /* gpio chip select */
591 int *cs_gpios;
592 struct gpio_desc **cs_gpiods;
593 bool use_gpio_descriptors;
594
595 /* statistics */
596 struct spi_statistics statistics;
597
598 /* DMA channels for use with core dmaengine helpers */
599 struct dma_chan *dma_tx;
600 struct dma_chan *dma_rx;
601
602 /* dummy data for full duplex devices */
603 void *dummy_rx;
604 void *dummy_tx;
605
606 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
607 };
608
609 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
610 {
611 return dev_get_drvdata(&ctlr->dev);
612 }
613
614 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
615 void *data)
616 {
617 dev_set_drvdata(&ctlr->dev, data);
618 }
619
620 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
621 {
622 if (!ctlr || !get_device(&ctlr->dev))
623 return NULL;
624 return ctlr;
625 }
626
627 static inline void spi_controller_put(struct spi_controller *ctlr)
628 {
629 if (ctlr)
630 put_device(&ctlr->dev);
631 }
632
633 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
634 {
635 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
636 }
637
638 /* PM calls that need to be issued by the driver */
639 extern int spi_controller_suspend(struct spi_controller *ctlr);
640 extern int spi_controller_resume(struct spi_controller *ctlr);
641
642 /* Calls the driver make to interact with the message queue */
643 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
644 extern void spi_finalize_current_message(struct spi_controller *ctlr);
645 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
646
647 /* the spi driver core manages memory for the spi_controller classdev */
648 extern struct spi_controller *__spi_alloc_controller(struct device *host,
649 unsigned int size, bool slave);
650
651 static inline struct spi_controller *spi_alloc_master(struct device *host,
652 unsigned int size)
653 {
654 return __spi_alloc_controller(host, size, false);
655 }
656
657 static inline struct spi_controller *spi_alloc_slave(struct device *host,
658 unsigned int size)
659 {
660 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
661 return NULL;
662
663 return __spi_alloc_controller(host, size, true);
664 }
665
666 extern int spi_register_controller(struct spi_controller *ctlr);
667 extern int devm_spi_register_controller(struct device *dev,
668 struct spi_controller *ctlr);
669 extern void spi_unregister_controller(struct spi_controller *ctlr);
670
671 extern struct spi_controller *spi_busnum_to_master(u16 busnum);
672
673 /*
674 * SPI resource management while processing a SPI message
675 */
676
677 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
678 struct spi_message *msg,
679 void *res);
680
681 /**
682 * struct spi_res - spi resource management structure
683 * @entry: list entry
684 * @release: release code called prior to freeing this resource
685 * @data: extra data allocated for the specific use-case
686 *
687 * this is based on ideas from devres, but focused on life-cycle
688 * management during spi_message processing
689 */
690 struct spi_res {
691 struct list_head entry;
692 spi_res_release_t release;
693 unsigned long long data[]; /* guarantee ull alignment */
694 };
695
696 extern void *spi_res_alloc(struct spi_device *spi,
697 spi_res_release_t release,
698 size_t size, gfp_t gfp);
699 extern void spi_res_add(struct spi_message *message, void *res);
700 extern void spi_res_free(void *res);
701
702 extern void spi_res_release(struct spi_controller *ctlr,
703 struct spi_message *message);
704
705 /*---------------------------------------------------------------------------*/
706
707 /*
708 * I/O INTERFACE between SPI controller and protocol drivers
709 *
710 * Protocol drivers use a queue of spi_messages, each transferring data
711 * between the controller and memory buffers.
712 *
713 * The spi_messages themselves consist of a series of read+write transfer
714 * segments. Those segments always read the same number of bits as they
715 * write; but one or the other is easily ignored by passing a null buffer
716 * pointer. (This is unlike most types of I/O API, because SPI hardware
717 * is full duplex.)
718 *
719 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
720 * up to the protocol driver, which guarantees the integrity of both (as
721 * well as the data buffers) for as long as the message is queued.
722 */
723
724 /**
725 * struct spi_transfer - a read/write buffer pair
726 * @tx_buf: data to be written (dma-safe memory), or NULL
727 * @rx_buf: data to be read (dma-safe memory), or NULL
728 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
729 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
730 * @tx_nbits: number of bits used for writing. If 0 the default
731 * (SPI_NBITS_SINGLE) is used.
732 * @rx_nbits: number of bits used for reading. If 0 the default
733 * (SPI_NBITS_SINGLE) is used.
734 * @len: size of rx and tx buffers (in bytes)
735 * @speed_hz: Select a speed other than the device default for this
736 * transfer. If 0 the default (from @spi_device) is used.
737 * @bits_per_word: select a bits_per_word other than the device default
738 * for this transfer. If 0 the default (from @spi_device) is used.
739 * @cs_change: affects chipselect after this transfer completes
740 * @cs_change_delay: delay between cs deassert and assert when
741 * @cs_change is set and @spi_transfer is not the last in @spi_message
742 * @cs_change_delay_unit: unit of cs_change_delay
743 * @delay_usecs: microseconds to delay after this transfer before
744 * (optionally) changing the chipselect status, then starting
745 * the next transfer or completing this @spi_message.
746 * @word_delay_usecs: microseconds to inter word delay after each word size
747 * (set by bits_per_word) transmission.
748 * @word_delay: clock cycles to inter word delay after each word size
749 * (set by bits_per_word) transmission.
750 * @effective_speed_hz: the effective SCK-speed that was used to
751 * transfer this transfer. Set to 0 if the spi bus driver does
752 * not support it.
753 * @transfer_list: transfers are sequenced through @spi_message.transfers
754 * @tx_sg: Scatterlist for transmit, currently not for client use
755 * @rx_sg: Scatterlist for receive, currently not for client use
756 *
757 * SPI transfers always write the same number of bytes as they read.
758 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
759 * In some cases, they may also want to provide DMA addresses for
760 * the data being transferred; that may reduce overhead, when the
761 * underlying driver uses dma.
762 *
763 * If the transmit buffer is null, zeroes will be shifted out
764 * while filling @rx_buf. If the receive buffer is null, the data
765 * shifted in will be discarded. Only "len" bytes shift out (or in).
766 * It's an error to try to shift out a partial word. (For example, by
767 * shifting out three bytes with word size of sixteen or twenty bits;
768 * the former uses two bytes per word, the latter uses four bytes.)
769 *
770 * In-memory data values are always in native CPU byte order, translated
771 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
772 * for example when bits_per_word is sixteen, buffers are 2N bytes long
773 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
774 *
775 * When the word size of the SPI transfer is not a power-of-two multiple
776 * of eight bits, those in-memory words include extra bits. In-memory
777 * words are always seen by protocol drivers as right-justified, so the
778 * undefined (rx) or unused (tx) bits are always the most significant bits.
779 *
780 * All SPI transfers start with the relevant chipselect active. Normally
781 * it stays selected until after the last transfer in a message. Drivers
782 * can affect the chipselect signal using cs_change.
783 *
784 * (i) If the transfer isn't the last one in the message, this flag is
785 * used to make the chipselect briefly go inactive in the middle of the
786 * message. Toggling chipselect in this way may be needed to terminate
787 * a chip command, letting a single spi_message perform all of group of
788 * chip transactions together.
789 *
790 * (ii) When the transfer is the last one in the message, the chip may
791 * stay selected until the next transfer. On multi-device SPI busses
792 * with nothing blocking messages going to other devices, this is just
793 * a performance hint; starting a message to another device deselects
794 * this one. But in other cases, this can be used to ensure correctness.
795 * Some devices need protocol transactions to be built from a series of
796 * spi_message submissions, where the content of one message is determined
797 * by the results of previous messages and where the whole transaction
798 * ends when the chipselect goes intactive.
799 *
800 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
801 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
802 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
803 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
804 *
805 * The code that submits an spi_message (and its spi_transfers)
806 * to the lower layers is responsible for managing its memory.
807 * Zero-initialize every field you don't set up explicitly, to
808 * insulate against future API updates. After you submit a message
809 * and its transfers, ignore them until its completion callback.
810 */
811 struct spi_transfer {
812 /* it's ok if tx_buf == rx_buf (right?)
813 * for MicroWire, one buffer must be null
814 * buffers must work with dma_*map_single() calls, unless
815 * spi_message.is_dma_mapped reports a pre-existing mapping
816 */
817 const void *tx_buf;
818 void *rx_buf;
819 unsigned len;
820
821 dma_addr_t tx_dma;
822 dma_addr_t rx_dma;
823 struct sg_table tx_sg;
824 struct sg_table rx_sg;
825
826 unsigned cs_change:1;
827 unsigned tx_nbits:3;
828 unsigned rx_nbits:3;
829 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
830 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
831 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
832 u8 bits_per_word;
833 u8 word_delay_usecs;
834 u16 delay_usecs;
835 u16 cs_change_delay;
836 u8 cs_change_delay_unit;
837 #define SPI_DELAY_UNIT_USECS 0
838 #define SPI_DELAY_UNIT_NSECS 1
839 #define SPI_DELAY_UNIT_SCK 2
840 u32 speed_hz;
841 u16 word_delay;
842
843 u32 effective_speed_hz;
844
845 struct list_head transfer_list;
846 };
847
848 /**
849 * struct spi_message - one multi-segment SPI transaction
850 * @transfers: list of transfer segments in this transaction
851 * @spi: SPI device to which the transaction is queued
852 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
853 * addresses for each transfer buffer
854 * @complete: called to report transaction completions
855 * @context: the argument to complete() when it's called
856 * @frame_length: the total number of bytes in the message
857 * @actual_length: the total number of bytes that were transferred in all
858 * successful segments
859 * @status: zero for success, else negative errno
860 * @queue: for use by whichever driver currently owns the message
861 * @state: for use by whichever driver currently owns the message
862 * @resources: for resource management when the spi message is processed
863 *
864 * A @spi_message is used to execute an atomic sequence of data transfers,
865 * each represented by a struct spi_transfer. The sequence is "atomic"
866 * in the sense that no other spi_message may use that SPI bus until that
867 * sequence completes. On some systems, many such sequences can execute as
868 * as single programmed DMA transfer. On all systems, these messages are
869 * queued, and might complete after transactions to other devices. Messages
870 * sent to a given spi_device are always executed in FIFO order.
871 *
872 * The code that submits an spi_message (and its spi_transfers)
873 * to the lower layers is responsible for managing its memory.
874 * Zero-initialize every field you don't set up explicitly, to
875 * insulate against future API updates. After you submit a message
876 * and its transfers, ignore them until its completion callback.
877 */
878 struct spi_message {
879 struct list_head transfers;
880
881 struct spi_device *spi;
882
883 unsigned is_dma_mapped:1;
884
885 /* REVISIT: we might want a flag affecting the behavior of the
886 * last transfer ... allowing things like "read 16 bit length L"
887 * immediately followed by "read L bytes". Basically imposing
888 * a specific message scheduling algorithm.
889 *
890 * Some controller drivers (message-at-a-time queue processing)
891 * could provide that as their default scheduling algorithm. But
892 * others (with multi-message pipelines) could need a flag to
893 * tell them about such special cases.
894 */
895
896 /* completion is reported through a callback */
897 void (*complete)(void *context);
898 void *context;
899 unsigned frame_length;
900 unsigned actual_length;
901 int status;
902
903 /* for optional use by whatever driver currently owns the
904 * spi_message ... between calls to spi_async and then later
905 * complete(), that's the spi_controller controller driver.
906 */
907 struct list_head queue;
908 void *state;
909
910 /* list of spi_res reources when the spi message is processed */
911 struct list_head resources;
912 };
913
914 static inline void spi_message_init_no_memset(struct spi_message *m)
915 {
916 INIT_LIST_HEAD(&m->transfers);
917 INIT_LIST_HEAD(&m->resources);
918 }
919
920 static inline void spi_message_init(struct spi_message *m)
921 {
922 memset(m, 0, sizeof *m);
923 spi_message_init_no_memset(m);
924 }
925
926 static inline void
927 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
928 {
929 list_add_tail(&t->transfer_list, &m->transfers);
930 }
931
932 static inline void
933 spi_transfer_del(struct spi_transfer *t)
934 {
935 list_del(&t->transfer_list);
936 }
937
938 /**
939 * spi_message_init_with_transfers - Initialize spi_message and append transfers
940 * @m: spi_message to be initialized
941 * @xfers: An array of spi transfers
942 * @num_xfers: Number of items in the xfer array
943 *
944 * This function initializes the given spi_message and adds each spi_transfer in
945 * the given array to the message.
946 */
947 static inline void
948 spi_message_init_with_transfers(struct spi_message *m,
949 struct spi_transfer *xfers, unsigned int num_xfers)
950 {
951 unsigned int i;
952
953 spi_message_init(m);
954 for (i = 0; i < num_xfers; ++i)
955 spi_message_add_tail(&xfers[i], m);
956 }
957
958 /* It's fine to embed message and transaction structures in other data
959 * structures so long as you don't free them while they're in use.
960 */
961
962 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
963 {
964 struct spi_message *m;
965
966 m = kzalloc(sizeof(struct spi_message)
967 + ntrans * sizeof(struct spi_transfer),
968 flags);
969 if (m) {
970 unsigned i;
971 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
972
973 spi_message_init_no_memset(m);
974 for (i = 0; i < ntrans; i++, t++)
975 spi_message_add_tail(t, m);
976 }
977 return m;
978 }
979
980 static inline void spi_message_free(struct spi_message *m)
981 {
982 kfree(m);
983 }
984
985 extern void spi_set_cs_timing(struct spi_device *spi, u8 setup, u8 hold, u8 inactive_dly);
986
987 extern int spi_setup(struct spi_device *spi);
988 extern int spi_async(struct spi_device *spi, struct spi_message *message);
989 extern int spi_async_locked(struct spi_device *spi,
990 struct spi_message *message);
991 extern int spi_slave_abort(struct spi_device *spi);
992
993 static inline size_t
994 spi_max_message_size(struct spi_device *spi)
995 {
996 struct spi_controller *ctlr = spi->controller;
997
998 if (!ctlr->max_message_size)
999 return SIZE_MAX;
1000 return ctlr->max_message_size(spi);
1001 }
1002
1003 static inline size_t
1004 spi_max_transfer_size(struct spi_device *spi)
1005 {
1006 struct spi_controller *ctlr = spi->controller;
1007 size_t tr_max = SIZE_MAX;
1008 size_t msg_max = spi_max_message_size(spi);
1009
1010 if (ctlr->max_transfer_size)
1011 tr_max = ctlr->max_transfer_size(spi);
1012
1013 /* transfer size limit must not be greater than messsage size limit */
1014 return min(tr_max, msg_max);
1015 }
1016
1017 /**
1018 * spi_is_bpw_supported - Check if bits per word is supported
1019 * @spi: SPI device
1020 * @bpw: Bits per word
1021 *
1022 * This function checks to see if the SPI controller supports @bpw.
1023 *
1024 * Returns:
1025 * True if @bpw is supported, false otherwise.
1026 */
1027 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
1028 {
1029 u32 bpw_mask = spi->master->bits_per_word_mask;
1030
1031 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
1032 return true;
1033
1034 return false;
1035 }
1036
1037 /*---------------------------------------------------------------------------*/
1038
1039 /* SPI transfer replacement methods which make use of spi_res */
1040
1041 struct spi_replaced_transfers;
1042 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
1043 struct spi_message *msg,
1044 struct spi_replaced_transfers *res);
1045 /**
1046 * struct spi_replaced_transfers - structure describing the spi_transfer
1047 * replacements that have occurred
1048 * so that they can get reverted
1049 * @release: some extra release code to get executed prior to
1050 * relasing this structure
1051 * @extradata: pointer to some extra data if requested or NULL
1052 * @replaced_transfers: transfers that have been replaced and which need
1053 * to get restored
1054 * @replaced_after: the transfer after which the @replaced_transfers
1055 * are to get re-inserted
1056 * @inserted: number of transfers inserted
1057 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1058 * that have been replacing replaced_transfers
1059 *
1060 * note: that @extradata will point to @inserted_transfers[@inserted]
1061 * if some extra allocation is requested, so alignment will be the same
1062 * as for spi_transfers
1063 */
1064 struct spi_replaced_transfers {
1065 spi_replaced_release_t release;
1066 void *extradata;
1067 struct list_head replaced_transfers;
1068 struct list_head *replaced_after;
1069 size_t inserted;
1070 struct spi_transfer inserted_transfers[];
1071 };
1072
1073 extern struct spi_replaced_transfers *spi_replace_transfers(
1074 struct spi_message *msg,
1075 struct spi_transfer *xfer_first,
1076 size_t remove,
1077 size_t insert,
1078 spi_replaced_release_t release,
1079 size_t extradatasize,
1080 gfp_t gfp);
1081
1082 /*---------------------------------------------------------------------------*/
1083
1084 /* SPI transfer transformation methods */
1085
1086 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1087 struct spi_message *msg,
1088 size_t maxsize,
1089 gfp_t gfp);
1090
1091 /*---------------------------------------------------------------------------*/
1092
1093 /* All these synchronous SPI transfer routines are utilities layered
1094 * over the core async transfer primitive. Here, "synchronous" means
1095 * they will sleep uninterruptibly until the async transfer completes.
1096 */
1097
1098 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1099 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1100 extern int spi_bus_lock(struct spi_controller *ctlr);
1101 extern int spi_bus_unlock(struct spi_controller *ctlr);
1102
1103 /**
1104 * spi_sync_transfer - synchronous SPI data transfer
1105 * @spi: device with which data will be exchanged
1106 * @xfers: An array of spi_transfers
1107 * @num_xfers: Number of items in the xfer array
1108 * Context: can sleep
1109 *
1110 * Does a synchronous SPI data transfer of the given spi_transfer array.
1111 *
1112 * For more specific semantics see spi_sync().
1113 *
1114 * Return: Return: zero on success, else a negative error code.
1115 */
1116 static inline int
1117 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1118 unsigned int num_xfers)
1119 {
1120 struct spi_message msg;
1121
1122 spi_message_init_with_transfers(&msg, xfers, num_xfers);
1123
1124 return spi_sync(spi, &msg);
1125 }
1126
1127 /**
1128 * spi_write - SPI synchronous write
1129 * @spi: device to which data will be written
1130 * @buf: data buffer
1131 * @len: data buffer size
1132 * Context: can sleep
1133 *
1134 * This function writes the buffer @buf.
1135 * Callable only from contexts that can sleep.
1136 *
1137 * Return: zero on success, else a negative error code.
1138 */
1139 static inline int
1140 spi_write(struct spi_device *spi, const void *buf, size_t len)
1141 {
1142 struct spi_transfer t = {
1143 .tx_buf = buf,
1144 .len = len,
1145 };
1146
1147 return spi_sync_transfer(spi, &t, 1);
1148 }
1149
1150 /**
1151 * spi_read - SPI synchronous read
1152 * @spi: device from which data will be read
1153 * @buf: data buffer
1154 * @len: data buffer size
1155 * Context: can sleep
1156 *
1157 * This function reads the buffer @buf.
1158 * Callable only from contexts that can sleep.
1159 *
1160 * Return: zero on success, else a negative error code.
1161 */
1162 static inline int
1163 spi_read(struct spi_device *spi, void *buf, size_t len)
1164 {
1165 struct spi_transfer t = {
1166 .rx_buf = buf,
1167 .len = len,
1168 };
1169
1170 return spi_sync_transfer(spi, &t, 1);
1171 }
1172
1173 /* this copies txbuf and rxbuf data; for small transfers only! */
1174 extern int spi_write_then_read(struct spi_device *spi,
1175 const void *txbuf, unsigned n_tx,
1176 void *rxbuf, unsigned n_rx);
1177
1178 /**
1179 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1180 * @spi: device with which data will be exchanged
1181 * @cmd: command to be written before data is read back
1182 * Context: can sleep
1183 *
1184 * Callable only from contexts that can sleep.
1185 *
1186 * Return: the (unsigned) eight bit number returned by the
1187 * device, or else a negative error code.
1188 */
1189 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1190 {
1191 ssize_t status;
1192 u8 result;
1193
1194 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1195
1196 /* return negative errno or unsigned value */
1197 return (status < 0) ? status : result;
1198 }
1199
1200 /**
1201 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1202 * @spi: device with which data will be exchanged
1203 * @cmd: command to be written before data is read back
1204 * Context: can sleep
1205 *
1206 * The number is returned in wire-order, which is at least sometimes
1207 * big-endian.
1208 *
1209 * Callable only from contexts that can sleep.
1210 *
1211 * Return: the (unsigned) sixteen bit number returned by the
1212 * device, or else a negative error code.
1213 */
1214 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1215 {
1216 ssize_t status;
1217 u16 result;
1218
1219 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1220
1221 /* return negative errno or unsigned value */
1222 return (status < 0) ? status : result;
1223 }
1224
1225 /**
1226 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1227 * @spi: device with which data will be exchanged
1228 * @cmd: command to be written before data is read back
1229 * Context: can sleep
1230 *
1231 * This function is similar to spi_w8r16, with the exception that it will
1232 * convert the read 16 bit data word from big-endian to native endianness.
1233 *
1234 * Callable only from contexts that can sleep.
1235 *
1236 * Return: the (unsigned) sixteen bit number returned by the device in cpu
1237 * endianness, or else a negative error code.
1238 */
1239 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1240
1241 {
1242 ssize_t status;
1243 __be16 result;
1244
1245 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1246 if (status < 0)
1247 return status;
1248
1249 return be16_to_cpu(result);
1250 }
1251
1252 /*---------------------------------------------------------------------------*/
1253
1254 /*
1255 * INTERFACE between board init code and SPI infrastructure.
1256 *
1257 * No SPI driver ever sees these SPI device table segments, but
1258 * it's how the SPI core (or adapters that get hotplugged) grows
1259 * the driver model tree.
1260 *
1261 * As a rule, SPI devices can't be probed. Instead, board init code
1262 * provides a table listing the devices which are present, with enough
1263 * information to bind and set up the device's driver. There's basic
1264 * support for nonstatic configurations too; enough to handle adding
1265 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1266 */
1267
1268 /**
1269 * struct spi_board_info - board-specific template for a SPI device
1270 * @modalias: Initializes spi_device.modalias; identifies the driver.
1271 * @platform_data: Initializes spi_device.platform_data; the particular
1272 * data stored there is driver-specific.
1273 * @properties: Additional device properties for the device.
1274 * @controller_data: Initializes spi_device.controller_data; some
1275 * controllers need hints about hardware setup, e.g. for DMA.
1276 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1277 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1278 * from the chip datasheet and board-specific signal quality issues.
1279 * @bus_num: Identifies which spi_controller parents the spi_device; unused
1280 * by spi_new_device(), and otherwise depends on board wiring.
1281 * @chip_select: Initializes spi_device.chip_select; depends on how
1282 * the board is wired.
1283 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1284 * wiring (some devices support both 3WIRE and standard modes), and
1285 * possibly presence of an inverter in the chipselect path.
1286 *
1287 * When adding new SPI devices to the device tree, these structures serve
1288 * as a partial device template. They hold information which can't always
1289 * be determined by drivers. Information that probe() can establish (such
1290 * as the default transfer wordsize) is not included here.
1291 *
1292 * These structures are used in two places. Their primary role is to
1293 * be stored in tables of board-specific device descriptors, which are
1294 * declared early in board initialization and then used (much later) to
1295 * populate a controller's device tree after the that controller's driver
1296 * initializes. A secondary (and atypical) role is as a parameter to
1297 * spi_new_device() call, which happens after those controller drivers
1298 * are active in some dynamic board configuration models.
1299 */
1300 struct spi_board_info {
1301 /* the device name and module name are coupled, like platform_bus;
1302 * "modalias" is normally the driver name.
1303 *
1304 * platform_data goes to spi_device.dev.platform_data,
1305 * controller_data goes to spi_device.controller_data,
1306 * device properties are copied and attached to spi_device,
1307 * irq is copied too
1308 */
1309 char modalias[SPI_NAME_SIZE];
1310 const void *platform_data;
1311 const struct property_entry *properties;
1312 void *controller_data;
1313 int irq;
1314
1315 /* slower signaling on noisy or low voltage boards */
1316 u32 max_speed_hz;
1317
1318
1319 /* bus_num is board specific and matches the bus_num of some
1320 * spi_controller that will probably be registered later.
1321 *
1322 * chip_select reflects how this chip is wired to that master;
1323 * it's less than num_chipselect.
1324 */
1325 u16 bus_num;
1326 u16 chip_select;
1327
1328 /* mode becomes spi_device.mode, and is essential for chips
1329 * where the default of SPI_CS_HIGH = 0 is wrong.
1330 */
1331 u32 mode;
1332
1333 /* ... may need additional spi_device chip config data here.
1334 * avoid stuff protocol drivers can set; but include stuff
1335 * needed to behave without being bound to a driver:
1336 * - quirks like clock rate mattering when not selected
1337 */
1338 };
1339
1340 #ifdef CONFIG_SPI
1341 extern int
1342 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1343 #else
1344 /* board init code may ignore whether SPI is configured or not */
1345 static inline int
1346 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1347 { return 0; }
1348 #endif
1349
1350 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1351 * use spi_new_device() to describe each device. You can also call
1352 * spi_unregister_device() to start making that device vanish, but
1353 * normally that would be handled by spi_unregister_controller().
1354 *
1355 * You can also use spi_alloc_device() and spi_add_device() to use a two
1356 * stage registration sequence for each spi_device. This gives the caller
1357 * some more control over the spi_device structure before it is registered,
1358 * but requires that caller to initialize fields that would otherwise
1359 * be defined using the board info.
1360 */
1361 extern struct spi_device *
1362 spi_alloc_device(struct spi_controller *ctlr);
1363
1364 extern int
1365 spi_add_device(struct spi_device *spi);
1366
1367 extern struct spi_device *
1368 spi_new_device(struct spi_controller *, struct spi_board_info *);
1369
1370 extern void spi_unregister_device(struct spi_device *spi);
1371
1372 extern const struct spi_device_id *
1373 spi_get_device_id(const struct spi_device *sdev);
1374
1375 static inline bool
1376 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1377 {
1378 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1379 }
1380
1381 /* OF support code */
1382 #if IS_ENABLED(CONFIG_OF)
1383
1384 /* must call put_device() when done with returned spi_device device */
1385 extern struct spi_device *
1386 of_find_spi_device_by_node(struct device_node *node);
1387
1388 #else
1389
1390 static inline struct spi_device *
1391 of_find_spi_device_by_node(struct device_node *node)
1392 {
1393 return NULL;
1394 }
1395
1396 #endif /* IS_ENABLED(CONFIG_OF) */
1397
1398 /* Compatibility layer */
1399 #define spi_master spi_controller
1400
1401 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX
1402 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX
1403 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX
1404 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX
1405 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX
1406
1407 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr)
1408 #define spi_master_set_devdata(_ctlr, _data) \
1409 spi_controller_set_devdata(_ctlr, _data)
1410 #define spi_master_get(_ctlr) spi_controller_get(_ctlr)
1411 #define spi_master_put(_ctlr) spi_controller_put(_ctlr)
1412 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr)
1413 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr)
1414
1415 #define spi_register_master(_ctlr) spi_register_controller(_ctlr)
1416 #define devm_spi_register_master(_dev, _ctlr) \
1417 devm_spi_register_controller(_dev, _ctlr)
1418 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr)
1419
1420 #endif /* __LINUX_SPI_H */