1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * pxa2xx_ssp.h
4 *
5 * Copyright (C) 2003 Russell King, All Rights Reserved.
6 *
7 * This driver supports the following PXA CPU/SSP ports:-
8 *
9 * PXA250 SSP
10 * PXA255 SSP, NSSP
11 * PXA26x SSP, NSSP, ASSP
12 * PXA27x SSP1, SSP2, SSP3
13 * PXA3xx SSP1, SSP2, SSP3, SSP4
14 */
15
16 #ifndef __LINUX_SSP_H
17 #define __LINUX_SSP_H
18
19 #include <linux/list.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22
23
24 /*
25 * SSP Serial Port Registers
26 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
27 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
28 */
29
30 #define SSCR0 (0x00) /* SSP Control Register 0 */
31 #define SSCR1 (0x04) /* SSP Control Register 1 */
32 #define SSSR (0x08) /* SSP Status Register */
33 #define SSITR (0x0C) /* SSP Interrupt Test Register */
34 #define SSDR (0x10) /* SSP Data Write/Data Read Register */
35
36 #define SSTO (0x28) /* SSP Time Out Register */
37 #define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
38 #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
39 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
40 #define SSRSA (0x34) /* SSP Rx Timeslot Active */
41 #define SSTSS (0x38) /* SSP Timeslot Status */
42 #define SSACD (0x3C) /* SSP Audio Clock Divider */
43 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
44
45 /* Common PXA2xx bits first */
46 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
47 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
48 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
49 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
50 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
51 #define SSCR0_National (0x2 << 4) /* National Microwire */
52 #define SSCR0_ECS (1 << 6) /* External clock select */
53 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
54 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
55
56 /* PXA27x, PXA3xx */
57 #define SSCR0_EDSS (1 << 20) /* Extended data size select */
58 #define SSCR0_NCS (1 << 21) /* Network clock select */
59 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
60 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
61 #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
62 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
63 #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
64 #define SSCR0_ACS (1 << 30) /* Audio clock select */
65 #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
66
67
68 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
69 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
70 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
71 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
72 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
73 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
74
75 #define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */
76 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
77 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
78 #define SSSR_BSY (1 << 4) /* SSP Busy */
79 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
80 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
81 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
82
83 #define RX_THRESH_DFLT 8
84 #define TX_THRESH_DFLT 8
85
86 #define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */
87 #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
88
89 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
90 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
91 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
92 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
93
94 #define RX_THRESH_CE4100_DFLT 2
95 #define TX_THRESH_CE4100_DFLT 2
96
97 #define CE4100_SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
98 #define CE4100_SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
99
100 #define CE4100_SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
101 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
102 #define CE4100_SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
103 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
104
105 /* QUARK_X1000 SSCR0 bit definition */
106 #define QUARK_X1000_SSCR0_DSS (0x1F << 0) /* Data Size Select (mask) */
107 #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
108 #define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */
109 #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */
110
111 #define RX_THRESH_QUARK_X1000_DFLT 1
112 #define TX_THRESH_QUARK_X1000_DFLT 16
113
114 #define QUARK_X1000_SSSR_TFL_MASK (0x1F << 8) /* Transmit FIFO Level mask */
115 #define QUARK_X1000_SSSR_RFL_MASK (0x1F << 13) /* Receive FIFO Level mask */
116
117 #define QUARK_X1000_SSCR1_TFT (0x1F << 6) /* Transmit FIFO Threshold (mask) */
118 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
119 #define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */
120 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
121 #define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */
122 #define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */
123
124 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
125 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
126 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
127 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
128 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
129 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
130 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
131 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
132 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
133 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
134 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
135 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
136 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
137 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
138 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
139 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
140 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */
141 #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
142 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
143 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
144
145 #define SSSR_BCE (1 << 23) /* Bit Count Error */
146 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
147 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
148 #define SSSR_EOC (1 << 20) /* End Of Chain */
149 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
150 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
151
152
153 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
154 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
155 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
156 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
157 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
158 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
159 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
160 #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
161 #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
162
163 /* PXA3xx */
164 #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
165 #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
166 #define SSPSP_TIMING_MASK (0x7f8001f0)
167
168 #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
169 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
170 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
171 #define SSACD_ACDS_1 (0)
172 #define SSACD_ACDS_2 (1)
173 #define SSACD_ACDS_4 (2)
174 #define SSACD_ACDS_8 (3)
175 #define SSACD_ACDS_16 (4)
176 #define SSACD_ACDS_32 (5)
177 #define SSACD_SCDB_4X (0)
178 #define SSACD_SCDB_1X (1)
179 #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
180
181 /* LPSS SSP */
182 #define SSITF 0x44 /* TX FIFO trigger level */
183 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
184 #define SSITF_TxHiThresh(x) ((x) - 1)
185
186 #define SSIRF 0x48 /* RX FIFO trigger level */
187 #define SSIRF_RxThresh(x) ((x) - 1)
188
189 enum pxa_ssp_type {
190 SSP_UNDEFINED = 0,
191 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
192 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
193 PXA27x_SSP,
194 PXA3xx_SSP,
195 PXA168_SSP,
196 MMP2_SSP,
197 PXA910_SSP,
198 CE4100_SSP,
199 QUARK_X1000_SSP,
200 LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
201 LPSS_BYT_SSP,
202 LPSS_BSW_SSP,
203 LPSS_SPT_SSP,
204 LPSS_BXT_SSP,
205 LPSS_CNL_SSP,
206 };
207
208 struct ssp_device {
209 struct platform_device *pdev;
210 struct list_head node;
211
212 struct clk *clk;
213 void __iomem *mmio_base;
214 unsigned long phys_base;
215
216 const char *label;
217 int port_id;
218 enum pxa_ssp_type type;
219 int use_count;
220 int irq;
221
222 struct device_node *of_node;
223 };
224
225 /**
226 * pxa_ssp_write_reg - Write to a SSP register
227 *
228 * @dev: SSP device to access
229 * @reg: Register to write to
230 * @val: Value to be written.
231 */
232 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
233 {
234 __raw_writel(val, dev->mmio_base + reg);
235 }
236
237 /**
238 * pxa_ssp_read_reg - Read from a SSP register
239 *
240 * @dev: SSP device to access
241 * @reg: Register to read from
242 */
243 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
244 {
245 return __raw_readl(dev->mmio_base + reg);
246 }
247
248 #if IS_ENABLED(CONFIG_PXA_SSP)
249 struct ssp_device *pxa_ssp_request(int port, const char *label);
250 void pxa_ssp_free(struct ssp_device *);
251 struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
252 const char *label);
253 #else
254 static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
255 {
256 return NULL;
257 }
258 static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
259 const char *name)
260 {
261 return NULL;
262 }
263 static inline void pxa_ssp_free(struct ssp_device *ssp) {}
264 #endif
265
266 #endif