1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3
4 #ifndef __SOUNDWIRE_H
5 #define __SOUNDWIRE_H
6
7 #include <linux/mod_devicetable.h>
8
9 struct sdw_bus;
10 struct sdw_slave;
11
12 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
13
14 /* SDW Broadcast Device Number */
15 #define SDW_BROADCAST_DEV_NUM 15
16
17 /* SDW Enumeration Device Number */
18 #define SDW_ENUM_DEV_NUM 0
19
20 /* SDW Group Device Numbers */
21 #define SDW_GROUP12_DEV_NUM 12
22 #define SDW_GROUP13_DEV_NUM 13
23
24 /* SDW Master Device Number, not supported yet */
25 #define SDW_MASTER_DEV_NUM 14
26
27 #define SDW_NUM_DEV_ID_REGISTERS 6
28 /* frame shape defines */
29
30 /*
31 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
32 * fill hole with 0, one more dummy entry is added
33 */
34 #define SDW_FRAME_ROWS 24
35 #define SDW_FRAME_COLS 8
36 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
37
38 #define SDW_FRAME_CTRL_BITS 48
39 #define SDW_MAX_DEVICES 11
40
41 #define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1)
42
43 #define SDW_DAI_ID_RANGE_START 100
44 #define SDW_DAI_ID_RANGE_END 200
45
46 enum {
47 SDW_PORT_DIRN_SINK = 0,
48 SDW_PORT_DIRN_SOURCE,
49 SDW_PORT_DIRN_MAX,
50 };
51
52 /*
53 * constants for flow control, ports and transport
54 *
55 * these are bit masks as devices can have multiple capabilities
56 */
57
58 /*
59 * flow modes for SDW port. These can be isochronous, tx controlled,
60 * rx controlled or async
61 */
62 #define SDW_PORT_FLOW_MODE_ISOCH 0
63 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
64 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
65 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
66
67 /* sample packaging for block. It can be per port or per channel */
68 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
69 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
70
71 /**
72 * enum sdw_slave_status - Slave status
73 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
74 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
75 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
76 * @SDW_SLAVE_RESERVED: Reserved for future use
77 */
78 enum sdw_slave_status {
79 SDW_SLAVE_UNATTACHED = 0,
80 SDW_SLAVE_ATTACHED = 1,
81 SDW_SLAVE_ALERT = 2,
82 SDW_SLAVE_RESERVED = 3,
83 };
84
85 /**
86 * enum sdw_command_response - Command response as defined by SDW spec
87 * @SDW_CMD_OK: cmd was successful
88 * @SDW_CMD_IGNORED: cmd was ignored
89 * @SDW_CMD_FAIL: cmd was NACKed
90 * @SDW_CMD_TIMEOUT: cmd timedout
91 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
92 *
93 * NOTE: The enum is different than actual Spec as response in the Spec is
94 * combination of ACK/NAK bits
95 *
96 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
97 */
98 enum sdw_command_response {
99 SDW_CMD_OK = 0,
100 SDW_CMD_IGNORED = 1,
101 SDW_CMD_FAIL = 2,
102 SDW_CMD_TIMEOUT = 3,
103 SDW_CMD_FAIL_OTHER = 4,
104 };
105
106 /* block group count enum */
107 enum sdw_dpn_grouping {
108 SDW_BLK_GRP_CNT_1 = 0,
109 SDW_BLK_GRP_CNT_2 = 1,
110 SDW_BLK_GRP_CNT_3 = 2,
111 SDW_BLK_GRP_CNT_4 = 3,
112 };
113
114 /**
115 * enum sdw_stream_type: data stream type
116 *
117 * @SDW_STREAM_PCM: PCM data stream
118 * @SDW_STREAM_PDM: PDM data stream
119 *
120 * spec doesn't define this, but is used in implementation
121 */
122 enum sdw_stream_type {
123 SDW_STREAM_PCM = 0,
124 SDW_STREAM_PDM = 1,
125 };
126
127 /**
128 * enum sdw_data_direction: Data direction
129 *
130 * @SDW_DATA_DIR_RX: Data into Port
131 * @SDW_DATA_DIR_TX: Data out of Port
132 */
133 enum sdw_data_direction {
134 SDW_DATA_DIR_RX = 0,
135 SDW_DATA_DIR_TX = 1,
136 };
137
138 /**
139 * enum sdw_port_data_mode: Data Port mode
140 *
141 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
142 * and transmitted.
143 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
144 * logic 1. The encoding will result in signal transitions at every bitslot
145 * owned by this Port
146 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
147 * logic 0. The encoding will result in no signal transitions
148 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
149 * a pseudo random data pattern that is transferred
150 */
151 enum sdw_port_data_mode {
152 SDW_PORT_DATA_MODE_NORMAL = 0,
153 SDW_PORT_DATA_MODE_STATIC_1 = 1,
154 SDW_PORT_DATA_MODE_STATIC_0 = 2,
155 SDW_PORT_DATA_MODE_PRBS = 3,
156 };
157
158 /*
159 * SDW properties, defined in MIPI DisCo spec v1.0
160 */
161 enum sdw_clk_stop_reset_behave {
162 SDW_CLK_STOP_KEEP_STATUS = 1,
163 };
164
165 /**
166 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
167 * read
168 * @SDW_P15_READ_IGNORED: Read is ignored
169 * @SDW_P15_CMD_OK: Command is ok
170 */
171 enum sdw_p15_behave {
172 SDW_P15_READ_IGNORED = 0,
173 SDW_P15_CMD_OK = 1,
174 };
175
176 /**
177 * enum sdw_dpn_type - Data port types
178 * @SDW_DPN_FULL: Full Data Port is supported
179 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
180 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
181 * are not implemented.
182 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
183 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
184 */
185 enum sdw_dpn_type {
186 SDW_DPN_FULL = 0,
187 SDW_DPN_SIMPLE = 1,
188 SDW_DPN_REDUCED = 2,
189 };
190
191 /**
192 * enum sdw_clk_stop_mode - Clock Stop modes
193 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
194 * restart
195 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
196 * not capable of continuing operation seamlessly when the clock restarts
197 */
198 enum sdw_clk_stop_mode {
199 SDW_CLK_STOP_MODE0 = 0,
200 SDW_CLK_STOP_MODE1 = 1,
201 };
202
203 /**
204 * struct sdw_dp0_prop - DP0 properties
205 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
206 * (inclusive)
207 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
208 * (inclusive)
209 * @num_words: number of wordlengths supported
210 * @words: wordlengths supported
211 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
212 * response
213 * @simple_ch_prep_sm: If channel prepare sequence is required
214 * @imp_def_interrupts: If set, each bit corresponds to support for
215 * implementation-defined interrupts
216 *
217 * The wordlengths are specified by Spec as max, min AND number of
218 * discrete values, implementation can define based on the wordlengths they
219 * support
220 */
221 struct sdw_dp0_prop {
222 u32 max_word;
223 u32 min_word;
224 u32 num_words;
225 u32 *words;
226 bool BRA_flow_controlled;
227 bool simple_ch_prep_sm;
228 bool imp_def_interrupts;
229 };
230
231 /**
232 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
233 * @bus_min_freq: Minimum bus frequency, in Hz
234 * @bus_max_freq: Maximum bus frequency, in Hz
235 * @bus_num_freq: Number of discrete frequencies supported
236 * @bus_freq: Discrete bus frequencies, in Hz
237 * @min_freq: Minimum sampling frequency, in Hz
238 * @max_freq: Maximum sampling bus frequency, in Hz
239 * @num_freq: Number of discrete sampling frequency supported
240 * @freq: Discrete sampling frequencies, in Hz
241 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
242 * sequence and bus clock configuration
243 * If 0, Channel Prepare can happen at any Bus clock rate
244 * If 1, Channel Prepare sequence shall happen only after Bus clock is
245 * changed to a frequency supported by this mode or compatible modes
246 * described by the next field
247 * @glitchless: Bitmap describing possible glitchless transitions from this
248 * Audio Mode to other Audio Modes
249 */
250 struct sdw_dpn_audio_mode {
251 u32 bus_min_freq;
252 u32 bus_max_freq;
253 u32 bus_num_freq;
254 u32 *bus_freq;
255 u32 max_freq;
256 u32 min_freq;
257 u32 num_freq;
258 u32 *freq;
259 u32 prep_ch_behave;
260 u32 glitchless;
261 };
262
263 /**
264 * struct sdw_dpn_prop - Data Port DPn properties
265 * @num: port number
266 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
267 * (inclusive)
268 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
269 * (inclusive)
270 * @num_words: Number of discrete supported wordlengths
271 * @words: Discrete supported wordlength
272 * @type: Data port type. Full, Simplified or Reduced
273 * @max_grouping: Maximum number of samples that can be grouped together for
274 * a full data port
275 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
276 * machine
277 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
278 * @imp_def_interrupts: If set, each bit corresponds to support for
279 * implementation-defined interrupts
280 * @max_ch: Maximum channels supported
281 * @min_ch: Minimum channels supported
282 * @num_ch: Number of discrete channels supported
283 * @ch: Discrete channels supported
284 * @num_ch_combinations: Number of channel combinations supported
285 * @ch_combinations: Channel combinations supported
286 * @modes: SDW mode supported
287 * @max_async_buffer: Number of samples that this port can buffer in
288 * asynchronous modes
289 * @block_pack_mode: Type of block port mode supported
290 * @port_encoding: Payload Channel Sample encoding schemes supported
291 * @audio_modes: Audio modes supported
292 */
293 struct sdw_dpn_prop {
294 u32 num;
295 u32 max_word;
296 u32 min_word;
297 u32 num_words;
298 u32 *words;
299 enum sdw_dpn_type type;
300 u32 max_grouping;
301 bool simple_ch_prep_sm;
302 u32 ch_prep_timeout;
303 u32 imp_def_interrupts;
304 u32 max_ch;
305 u32 min_ch;
306 u32 num_ch;
307 u32 *ch;
308 u32 num_ch_combinations;
309 u32 *ch_combinations;
310 u32 modes;
311 u32 max_async_buffer;
312 bool block_pack_mode;
313 u32 port_encoding;
314 struct sdw_dpn_audio_mode *audio_modes;
315 };
316
317 /**
318 * struct sdw_slave_prop - SoundWire Slave properties
319 * @mipi_revision: Spec version of the implementation
320 * @wake_capable: Wake-up events are supported
321 * @test_mode_capable: If test mode is supported
322 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
323 * @simple_clk_stop_capable: Simple clock mode is supported
324 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
325 * Machine transitions, in milliseconds
326 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
327 * transitions, in milliseconds
328 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
329 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
330 * @high_PHY_capable: Slave is HighPHY capable
331 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
332 * SCP_AddrPage2
333 * @bank_delay_support: Slave implements bank delay/bridge support registers
334 * SCP_BankDelay and SCP_NextFrame
335 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
336 * alias
337 * @lane_control_support: Slave supports lane control
338 * @master_count: Number of Masters present on this Slave
339 * @source_ports: Bitmap identifying source ports
340 * @sink_ports: Bitmap identifying sink ports
341 * @dp0_prop: Data Port 0 properties
342 * @src_dpn_prop: Source Data Port N properties
343 * @sink_dpn_prop: Sink Data Port N properties
344 */
345 struct sdw_slave_prop {
346 u32 mipi_revision;
347 bool wake_capable;
348 bool test_mode_capable;
349 bool clk_stop_mode1;
350 bool simple_clk_stop_capable;
351 u32 clk_stop_timeout;
352 u32 ch_prep_timeout;
353 enum sdw_clk_stop_reset_behave reset_behave;
354 bool high_PHY_capable;
355 bool paging_support;
356 bool bank_delay_support;
357 enum sdw_p15_behave p15_behave;
358 bool lane_control_support;
359 u32 master_count;
360 u32 source_ports;
361 u32 sink_ports;
362 struct sdw_dp0_prop *dp0_prop;
363 struct sdw_dpn_prop *src_dpn_prop;
364 struct sdw_dpn_prop *sink_dpn_prop;
365 };
366
367 /**
368 * struct sdw_master_prop - Master properties
369 * @revision: MIPI spec version of the implementation
370 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
371 * @max_clk_freq: Maximum Bus clock frequency, in Hz
372 * @num_clk_gears: Number of clock gears supported
373 * @clk_gears: Clock gears supported
374 * @num_clk_freq: Number of clock frequencies supported, in Hz
375 * @clk_freq: Clock frequencies supported, in Hz
376 * @default_frame_rate: Controller default Frame rate, in Hz
377 * @default_row: Number of rows
378 * @default_col: Number of columns
379 * @dynamic_frame: Dynamic frame shape supported
380 * @err_threshold: Number of times that software may retry sending a single
381 * command
382 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
383 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
384 */
385 struct sdw_master_prop {
386 u32 revision;
387 u32 clk_stop_modes;
388 u32 max_clk_freq;
389 u32 num_clk_gears;
390 u32 *clk_gears;
391 u32 num_clk_freq;
392 u32 *clk_freq;
393 u32 default_frame_rate;
394 u32 default_row;
395 u32 default_col;
396 bool dynamic_frame;
397 u32 err_threshold;
398 u32 mclk_freq;
399 bool hw_disabled;
400 };
401
402 int sdw_master_read_prop(struct sdw_bus *bus);
403 int sdw_slave_read_prop(struct sdw_slave *slave);
404
405 /*
406 * SDW Slave Structures and APIs
407 */
408
409 /**
410 * struct sdw_slave_id - Slave ID
411 * @mfg_id: MIPI Manufacturer ID
412 * @part_id: Device Part ID
413 * @class_id: MIPI Class ID, unused now.
414 * Currently a placeholder in MIPI SoundWire Spec
415 * @unique_id: Device unique ID
416 * @sdw_version: SDW version implemented
417 *
418 * The order of the IDs here does not follow the DisCo spec definitions
419 */
420 struct sdw_slave_id {
421 __u16 mfg_id;
422 __u16 part_id;
423 __u8 class_id;
424 __u8 unique_id:4;
425 __u8 sdw_version:4;
426 };
427
428 /**
429 * struct sdw_slave_intr_status - Slave interrupt status
430 * @control_port: control port status
431 * @port: data port status
432 */
433 struct sdw_slave_intr_status {
434 u8 control_port;
435 u8 port[15];
436 };
437
438 /**
439 * sdw_reg_bank - SoundWire register banks
440 * @SDW_BANK0: Soundwire register bank 0
441 * @SDW_BANK1: Soundwire register bank 1
442 */
443 enum sdw_reg_bank {
444 SDW_BANK0,
445 SDW_BANK1,
446 };
447
448 /**
449 * struct sdw_bus_conf: Bus configuration
450 *
451 * @clk_freq: Clock frequency, in Hz
452 * @num_rows: Number of rows in frame
453 * @num_cols: Number of columns in frame
454 * @bank: Next register bank
455 */
456 struct sdw_bus_conf {
457 unsigned int clk_freq;
458 unsigned int num_rows;
459 unsigned int num_cols;
460 unsigned int bank;
461 };
462
463 /**
464 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
465 *
466 * @num: Port number
467 * @ch_mask: Active channel mask
468 * @prepare: Prepare (true) /de-prepare (false) channel
469 * @bank: Register bank, which bank Slave/Master driver should program for
470 * implementation defined registers. This is always updated to next_bank
471 * value read from bus params.
472 *
473 */
474 struct sdw_prepare_ch {
475 unsigned int num;
476 unsigned int ch_mask;
477 bool prepare;
478 unsigned int bank;
479 };
480
481 /**
482 * enum sdw_port_prep_ops: Prepare operations for Data Port
483 *
484 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
485 * @SDW_OPS_PORT_PREP: Prepare operation for the Port
486 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
487 */
488 enum sdw_port_prep_ops {
489 SDW_OPS_PORT_PRE_PREP = 0,
490 SDW_OPS_PORT_PREP = 1,
491 SDW_OPS_PORT_POST_PREP = 2,
492 };
493
494 /**
495 * struct sdw_bus_params: Structure holding bus configuration
496 *
497 * @curr_bank: Current bank in use (BANK0/BANK1)
498 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
499 * set to !curr_bank
500 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
501 * @curr_dr_freq: Current double rate clock frequency, in Hz
502 * @bandwidth: Current bandwidth
503 * @col: Active columns
504 * @row: Active rows
505 */
506 struct sdw_bus_params {
507 enum sdw_reg_bank curr_bank;
508 enum sdw_reg_bank next_bank;
509 unsigned int max_dr_freq;
510 unsigned int curr_dr_freq;
511 unsigned int bandwidth;
512 unsigned int col;
513 unsigned int row;
514 };
515
516 /**
517 * struct sdw_slave_ops: Slave driver callback ops
518 *
519 * @read_prop: Read Slave properties
520 * @interrupt_callback: Device interrupt notification (invoked in thread
521 * context)
522 * @update_status: Update Slave status
523 * @bus_config: Update the bus config for Slave
524 * @port_prep: Prepare the port with parameters
525 */
526 struct sdw_slave_ops {
527 int (*read_prop)(struct sdw_slave *sdw);
528 int (*interrupt_callback)(struct sdw_slave *slave,
529 struct sdw_slave_intr_status *status);
530 int (*update_status)(struct sdw_slave *slave,
531 enum sdw_slave_status status);
532 int (*bus_config)(struct sdw_slave *slave,
533 struct sdw_bus_params *params);
534 int (*port_prep)(struct sdw_slave *slave,
535 struct sdw_prepare_ch *prepare_ch,
536 enum sdw_port_prep_ops pre_ops);
537 };
538
539 /**
540 * struct sdw_slave - SoundWire Slave
541 * @id: MIPI device ID
542 * @dev: Linux device
543 * @status: Status reported by the Slave
544 * @bus: Bus handle
545 * @ops: Slave callback ops
546 * @prop: Slave properties
547 * @debugfs: Slave debugfs
548 * @node: node for bus list
549 * @port_ready: Port ready completion flag for each Slave port
550 * @dev_num: Device Number assigned by Bus
551 */
552 struct sdw_slave {
553 struct sdw_slave_id id;
554 struct device dev;
555 enum sdw_slave_status status;
556 struct sdw_bus *bus;
557 const struct sdw_slave_ops *ops;
558 struct sdw_slave_prop prop;
559 #ifdef CONFIG_DEBUG_FS
560 struct dentry *debugfs;
561 #endif
562 struct list_head node;
563 struct completion *port_ready;
564 u16 dev_num;
565 };
566
567 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
568
569 struct sdw_driver {
570 const char *name;
571
572 int (*probe)(struct sdw_slave *sdw,
573 const struct sdw_device_id *id);
574 int (*remove)(struct sdw_slave *sdw);
575 void (*shutdown)(struct sdw_slave *sdw);
576
577 const struct sdw_device_id *id_table;
578 const struct sdw_slave_ops *ops;
579
580 struct device_driver driver;
581 };
582
583 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
584 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
585 .driver_data = (unsigned long)(_drv_data) }
586
587 int sdw_handle_slave_status(struct sdw_bus *bus,
588 enum sdw_slave_status status[]);
589
590 /*
591 * SDW master structures and APIs
592 */
593
594 /**
595 * struct sdw_port_params: Data Port parameters
596 *
597 * @num: Port number
598 * @bps: Word length of the Port
599 * @flow_mode: Port Data flow mode
600 * @data_mode: Test modes or normal mode
601 *
602 * This is used to program the Data Port based on Data Port stream
603 * parameters.
604 */
605 struct sdw_port_params {
606 unsigned int num;
607 unsigned int bps;
608 unsigned int flow_mode;
609 unsigned int data_mode;
610 };
611
612 /**
613 * struct sdw_transport_params: Data Port Transport Parameters
614 *
615 * @blk_grp_ctrl_valid: Port implements block group control
616 * @num: Port number
617 * @blk_grp_ctrl: Block group control value
618 * @sample_interval: Sample interval
619 * @offset1: Blockoffset of the payload data
620 * @offset2: Blockoffset of the payload data
621 * @hstart: Horizontal start of the payload data
622 * @hstop: Horizontal stop of the payload data
623 * @blk_pkg_mode: Block per channel or block per port
624 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
625 * data lane is supported in bus
626 *
627 * This is used to program the Data Port based on Data Port transport
628 * parameters. All these parameters are banked and can be modified
629 * during a bank switch without any artifacts in audio stream.
630 */
631 struct sdw_transport_params {
632 bool blk_grp_ctrl_valid;
633 unsigned int port_num;
634 unsigned int blk_grp_ctrl;
635 unsigned int sample_interval;
636 unsigned int offset1;
637 unsigned int offset2;
638 unsigned int hstart;
639 unsigned int hstop;
640 unsigned int blk_pkg_mode;
641 unsigned int lane_ctrl;
642 };
643
644 /**
645 * struct sdw_enable_ch: Enable/disable Data Port channel
646 *
647 * @num: Port number
648 * @ch_mask: Active channel mask
649 * @enable: Enable (true) /disable (false) channel
650 */
651 struct sdw_enable_ch {
652 unsigned int port_num;
653 unsigned int ch_mask;
654 bool enable;
655 };
656
657 /**
658 * struct sdw_master_port_ops: Callback functions from bus to Master
659 * driver to set Master Data ports.
660 *
661 * @dpn_set_port_params: Set the Port parameters for the Master Port.
662 * Mandatory callback
663 * @dpn_set_port_transport_params: Set transport parameters for the Master
664 * Port. Mandatory callback
665 * @dpn_port_prep: Port prepare operations for the Master Data Port.
666 * @dpn_port_enable_ch: Enable the channels of Master Port.
667 */
668 struct sdw_master_port_ops {
669 int (*dpn_set_port_params)(struct sdw_bus *bus,
670 struct sdw_port_params *port_params,
671 unsigned int bank);
672 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
673 struct sdw_transport_params *transport_params,
674 enum sdw_reg_bank bank);
675 int (*dpn_port_prep)(struct sdw_bus *bus,
676 struct sdw_prepare_ch *prepare_ch);
677 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
678 struct sdw_enable_ch *enable_ch, unsigned int bank);
679 };
680
681 struct sdw_msg;
682
683 /**
684 * struct sdw_defer - SDW deffered message
685 * @length: message length
686 * @complete: message completion
687 * @msg: SDW message
688 */
689 struct sdw_defer {
690 int length;
691 struct completion complete;
692 struct sdw_msg *msg;
693 };
694
695 /**
696 * struct sdw_master_ops - Master driver ops
697 * @read_prop: Read Master properties
698 * @xfer_msg: Transfer message callback
699 * @xfer_msg_defer: Defer version of transfer message callback
700 * @reset_page_addr: Reset the SCP page address registers
701 * @set_bus_conf: Set the bus configuration
702 * @pre_bank_switch: Callback for pre bank switch
703 * @post_bank_switch: Callback for post bank switch
704 */
705 struct sdw_master_ops {
706 int (*read_prop)(struct sdw_bus *bus);
707
708 enum sdw_command_response (*xfer_msg)
709 (struct sdw_bus *bus, struct sdw_msg *msg);
710 enum sdw_command_response (*xfer_msg_defer)
711 (struct sdw_bus *bus, struct sdw_msg *msg,
712 struct sdw_defer *defer);
713 enum sdw_command_response (*reset_page_addr)
714 (struct sdw_bus *bus, unsigned int dev_num);
715 int (*set_bus_conf)(struct sdw_bus *bus,
716 struct sdw_bus_params *params);
717 int (*pre_bank_switch)(struct sdw_bus *bus);
718 int (*post_bank_switch)(struct sdw_bus *bus);
719
720 };
721
722 /**
723 * struct sdw_bus - SoundWire bus
724 * @dev: Master linux device
725 * @link_id: Link id number, can be 0 to N, unique for each Master
726 * @slaves: list of Slaves on this bus
727 * @assigned: Bitmap for Slave device numbers.
728 * Bit set implies used number, bit clear implies unused number.
729 * @bus_lock: bus lock
730 * @msg_lock: message lock
731 * @compute_params: points to Bus resource management implementation
732 * @ops: Master callback ops
733 * @port_ops: Master port callback ops
734 * @params: Current bus parameters
735 * @prop: Master properties
736 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
737 * is used to compute and program bus bandwidth, clock, frame shape,
738 * transport and port parameters
739 * @debugfs: Bus debugfs
740 * @defer_msg: Defer message
741 * @clk_stop_timeout: Clock stop timeout computed
742 * @bank_switch_timeout: Bank switch timeout computed
743 * @multi_link: Store bus property that indicates if multi links
744 * are supported. This flag is populated by drivers after reading
745 * appropriate firmware (ACPI/DT).
746 */
747 struct sdw_bus {
748 struct device *dev;
749 unsigned int link_id;
750 struct list_head slaves;
751 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
752 struct mutex bus_lock;
753 struct mutex msg_lock;
754 int (*compute_params)(struct sdw_bus *bus);
755 const struct sdw_master_ops *ops;
756 const struct sdw_master_port_ops *port_ops;
757 struct sdw_bus_params params;
758 struct sdw_master_prop prop;
759 struct list_head m_rt_list;
760 #ifdef CONFIG_DEBUG_FS
761 struct dentry *debugfs;
762 #endif
763 struct sdw_defer defer_msg;
764 unsigned int clk_stop_timeout;
765 u32 bank_switch_timeout;
766 bool multi_link;
767 };
768
769 int sdw_add_bus_master(struct sdw_bus *bus);
770 void sdw_delete_bus_master(struct sdw_bus *bus);
771
772 /**
773 * sdw_port_config: Master or Slave Port configuration
774 *
775 * @num: Port number
776 * @ch_mask: channels mask for port
777 */
778 struct sdw_port_config {
779 unsigned int num;
780 unsigned int ch_mask;
781 };
782
783 /**
784 * sdw_stream_config: Master or Slave stream configuration
785 *
786 * @frame_rate: Audio frame rate of the stream, in Hz
787 * @ch_count: Channel count of the stream
788 * @bps: Number of bits per audio sample
789 * @direction: Data direction
790 * @type: Stream type PCM or PDM
791 */
792 struct sdw_stream_config {
793 unsigned int frame_rate;
794 unsigned int ch_count;
795 unsigned int bps;
796 enum sdw_data_direction direction;
797 enum sdw_stream_type type;
798 };
799
800 /**
801 * sdw_stream_state: Stream states
802 *
803 * @SDW_STREAM_ALLOCATED: New stream allocated.
804 * @SDW_STREAM_CONFIGURED: Stream configured
805 * @SDW_STREAM_PREPARED: Stream prepared
806 * @SDW_STREAM_ENABLED: Stream enabled
807 * @SDW_STREAM_DISABLED: Stream disabled
808 * @SDW_STREAM_DEPREPARED: Stream de-prepared
809 * @SDW_STREAM_RELEASED: Stream released
810 */
811 enum sdw_stream_state {
812 SDW_STREAM_ALLOCATED = 0,
813 SDW_STREAM_CONFIGURED = 1,
814 SDW_STREAM_PREPARED = 2,
815 SDW_STREAM_ENABLED = 3,
816 SDW_STREAM_DISABLED = 4,
817 SDW_STREAM_DEPREPARED = 5,
818 SDW_STREAM_RELEASED = 6,
819 };
820
821 /**
822 * sdw_stream_params: Stream parameters
823 *
824 * @rate: Sampling frequency, in Hz
825 * @ch_count: Number of channels
826 * @bps: bits per channel sample
827 */
828 struct sdw_stream_params {
829 unsigned int rate;
830 unsigned int ch_count;
831 unsigned int bps;
832 };
833
834 /**
835 * sdw_stream_runtime: Runtime stream parameters
836 *
837 * @name: SoundWire stream name
838 * @params: Stream parameters
839 * @state: Current state of the stream
840 * @type: Stream type PCM or PDM
841 * @master_list: List of Master runtime(s) in this stream.
842 * master_list can contain only one m_rt per Master instance
843 * for a stream
844 * @m_rt_count: Count of Master runtime(s) in this stream
845 */
846 struct sdw_stream_runtime {
847 const char *name;
848 struct sdw_stream_params params;
849 enum sdw_stream_state state;
850 enum sdw_stream_type type;
851 struct list_head master_list;
852 int m_rt_count;
853 };
854
855 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
856 void sdw_release_stream(struct sdw_stream_runtime *stream);
857 int sdw_stream_add_master(struct sdw_bus *bus,
858 struct sdw_stream_config *stream_config,
859 struct sdw_port_config *port_config,
860 unsigned int num_ports,
861 struct sdw_stream_runtime *stream);
862 int sdw_stream_add_slave(struct sdw_slave *slave,
863 struct sdw_stream_config *stream_config,
864 struct sdw_port_config *port_config,
865 unsigned int num_ports,
866 struct sdw_stream_runtime *stream);
867 int sdw_stream_remove_master(struct sdw_bus *bus,
868 struct sdw_stream_runtime *stream);
869 int sdw_stream_remove_slave(struct sdw_slave *slave,
870 struct sdw_stream_runtime *stream);
871 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
872 int sdw_enable_stream(struct sdw_stream_runtime *stream);
873 int sdw_disable_stream(struct sdw_stream_runtime *stream);
874 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
875
876 /* messaging and data APIs */
877
878 int sdw_read(struct sdw_slave *slave, u32 addr);
879 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
880 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
881 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
882
883 #endif /* __SOUNDWIRE_H */