This source file includes following definitions.
- nand_get_sdr_timings
- nand_op_trace
- nand_controller_init
- mtd_to_nand
- nand_to_mtd
- nand_get_controller_data
- nand_set_controller_data
- nand_set_manufacturer_data
- nand_get_manufacturer_data
- nand_set_flash_node
- nand_get_flash_node
- nand_is_slc
- nand_opcode_8bits
- nand_scan
- nand_get_data_buf
1
2
3
4
5
6
7
8
9
10
11
12
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/flashchip.h>
18 #include <linux/mtd/bbm.h>
19 #include <linux/mtd/jedec.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/onfi.h>
22 #include <linux/mutex.h>
23 #include <linux/of.h>
24 #include <linux/types.h>
25
26 struct nand_chip;
27
28
29 #define NAND_MAX_CHIPS 8
30
31
32
33
34
35
36
37
38 #define NAND_NCE 0x01
39
40 #define NAND_CLE 0x02
41
42 #define NAND_ALE 0x04
43
44 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
45 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
46 #define NAND_CTRL_CHANGE 0x80
47
48
49
50
51 #define NAND_CMD_READ0 0
52 #define NAND_CMD_READ1 1
53 #define NAND_CMD_RNDOUT 5
54 #define NAND_CMD_PAGEPROG 0x10
55 #define NAND_CMD_READOOB 0x50
56 #define NAND_CMD_ERASE1 0x60
57 #define NAND_CMD_STATUS 0x70
58 #define NAND_CMD_SEQIN 0x80
59 #define NAND_CMD_RNDIN 0x85
60 #define NAND_CMD_READID 0x90
61 #define NAND_CMD_ERASE2 0xd0
62 #define NAND_CMD_PARAM 0xec
63 #define NAND_CMD_GET_FEATURES 0xee
64 #define NAND_CMD_SET_FEATURES 0xef
65 #define NAND_CMD_RESET 0xff
66
67
68 #define NAND_CMD_READSTART 0x30
69 #define NAND_CMD_RNDOUTSTART 0xE0
70 #define NAND_CMD_CACHEDPROG 0x15
71
72 #define NAND_CMD_NONE -1
73
74
75 #define NAND_STATUS_FAIL 0x01
76 #define NAND_STATUS_FAIL_N1 0x02
77 #define NAND_STATUS_TRUE_READY 0x20
78 #define NAND_STATUS_READY 0x40
79 #define NAND_STATUS_WP 0x80
80
81 #define NAND_DATA_IFACE_CHECK_ONLY -1
82
83
84
85
86 typedef enum {
87 NAND_ECC_NONE,
88 NAND_ECC_SOFT,
89 NAND_ECC_HW,
90 NAND_ECC_HW_SYNDROME,
91 NAND_ECC_HW_OOB_FIRST,
92 NAND_ECC_ON_DIE,
93 } nand_ecc_modes_t;
94
95 enum nand_ecc_algo {
96 NAND_ECC_UNKNOWN,
97 NAND_ECC_HAMMING,
98 NAND_ECC_BCH,
99 NAND_ECC_RS,
100 };
101
102
103
104
105
106 #define NAND_ECC_READ 0
107
108 #define NAND_ECC_WRITE 1
109
110 #define NAND_ECC_READSYN 2
111
112
113
114
115
116
117
118 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
119 #define NAND_ECC_MAXIMIZE BIT(1)
120
121
122
123
124
125 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
126
127
128
129
130
131
132 #define NAND_BUSWIDTH_16 0x00000002
133
134 #define NAND_CACHEPRG 0x00000008
135
136
137
138
139
140 #define NAND_NEED_READRDY 0x00000100
141
142
143 #define NAND_NO_SUBPAGE_WRITE 0x00000200
144
145
146 #define NAND_BROKEN_XD 0x00000400
147
148
149 #define NAND_ROM 0x00000800
150
151
152 #define NAND_SUBPAGE_READ 0x00001000
153
154
155
156
157
158 #define NAND_NEED_SCRAMBLING 0x00002000
159
160
161 #define NAND_ROW_ADDR_3 0x00004000
162
163
164 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
165
166
167 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
168
169
170
171
172
173
174
175
176 #define NAND_BBM_FIRSTPAGE 0x01000000
177 #define NAND_BBM_SECONDPAGE 0x02000000
178 #define NAND_BBM_LASTPAGE 0x04000000
179
180
181 #define NAND_BBM_POS_SMALL 5
182 #define NAND_BBM_POS_LARGE 0
183
184
185
186 #define NAND_SKIP_BBTSCAN 0x00010000
187
188 #define NAND_SCAN_SILENT_NODEV 0x00040000
189
190
191
192
193
194
195 #define NAND_BUSWIDTH_AUTO 0x00080000
196
197
198
199
200 #define NAND_USE_BOUNCE_BUFFER 0x00100000
201
202
203
204
205
206
207
208
209
210 #define NAND_WAIT_TCCS 0x00200000
211
212
213
214
215
216 #define NAND_IS_BOOT_MEDIUM 0x00400000
217
218
219
220
221
222
223 #define NAND_KEEP_TIMINGS 0x00800000
224
225
226 #define NAND_CI_CHIPNR_MSK 0x03
227 #define NAND_CI_CELLTYPE_MSK 0x0C
228 #define NAND_CI_CELLTYPE_SHIFT 2
229
230
231
232
233
234
235
236
237
238 struct nand_parameters {
239
240 const char *model;
241 bool supports_set_get_features;
242 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
243 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
244
245
246 struct onfi_params *onfi;
247 };
248
249
250 #define NAND_MAX_ID_LEN 8
251
252
253
254
255
256
257 struct nand_id {
258 u8 data[NAND_MAX_ID_LEN];
259 int len;
260 };
261
262
263
264
265
266
267
268 struct nand_ecc_step_info {
269 int stepsize;
270 const int *strengths;
271 int nstrengths;
272 };
273
274
275
276
277
278
279
280 struct nand_ecc_caps {
281 const struct nand_ecc_step_info *stepinfos;
282 int nstepinfos;
283 int (*calc_ecc_bytes)(int step_size, int strength);
284 };
285
286
287 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
288 static const int __name##_strengths[] = { __VA_ARGS__ }; \
289 static const struct nand_ecc_step_info __name##_stepinfo = { \
290 .stepsize = __step, \
291 .strengths = __name##_strengths, \
292 .nstrengths = ARRAY_SIZE(__name##_strengths), \
293 }; \
294 static const struct nand_ecc_caps __name = { \
295 .stepinfos = &__name##_stepinfo, \
296 .nstepinfos = 1, \
297 .calc_ecc_bytes = __calc, \
298 }
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353 struct nand_ecc_ctrl {
354 nand_ecc_modes_t mode;
355 enum nand_ecc_algo algo;
356 int steps;
357 int size;
358 int bytes;
359 int total;
360 int strength;
361 int prepad;
362 int postpad;
363 unsigned int options;
364 void *priv;
365 u8 *calc_buf;
366 u8 *code_buf;
367 void (*hwctl)(struct nand_chip *chip, int mode);
368 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
369 uint8_t *ecc_code);
370 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
371 uint8_t *calc_ecc);
372 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
373 int oob_required, int page);
374 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
375 int oob_required, int page);
376 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
377 int oob_required, int page);
378 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
379 uint32_t len, uint8_t *buf, int page);
380 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
381 uint32_t data_len, const uint8_t *data_buf,
382 int oob_required, int page);
383 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
384 int oob_required, int page);
385 int (*write_oob_raw)(struct nand_chip *chip, int page);
386 int (*read_oob_raw)(struct nand_chip *chip, int page);
387 int (*read_oob)(struct nand_chip *chip, int page);
388 int (*write_oob)(struct nand_chip *chip, int page);
389 };
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442 struct nand_sdr_timings {
443 u64 tBERS_max;
444 u32 tCCS_min;
445 u64 tPROG_max;
446 u64 tR_max;
447 u32 tALH_min;
448 u32 tADL_min;
449 u32 tALS_min;
450 u32 tAR_min;
451 u32 tCEA_max;
452 u32 tCEH_min;
453 u32 tCH_min;
454 u32 tCHZ_max;
455 u32 tCLH_min;
456 u32 tCLR_min;
457 u32 tCLS_min;
458 u32 tCOH_min;
459 u32 tCS_min;
460 u32 tDH_min;
461 u32 tDS_min;
462 u32 tFEAT_max;
463 u32 tIR_min;
464 u32 tITC_max;
465 u32 tRC_min;
466 u32 tREA_max;
467 u32 tREH_min;
468 u32 tRHOH_min;
469 u32 tRHW_min;
470 u32 tRHZ_max;
471 u32 tRLOH_min;
472 u32 tRP_min;
473 u32 tRR_min;
474 u64 tRST_max;
475 u32 tWB_max;
476 u32 tWC_min;
477 u32 tWH_min;
478 u32 tWHR_min;
479 u32 tWP_min;
480 u32 tWW_min;
481 };
482
483
484
485
486
487 enum nand_data_interface_type {
488 NAND_SDR_IFACE,
489 };
490
491
492
493
494
495
496
497 struct nand_data_interface {
498 enum nand_data_interface_type type;
499 union {
500 struct nand_sdr_timings sdr;
501 } timings;
502 };
503
504
505
506
507
508 static inline const struct nand_sdr_timings *
509 nand_get_sdr_timings(const struct nand_data_interface *conf)
510 {
511 if (conf->type != NAND_SDR_IFACE)
512 return ERR_PTR(-EINVAL);
513
514 return &conf->timings.sdr;
515 }
516
517
518
519
520
521 struct nand_op_cmd_instr {
522 u8 opcode;
523 };
524
525
526
527
528
529
530 struct nand_op_addr_instr {
531 unsigned int naddrs;
532 const u8 *addrs;
533 };
534
535
536
537
538
539
540
541
542
543
544
545
546
547 struct nand_op_data_instr {
548 unsigned int len;
549 union {
550 void *in;
551 const void *out;
552 } buf;
553 bool force_8bit;
554 };
555
556
557
558
559
560 struct nand_op_waitrdy_instr {
561 unsigned int timeout_ms;
562 };
563
564
565
566
567
568
569
570
571
572 enum nand_op_instr_type {
573 NAND_OP_CMD_INSTR,
574 NAND_OP_ADDR_INSTR,
575 NAND_OP_DATA_IN_INSTR,
576 NAND_OP_DATA_OUT_INSTR,
577 NAND_OP_WAITRDY_INSTR,
578 };
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595 struct nand_op_instr {
596 enum nand_op_instr_type type;
597 union {
598 struct nand_op_cmd_instr cmd;
599 struct nand_op_addr_instr addr;
600 struct nand_op_data_instr data;
601 struct nand_op_waitrdy_instr waitrdy;
602 } ctx;
603 unsigned int delay_ns;
604 };
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619 #define __DIVIDE(dividend, divisor) ({ \
620 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
621 DIV_ROUND_UP(dividend, divisor) : \
622 DIV_ROUND_UP_ULL(dividend, divisor)); \
623 })
624 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
625 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
626
627 #define NAND_OP_CMD(id, ns) \
628 { \
629 .type = NAND_OP_CMD_INSTR, \
630 .ctx.cmd.opcode = id, \
631 .delay_ns = ns, \
632 }
633
634 #define NAND_OP_ADDR(ncycles, cycles, ns) \
635 { \
636 .type = NAND_OP_ADDR_INSTR, \
637 .ctx.addr = { \
638 .naddrs = ncycles, \
639 .addrs = cycles, \
640 }, \
641 .delay_ns = ns, \
642 }
643
644 #define NAND_OP_DATA_IN(l, b, ns) \
645 { \
646 .type = NAND_OP_DATA_IN_INSTR, \
647 .ctx.data = { \
648 .len = l, \
649 .buf.in = b, \
650 .force_8bit = false, \
651 }, \
652 .delay_ns = ns, \
653 }
654
655 #define NAND_OP_DATA_OUT(l, b, ns) \
656 { \
657 .type = NAND_OP_DATA_OUT_INSTR, \
658 .ctx.data = { \
659 .len = l, \
660 .buf.out = b, \
661 .force_8bit = false, \
662 }, \
663 .delay_ns = ns, \
664 }
665
666 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
667 { \
668 .type = NAND_OP_DATA_IN_INSTR, \
669 .ctx.data = { \
670 .len = l, \
671 .buf.in = b, \
672 .force_8bit = true, \
673 }, \
674 .delay_ns = ns, \
675 }
676
677 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
678 { \
679 .type = NAND_OP_DATA_OUT_INSTR, \
680 .ctx.data = { \
681 .len = l, \
682 .buf.out = b, \
683 .force_8bit = true, \
684 }, \
685 .delay_ns = ns, \
686 }
687
688 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
689 { \
690 .type = NAND_OP_WAITRDY_INSTR, \
691 .ctx.waitrdy.timeout_ms = tout_ms, \
692 .delay_ns = ns, \
693 }
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711 struct nand_subop {
712 const struct nand_op_instr *instrs;
713 unsigned int ninstrs;
714 unsigned int first_instr_start_off;
715 unsigned int last_instr_end_off;
716 };
717
718 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
719 unsigned int op_id);
720 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
721 unsigned int op_id);
722 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
723 unsigned int op_id);
724 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
725 unsigned int op_id);
726
727
728
729
730
731
732 struct nand_op_parser_addr_constraints {
733 unsigned int maxcycles;
734 };
735
736
737
738
739
740 struct nand_op_parser_data_constraints {
741 unsigned int maxlen;
742 };
743
744
745
746
747
748
749
750
751
752 struct nand_op_parser_pattern_elem {
753 enum nand_op_instr_type type;
754 bool optional;
755 union {
756 struct nand_op_parser_addr_constraints addr;
757 struct nand_op_parser_data_constraints data;
758 } ctx;
759 };
760
761 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
762 { \
763 .type = NAND_OP_CMD_INSTR, \
764 .optional = _opt, \
765 }
766
767 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
768 { \
769 .type = NAND_OP_ADDR_INSTR, \
770 .optional = _opt, \
771 .ctx.addr.maxcycles = _maxcycles, \
772 }
773
774 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
775 { \
776 .type = NAND_OP_DATA_IN_INSTR, \
777 .optional = _opt, \
778 .ctx.data.maxlen = _maxlen, \
779 }
780
781 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
782 { \
783 .type = NAND_OP_DATA_OUT_INSTR, \
784 .optional = _opt, \
785 .ctx.data.maxlen = _maxlen, \
786 }
787
788 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
789 { \
790 .type = NAND_OP_WAITRDY_INSTR, \
791 .optional = _opt, \
792 }
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812 struct nand_op_parser_pattern {
813 const struct nand_op_parser_pattern_elem *elems;
814 unsigned int nelems;
815 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
816 };
817
818 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
819 { \
820 .exec = _exec, \
821 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
822 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
823 sizeof(struct nand_op_parser_pattern_elem), \
824 }
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840 struct nand_op_parser {
841 const struct nand_op_parser_pattern *patterns;
842 unsigned int npatterns;
843 };
844
845 #define NAND_OP_PARSER(...) \
846 { \
847 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
848 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
849 sizeof(struct nand_op_parser_pattern), \
850 }
851
852
853
854
855
856
857
858
859
860 struct nand_operation {
861 unsigned int cs;
862 const struct nand_op_instr *instrs;
863 unsigned int ninstrs;
864 };
865
866 #define NAND_OPERATION(_cs, _instrs) \
867 { \
868 .cs = _cs, \
869 .instrs = _instrs, \
870 .ninstrs = ARRAY_SIZE(_instrs), \
871 }
872
873 int nand_op_parser_exec_op(struct nand_chip *chip,
874 const struct nand_op_parser *parser,
875 const struct nand_operation *op, bool check_only);
876
877 static inline void nand_op_trace(const char *prefix,
878 const struct nand_op_instr *instr)
879 {
880 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
881 switch (instr->type) {
882 case NAND_OP_CMD_INSTR:
883 pr_debug("%sCMD [0x%02x]\n", prefix,
884 instr->ctx.cmd.opcode);
885 break;
886 case NAND_OP_ADDR_INSTR:
887 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
888 instr->ctx.addr.naddrs,
889 instr->ctx.addr.naddrs < 64 ?
890 instr->ctx.addr.naddrs : 64,
891 instr->ctx.addr.addrs);
892 break;
893 case NAND_OP_DATA_IN_INSTR:
894 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
895 instr->ctx.data.len,
896 instr->ctx.data.force_8bit ?
897 ", force 8-bit" : "");
898 break;
899 case NAND_OP_DATA_OUT_INSTR:
900 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
901 instr->ctx.data.len,
902 instr->ctx.data.force_8bit ?
903 ", force 8-bit" : "");
904 break;
905 case NAND_OP_WAITRDY_INSTR:
906 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
907 instr->ctx.waitrdy.timeout_ms);
908 break;
909 }
910 #endif
911 }
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936 struct nand_controller_ops {
937 int (*attach_chip)(struct nand_chip *chip);
938 void (*detach_chip)(struct nand_chip *chip);
939 int (*exec_op)(struct nand_chip *chip,
940 const struct nand_operation *op,
941 bool check_only);
942 int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
943 const struct nand_data_interface *conf);
944 };
945
946
947
948
949
950
951
952 struct nand_controller {
953 struct mutex lock;
954 const struct nand_controller_ops *ops;
955 };
956
957 static inline void nand_controller_init(struct nand_controller *nfc)
958 {
959 mutex_init(&nfc->lock);
960 }
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990 struct nand_legacy {
991 void __iomem *IO_ADDR_R;
992 void __iomem *IO_ADDR_W;
993 void (*select_chip)(struct nand_chip *chip, int cs);
994 u8 (*read_byte)(struct nand_chip *chip);
995 void (*write_byte)(struct nand_chip *chip, u8 byte);
996 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
997 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
998 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
999 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1000 int page_addr);
1001 int (*dev_ready)(struct nand_chip *chip);
1002 int (*waitfunc)(struct nand_chip *chip);
1003 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1004 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1005 int (*set_features)(struct nand_chip *chip, int feature_addr,
1006 u8 *subfeature_para);
1007 int (*get_features)(struct nand_chip *chip, int feature_addr,
1008 u8 *subfeature_para);
1009 int chip_delay;
1010 struct nand_controller dummy_controller;
1011 };
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082 struct nand_chip {
1083 struct nand_device base;
1084
1085 struct nand_legacy legacy;
1086
1087 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1088
1089 unsigned int options;
1090 unsigned int bbt_options;
1091
1092 int page_shift;
1093 int phys_erase_shift;
1094 int bbt_erase_shift;
1095 int chip_shift;
1096 int pagemask;
1097 u8 *data_buf;
1098
1099 struct {
1100 unsigned int bitflips;
1101 int page;
1102 } pagecache;
1103
1104 int subpagesize;
1105 int onfi_timing_mode_default;
1106 unsigned int badblockpos;
1107 int badblockbits;
1108
1109 struct nand_id id;
1110 struct nand_parameters parameters;
1111
1112 struct nand_data_interface data_interface;
1113
1114 int cur_cs;
1115
1116 int read_retries;
1117
1118 struct mutex lock;
1119 unsigned int suspended : 1;
1120
1121 uint8_t *oob_poi;
1122 struct nand_controller *controller;
1123
1124 struct nand_ecc_ctrl ecc;
1125 unsigned long buf_align;
1126
1127 uint8_t *bbt;
1128 struct nand_bbt_descr *bbt_td;
1129 struct nand_bbt_descr *bbt_md;
1130
1131 struct nand_bbt_descr *badblock_pattern;
1132
1133 void *priv;
1134
1135 struct {
1136 const struct nand_manufacturer *desc;
1137 void *priv;
1138 } manufacturer;
1139 };
1140
1141 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1142 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1143
1144 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1145 {
1146 return container_of(mtd, struct nand_chip, base.mtd);
1147 }
1148
1149 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1150 {
1151 return &chip->base.mtd;
1152 }
1153
1154 static inline void *nand_get_controller_data(struct nand_chip *chip)
1155 {
1156 return chip->priv;
1157 }
1158
1159 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1160 {
1161 chip->priv = priv;
1162 }
1163
1164 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1165 void *priv)
1166 {
1167 chip->manufacturer.priv = priv;
1168 }
1169
1170 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1171 {
1172 return chip->manufacturer.priv;
1173 }
1174
1175 static inline void nand_set_flash_node(struct nand_chip *chip,
1176 struct device_node *np)
1177 {
1178 mtd_set_of_node(nand_to_mtd(chip), np);
1179 }
1180
1181 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1182 {
1183 return mtd_get_of_node(nand_to_mtd(chip));
1184 }
1185
1186
1187
1188
1189
1190
1191 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1192 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1193 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1206 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1207 .options = (opts) }
1208
1209 #define NAND_ECC_INFO(_strength, _step) \
1210 { .strength_ds = (_strength), .step_ds = (_step) }
1211 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1212 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243 struct nand_flash_dev {
1244 char *name;
1245 union {
1246 struct {
1247 uint8_t mfr_id;
1248 uint8_t dev_id;
1249 };
1250 uint8_t id[NAND_MAX_ID_LEN];
1251 };
1252 unsigned int pagesize;
1253 unsigned int chipsize;
1254 unsigned int erasesize;
1255 unsigned int options;
1256 uint16_t id_len;
1257 uint16_t oobsize;
1258 struct {
1259 uint16_t strength_ds;
1260 uint16_t step_ds;
1261 } ecc;
1262 int onfi_timing_mode_default;
1263 };
1264
1265 int nand_create_bbt(struct nand_chip *chip);
1266
1267
1268
1269
1270
1271
1272 static inline bool nand_is_slc(struct nand_chip *chip)
1273 {
1274 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1275 "chip->bits_per_cell is used uninitialized\n");
1276 return nanddev_bits_per_cell(&chip->base) == 1;
1277 }
1278
1279
1280
1281
1282
1283 static inline int nand_opcode_8bits(unsigned int command)
1284 {
1285 switch (command) {
1286 case NAND_CMD_READID:
1287 case NAND_CMD_PARAM:
1288 case NAND_CMD_GET_FEATURES:
1289 case NAND_CMD_SET_FEATURES:
1290 return 1;
1291 default:
1292 break;
1293 }
1294 return 0;
1295 }
1296
1297 int nand_check_erased_ecc_chunk(void *data, int datalen,
1298 void *ecc, int ecclen,
1299 void *extraoob, int extraooblen,
1300 int threshold);
1301
1302 int nand_ecc_choose_conf(struct nand_chip *chip,
1303 const struct nand_ecc_caps *caps, int oobavail);
1304
1305
1306 int nand_write_oob_std(struct nand_chip *chip, int page);
1307
1308
1309 int nand_read_oob_std(struct nand_chip *chip, int page);
1310
1311
1312 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1313 u8 *subfeature_param);
1314
1315
1316 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1317 int page);
1318
1319
1320 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1321 int oob_required, int page);
1322
1323
1324 int nand_reset(struct nand_chip *chip, int chipnr);
1325
1326
1327 int nand_reset_op(struct nand_chip *chip);
1328 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1329 unsigned int len);
1330 int nand_status_op(struct nand_chip *chip, u8 *status);
1331 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1332 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1333 unsigned int offset_in_page, void *buf, unsigned int len);
1334 int nand_change_read_column_op(struct nand_chip *chip,
1335 unsigned int offset_in_page, void *buf,
1336 unsigned int len, bool force_8bit);
1337 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1338 unsigned int offset_in_page, void *buf, unsigned int len);
1339 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1340 unsigned int offset_in_page, const void *buf,
1341 unsigned int len);
1342 int nand_prog_page_end_op(struct nand_chip *chip);
1343 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1344 unsigned int offset_in_page, const void *buf,
1345 unsigned int len);
1346 int nand_change_write_column_op(struct nand_chip *chip,
1347 unsigned int offset_in_page, const void *buf,
1348 unsigned int len, bool force_8bit);
1349 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1350 bool force_8bit);
1351 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1352 unsigned int len, bool force_8bit);
1353
1354
1355 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1356 struct nand_flash_dev *ids);
1357
1358 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1359 {
1360 return nand_scan_with_ids(chip, max_chips, NULL);
1361 }
1362
1363
1364 void nand_wait_ready(struct nand_chip *chip);
1365
1366
1367
1368
1369
1370 void nand_cleanup(struct nand_chip *chip);
1371
1372 void nand_release(struct nand_chip *chip);
1373
1374
1375
1376
1377
1378 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1379 struct gpio_desc;
1380 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1381 unsigned long timeout_ms);
1382
1383
1384 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1385 void nand_deselect_target(struct nand_chip *chip);
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401 static inline void *nand_get_data_buf(struct nand_chip *chip)
1402 {
1403 chip->pagecache.page = -1;
1404
1405 return chip->data_buf;
1406 }
1407
1408 #endif