include/linux/dmaengine.h

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This source file includes following definitions.
dma_submit_error
dma_chan_name
dma_set_unmap
dma_set_unmap
dmaengine_get_unmap_data
dmaengine_unmap_put
dma_descriptor_unmap
txd_lock
txd_unlock
txd_chain
txd_clear_parent
txd_clear_next
txd_next
txd_parent
txd_lock
txd_unlock
txd_chain
txd_clear_parent
txd_clear_next
txd_parent
txd_next
dmaengine_slave_config
is_slave_direction
dmaengine_prep_slave_single
dmaengine_prep_slave_sg
dmaengine_prep_rio_sg
dmaengine_prep_dma_cyclic
dmaengine_prep_interleaved_dma
dmaengine_prep_dma_memset
dmaengine_prep_dma_memcpy
dmaengine_terminate_all
dmaengine_terminate_async
dmaengine_synchronize
dmaengine_terminate_sync
dmaengine_pause
dmaengine_resume
dmaengine_tx_status
dmaengine_submit
dmaengine_check_align
is_dma_copy_aligned
is_dma_xor_aligned
is_dma_pq_aligned
is_dma_fill_aligned
dma_set_maxpq
dmaf_continue
dmaf_p_disabled_continue
dma_dev_has_pq_continue
dma_dev_to_maxpq
dma_maxpq
dmaengine_get_icg
dmaengine_get_dst_icg
dmaengine_get_src_icg
dmaengine_get
dmaengine_put
async_dmaengine_get
async_dmaengine_put
async_dma_find_channel
async_tx_ack
async_tx_clear_ack
async_tx_test_ack
__dma_cap_set
__dma_cap_clear
__dma_cap_zero
__dma_has_cap
dma_async_issue_pending
dma_async_is_tx_complete
dma_async_is_complete
dma_set_tx_state
dma_find_channel
dma_sync_wait
dma_wait_for_async_tx
dma_issue_pending_all
__dma_request_channel
dma_request_slave_channel
dma_request_chan
dma_request_chan_by_mask
dma_release_channel
dma_get_slave_caps
dmaengine_desc_set_reuse
dmaengine_desc_clear_reuse
dmaengine_desc_test_reuse
dmaengine_desc_free
__dma_request_slave_channel_compat
   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
   4  */
   5 #ifndef LINUX_DMAENGINE_H
   6 #define LINUX_DMAENGINE_H
   7 
   8 #include <linux/device.h>
   9 #include <linux/err.h>
  10 #include <linux/uio.h>
  11 #include <linux/bug.h>
  12 #include <linux/scatterlist.h>
  13 #include <linux/bitmap.h>
  14 #include <linux/types.h>
  15 #include <asm/page.h>
  16 
  17 /**
  18  * typedef dma_cookie_t - an opaque DMA cookie
  19  *
  20  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  21  */
  22 typedef s32 dma_cookie_t;
  23 #define DMA_MIN_COOKIE  1
  24 
  25 static inline int dma_submit_error(dma_cookie_t cookie)
  26 {
  27         return cookie < 0 ? cookie : 0;
  28 }
  29 
  30 /**
  31  * enum dma_status - DMA transaction status
  32  * @DMA_COMPLETE: transaction completed
  33  * @DMA_IN_PROGRESS: transaction not yet processed
  34  * @DMA_PAUSED: transaction is paused
  35  * @DMA_ERROR: transaction failed
  36  */
  37 enum dma_status {
  38         DMA_COMPLETE,
  39         DMA_IN_PROGRESS,
  40         DMA_PAUSED,
  41         DMA_ERROR,
  42 };
  43 
  44 /**
  45  * enum dma_transaction_type - DMA transaction types/indexes
  46  *
  47  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
  48  * automatically set as dma devices are registered.
  49  */
  50 enum dma_transaction_type {
  51         DMA_MEMCPY,
  52         DMA_XOR,
  53         DMA_PQ,
  54         DMA_XOR_VAL,
  55         DMA_PQ_VAL,
  56         DMA_MEMSET,
  57         DMA_MEMSET_SG,
  58         DMA_INTERRUPT,
  59         DMA_PRIVATE,
  60         DMA_ASYNC_TX,
  61         DMA_SLAVE,
  62         DMA_CYCLIC,
  63         DMA_INTERLEAVE,
  64 /* last transaction type for creation of the capabilities mask */
  65         DMA_TX_TYPE_END,
  66 };
  67 
  68 /**
  69  * enum dma_transfer_direction - dma transfer mode and direction indicator
  70  * @DMA_MEM_TO_MEM: Async/Memcpy mode
  71  * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
  72  * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
  73  * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
  74  */
  75 enum dma_transfer_direction {
  76         DMA_MEM_TO_MEM,
  77         DMA_MEM_TO_DEV,
  78         DMA_DEV_TO_MEM,
  79         DMA_DEV_TO_DEV,
  80         DMA_TRANS_NONE,
  81 };
  82 
  83 /**
  84  * Interleaved Transfer Request
  85  * ----------------------------
  86  * A chunk is collection of contiguous bytes to be transfered.
  87  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
  88  * ICGs may or maynot change between chunks.
  89  * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
  90  *  that when repeated an integral number of times, specifies the transfer.
  91  * A transfer template is specification of a Frame, the number of times
  92  *  it is to be repeated and other per-transfer attributes.
  93  *
  94  * Practically, a client driver would have ready a template for each
  95  *  type of transfer it is going to need during its lifetime and
  96  *  set only 'src_start' and 'dst_start' before submitting the requests.
  97  *
  98  *
  99  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
 100  *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
 101  *
 102  *    ==  Chunk size
 103  *    ... ICG
 104  */
 105 
 106 /**
 107  * struct data_chunk - Element of scatter-gather list that makes a frame.
 108  * @size: Number of bytes to read from source.
 109  *        size_dst := fn(op, size_src), so doesn't mean much for destination.
 110  * @icg: Number of bytes to jump after last src/dst address of this
 111  *       chunk and before first src/dst address for next chunk.
 112  *       Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
 113  *       Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
 114  * @dst_icg: Number of bytes to jump after last dst address of this
 115  *       chunk and before the first dst address for next chunk.
 116  *       Ignored if dst_inc is true and dst_sgl is false.
 117  * @src_icg: Number of bytes to jump after last src address of this
 118  *       chunk and before the first src address for next chunk.
 119  *       Ignored if src_inc is true and src_sgl is false.
 120  */
 121 struct data_chunk {
 122         size_t size;
 123         size_t icg;
 124         size_t dst_icg;
 125         size_t src_icg;
 126 };
 127 
 128 /**
 129  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
 130  *       and attributes.
 131  * @src_start: Bus address of source for the first chunk.
 132  * @dst_start: Bus address of destination for the first chunk.
 133  * @dir: Specifies the type of Source and Destination.
 134  * @src_inc: If the source address increments after reading from it.
 135  * @dst_inc: If the destination address increments after writing to it.
 136  * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
 137  *              Otherwise, source is read contiguously (icg ignored).
 138  *              Ignored if src_inc is false.
 139  * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
 140  *              Otherwise, destination is filled contiguously (icg ignored).
 141  *              Ignored if dst_inc is false.
 142  * @numf: Number of frames in this template.
 143  * @frame_size: Number of chunks in a frame i.e, size of sgl[].
 144  * @sgl: Array of {chunk,icg} pairs that make up a frame.
 145  */
 146 struct dma_interleaved_template {
 147         dma_addr_t src_start;
 148         dma_addr_t dst_start;
 149         enum dma_transfer_direction dir;
 150         bool src_inc;
 151         bool dst_inc;
 152         bool src_sgl;
 153         bool dst_sgl;
 154         size_t numf;
 155         size_t frame_size;
 156         struct data_chunk sgl[0];
 157 };
 158 
 159 /**
 160  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
 161  *  control completion, and communicate status.
 162  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
 163  *  this transaction
 164  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
 165  *  acknowledges receipt, i.e. has has a chance to establish any dependency
 166  *  chains
 167  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
 168  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
 169  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
 170  *  sources that were the result of a previous operation, in the case of a PQ
 171  *  operation it continues the calculation with new sources
 172  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
 173  *  on the result of this operation
 174  * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
 175  *  cleared or freed
 176  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
 177  *  data and the descriptor should be in different format from normal
 178  *  data descriptors.
 179  */
 180 enum dma_ctrl_flags {
 181         DMA_PREP_INTERRUPT = (1 << 0),
 182         DMA_CTRL_ACK = (1 << 1),
 183         DMA_PREP_PQ_DISABLE_P = (1 << 2),
 184         DMA_PREP_PQ_DISABLE_Q = (1 << 3),
 185         DMA_PREP_CONTINUE = (1 << 4),
 186         DMA_PREP_FENCE = (1 << 5),
 187         DMA_CTRL_REUSE = (1 << 6),
 188         DMA_PREP_CMD = (1 << 7),
 189 };
 190 
 191 /**
 192  * enum sum_check_bits - bit position of pq_check_flags
 193  */
 194 enum sum_check_bits {
 195         SUM_CHECK_P = 0,
 196         SUM_CHECK_Q = 1,
 197 };
 198 
 199 /**
 200  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 201  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 202  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 203  */
 204 enum sum_check_flags {
 205         SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
 206         SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
 207 };
 208 
 209 
 210 /**
 211  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 212  * See linux/cpumask.h
 213  */
 214 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
 215 
 216 /**
 217  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 218  * @memcpy_count: transaction counter
 219  * @bytes_transferred: byte counter
 220  */
 221 
 222 struct dma_chan_percpu {
 223         /* stats */
 224         unsigned long memcpy_count;
 225         unsigned long bytes_transferred;
 226 };
 227 
 228 /**
 229  * struct dma_router - DMA router structure
 230  * @dev: pointer to the DMA router device
 231  * @route_free: function to be called when the route can be disconnected
 232  */
 233 struct dma_router {
 234         struct device *dev;
 235         void (*route_free)(struct device *dev, void *route_data);
 236 };
 237 
 238 /**
 239  * struct dma_chan - devices supply DMA channels, clients use them
 240  * @device: ptr to the dma device who supplies this channel, always !%NULL
 241  * @cookie: last cookie value returned to client
 242  * @completed_cookie: last completed cookie for this channel
 243  * @chan_id: channel ID for sysfs
 244  * @dev: class device for sysfs
 245  * @device_node: used to add this to the device chan list
 246  * @local: per-cpu pointer to a struct dma_chan_percpu
 247  * @client_count: how many clients are using this channel
 248  * @table_count: number of appearances in the mem-to-mem allocation table
 249  * @router: pointer to the DMA router structure
 250  * @route_data: channel specific data for the router
 251  * @private: private data for certain client-channel associations
 252  */
 253 struct dma_chan {
 254         struct dma_device *device;
 255         dma_cookie_t cookie;
 256         dma_cookie_t completed_cookie;
 257 
 258         /* sysfs */
 259         int chan_id;
 260         struct dma_chan_dev *dev;
 261 
 262         struct list_head device_node;
 263         struct dma_chan_percpu __percpu *local;
 264         int client_count;
 265         int table_count;
 266 
 267         /* DMA router */
 268         struct dma_router *router;
 269         void *route_data;
 270 
 271         void *private;
 272 };
 273 
 274 /**
 275  * struct dma_chan_dev - relate sysfs device node to backing channel device
 276  * @chan: driver channel device
 277  * @device: sysfs device
 278  * @dev_id: parent dma_device dev_id
 279  * @idr_ref: reference count to gate release of dma_device dev_id
 280  */
 281 struct dma_chan_dev {
 282         struct dma_chan *chan;
 283         struct device device;
 284         int dev_id;
 285         atomic_t *idr_ref;
 286 };
 287 
 288 /**
 289  * enum dma_slave_buswidth - defines bus width of the DMA slave
 290  * device, source or target buses
 291  */
 292 enum dma_slave_buswidth {
 293         DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
 294         DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
 295         DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
 296         DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
 297         DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
 298         DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
 299         DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
 300         DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
 301         DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
 302 };
 303 
 304 /**
 305  * struct dma_slave_config - dma slave channel runtime config
 306  * @direction: whether the data shall go in or out on this slave
 307  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
 308  * legal values. DEPRECATED, drivers should use the direction argument
 309  * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
 310  * the dir field in the dma_interleaved_template structure.
 311  * @src_addr: this is the physical address where DMA slave data
 312  * should be read (RX), if the source is memory this argument is
 313  * ignored.
 314  * @dst_addr: this is the physical address where DMA slave data
 315  * should be written (TX), if the source is memory this argument
 316  * is ignored.
 317  * @src_addr_width: this is the width in bytes of the source (RX)
 318  * register where DMA data shall be read. If the source
 319  * is memory this may be ignored depending on architecture.
 320  * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
 321  * @dst_addr_width: same as src_addr_width but for destination
 322  * target (TX) mutatis mutandis.
 323  * @src_maxburst: the maximum number of words (note: words, as in
 324  * units of the src_addr_width member, not bytes) that can be sent
 325  * in one burst to the device. Typically something like half the
 326  * FIFO depth on I/O peripherals so you don't overflow it. This
 327  * may or may not be applicable on memory sources.
 328  * @dst_maxburst: same as src_maxburst but for destination target
 329  * mutatis mutandis.
 330  * @src_port_window_size: The length of the register area in words the data need
 331  * to be accessed on the device side. It is only used for devices which is using
 332  * an area instead of a single register to receive the data. Typically the DMA
 333  * loops in this area in order to transfer the data.
 334  * @dst_port_window_size: same as src_port_window_size but for the destination
 335  * port.
 336  * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
 337  * with 'true' if peripheral should be flow controller. Direction will be
 338  * selected at Runtime.
 339  * @slave_id: Slave requester id. Only valid for slave channels. The dma
 340  * slave peripheral will have unique id as dma requester which need to be
 341  * pass as slave config.
 342  *
 343  * This struct is passed in as configuration data to a DMA engine
 344  * in order to set up a certain channel for DMA transport at runtime.
 345  * The DMA device/engine has to provide support for an additional
 346  * callback in the dma_device structure, device_config and this struct
 347  * will then be passed in as an argument to the function.
 348  *
 349  * The rationale for adding configuration information to this struct is as
 350  * follows: if it is likely that more than one DMA slave controllers in
 351  * the world will support the configuration option, then make it generic.
 352  * If not: if it is fixed so that it be sent in static from the platform
 353  * data, then prefer to do that.
 354  */
 355 struct dma_slave_config {
 356         enum dma_transfer_direction direction;
 357         phys_addr_t src_addr;
 358         phys_addr_t dst_addr;
 359         enum dma_slave_buswidth src_addr_width;
 360         enum dma_slave_buswidth dst_addr_width;
 361         u32 src_maxburst;
 362         u32 dst_maxburst;
 363         u32 src_port_window_size;
 364         u32 dst_port_window_size;
 365         bool device_fc;
 366         unsigned int slave_id;
 367 };
 368 
 369 /**
 370  * enum dma_residue_granularity - Granularity of the reported transfer residue
 371  * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
 372  *  DMA channel is only able to tell whether a descriptor has been completed or
 373  *  not, which means residue reporting is not supported by this channel. The
 374  *  residue field of the dma_tx_state field will always be 0.
 375  * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
 376  *  completed segment of the transfer (For cyclic transfers this is after each
 377  *  period). This is typically implemented by having the hardware generate an
 378  *  interrupt after each transferred segment and then the drivers updates the
 379  *  outstanding residue by the size of the segment. Another possibility is if
 380  *  the hardware supports scatter-gather and the segment descriptor has a field
 381  *  which gets set after the segment has been completed. The driver then counts
 382  *  the number of segments without the flag set to compute the residue.
 383  * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
 384  *  burst. This is typically only supported if the hardware has a progress
 385  *  register of some sort (E.g. a register with the current read/write address
 386  *  or a register with the amount of bursts/beats/bytes that have been
 387  *  transferred or still need to be transferred).
 388  */
 389 enum dma_residue_granularity {
 390         DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
 391         DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
 392         DMA_RESIDUE_GRANULARITY_BURST = 2,
 393 };
 394 
 395 /**
 396  * struct dma_slave_caps - expose capabilities of a slave channel only
 397  * @src_addr_widths: bit mask of src addr widths the channel supports.
 398  *      Width is specified in bytes, e.g. for a channel supporting
 399  *      a width of 4 the mask should have BIT(4) set.
 400  * @dst_addr_widths: bit mask of dst addr widths the channel supports
 401  * @directions: bit mask of slave directions the channel supports.
 402  *      Since the enum dma_transfer_direction is not defined as bit flag for
 403  *      each type, the dma controller should set BIT(<TYPE>) and same
 404  *      should be checked by controller as well
 405  * @max_burst: max burst capability per-transfer
 406  * @cmd_pause: true, if pause is supported (i.e. for reading residue or
 407  *             for resume later)
 408  * @cmd_resume: true, if resume is supported
 409  * @cmd_terminate: true, if terminate cmd is supported
 410  * @residue_granularity: granularity of the reported transfer residue
 411  * @descriptor_reuse: if a descriptor can be reused by client and
 412  * resubmitted multiple times
 413  */
 414 struct dma_slave_caps {
 415         u32 src_addr_widths;
 416         u32 dst_addr_widths;
 417         u32 directions;
 418         u32 max_burst;
 419         bool cmd_pause;
 420         bool cmd_resume;
 421         bool cmd_terminate;
 422         enum dma_residue_granularity residue_granularity;
 423         bool descriptor_reuse;
 424 };
 425 
 426 static inline const char *dma_chan_name(struct dma_chan *chan)
 427 {
 428         return dev_name(&chan->dev->device);
 429 }
 430 
 431 void dma_chan_cleanup(struct kref *kref);
 432 
 433 /**
 434  * typedef dma_filter_fn - callback filter for dma_request_channel
 435  * @chan: channel to be reviewed
 436  * @filter_param: opaque parameter passed through dma_request_channel
 437  *
 438  * When this optional parameter is specified in a call to dma_request_channel a
 439  * suitable channel is passed to this routine for further dispositioning before
 440  * being returned.  Where 'suitable' indicates a non-busy channel that
 441  * satisfies the given capability mask.  It returns 'true' to indicate that the
 442  * channel is suitable.
 443  */
 444 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
 445 
 446 typedef void (*dma_async_tx_callback)(void *dma_async_param);
 447 
 448 enum dmaengine_tx_result {
 449         DMA_TRANS_NOERROR = 0,          /* SUCCESS */
 450         DMA_TRANS_READ_FAILED,          /* Source DMA read failed */
 451         DMA_TRANS_WRITE_FAILED,         /* Destination DMA write failed */
 452         DMA_TRANS_ABORTED,              /* Op never submitted / aborted */
 453 };
 454 
 455 struct dmaengine_result {
 456         enum dmaengine_tx_result result;
 457         u32 residue;
 458 };
 459 
 460 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
 461                                 const struct dmaengine_result *result);
 462 
 463 struct dmaengine_unmap_data {
 464 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
 465         u16 map_cnt;
 466 #else
 467         u8 map_cnt;
 468 #endif
 469         u8 to_cnt;
 470         u8 from_cnt;
 471         u8 bidi_cnt;
 472         struct device *dev;
 473         struct kref kref;
 474         size_t len;
 475         dma_addr_t addr[0];
 476 };
 477 
 478 /**
 479  * struct dma_async_tx_descriptor - async transaction descriptor
 480  * ---dma generic offload fields---
 481  * @cookie: tracking cookie for this transaction, set to -EBUSY if
 482  *      this tx is sitting on a dependency list
 483  * @flags: flags to augment operation preparation, control completion, and
 484  *      communicate status
 485  * @phys: physical address of the descriptor
 486  * @chan: target channel for this operation
 487  * @tx_submit: accept the descriptor, assign ordered cookie and mark the
 488  * descriptor pending. To be pushed on .issue_pending() call
 489  * @callback: routine to call after this operation is complete
 490  * @callback_param: general parameter to pass to the callback routine
 491  * ---async_tx api specific fields---
 492  * @next: at completion submit this descriptor
 493  * @parent: pointer to the next level up in the dependency chain
 494  * @lock: protect the parent and next pointers
 495  */
 496 struct dma_async_tx_descriptor {
 497         dma_cookie_t cookie;
 498         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
 499         dma_addr_t phys;
 500         struct dma_chan *chan;
 501         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
 502         int (*desc_free)(struct dma_async_tx_descriptor *tx);
 503         dma_async_tx_callback callback;
 504         dma_async_tx_callback_result callback_result;
 505         void *callback_param;
 506         struct dmaengine_unmap_data *unmap;
 507 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
 508         struct dma_async_tx_descriptor *next;
 509         struct dma_async_tx_descriptor *parent;
 510         spinlock_t lock;
 511 #endif
 512 };
 513 
 514 #ifdef CONFIG_DMA_ENGINE
 515 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
 516                                  struct dmaengine_unmap_data *unmap)
 517 {
 518         kref_get(&unmap->kref);
 519         tx->unmap = unmap;
 520 }
 521 
 522 struct dmaengine_unmap_data *
 523 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
 524 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
 525 #else
 526 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
 527                                  struct dmaengine_unmap_data *unmap)
 528 {
 529 }
 530 static inline struct dmaengine_unmap_data *
 531 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
 532 {
 533         return NULL;
 534 }
 535 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
 536 {
 537 }
 538 #endif
 539 
 540 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
 541 {
 542         if (tx->unmap) {
 543                 dmaengine_unmap_put(tx->unmap);
 544                 tx->unmap = NULL;
 545         }
 546 }
 547 
 548 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
 549 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
 550 {
 551 }
 552 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
 553 {
 554 }
 555 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
 556 {
 557         BUG();
 558 }
 559 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
 560 {
 561 }
 562 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
 563 {
 564 }
 565 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
 566 {
 567         return NULL;
 568 }
 569 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
 570 {
 571         return NULL;
 572 }
 573 
 574 #else
 575 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
 576 {
 577         spin_lock_bh(&txd->lock);
 578 }
 579 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
 580 {
 581         spin_unlock_bh(&txd->lock);
 582 }
 583 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
 584 {
 585         txd->next = next;
 586         next->parent = txd;
 587 }
 588 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
 589 {
 590         txd->parent = NULL;
 591 }
 592 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
 593 {
 594         txd->next = NULL;
 595 }
 596 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
 597 {
 598         return txd->parent;
 599 }
 600 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
 601 {
 602         return txd->next;
 603 }
 604 #endif
 605 
 606 /**
 607  * struct dma_tx_state - filled in to report the status of
 608  * a transfer.
 609  * @last: last completed DMA cookie
 610  * @used: last issued DMA cookie (i.e. the one in progress)
 611  * @residue: the remaining number of bytes left to transmit
 612  *      on the selected transfer for states DMA_IN_PROGRESS and
 613  *      DMA_PAUSED if this is implemented in the driver, else 0
 614  */
 615 struct dma_tx_state {
 616         dma_cookie_t last;
 617         dma_cookie_t used;
 618         u32 residue;
 619 };
 620 
 621 /**
 622  * enum dmaengine_alignment - defines alignment of the DMA async tx
 623  * buffers
 624  */
 625 enum dmaengine_alignment {
 626         DMAENGINE_ALIGN_1_BYTE = 0,
 627         DMAENGINE_ALIGN_2_BYTES = 1,
 628         DMAENGINE_ALIGN_4_BYTES = 2,
 629         DMAENGINE_ALIGN_8_BYTES = 3,
 630         DMAENGINE_ALIGN_16_BYTES = 4,
 631         DMAENGINE_ALIGN_32_BYTES = 5,
 632         DMAENGINE_ALIGN_64_BYTES = 6,
 633 };
 634 
 635 /**
 636  * struct dma_slave_map - associates slave device and it's slave channel with
 637  * parameter to be used by a filter function
 638  * @devname: name of the device
 639  * @slave: slave channel name
 640  * @param: opaque parameter to pass to struct dma_filter.fn
 641  */
 642 struct dma_slave_map {
 643         const char *devname;
 644         const char *slave;
 645         void *param;
 646 };
 647 
 648 /**
 649  * struct dma_filter - information for slave device/channel to filter_fn/param
 650  * mapping
 651  * @fn: filter function callback
 652  * @mapcnt: number of slave device/channel in the map
 653  * @map: array of channel to filter mapping data
 654  */
 655 struct dma_filter {
 656         dma_filter_fn fn;
 657         int mapcnt;
 658         const struct dma_slave_map *map;
 659 };
 660 
 661 /**
 662  * struct dma_device - info on the entity supplying DMA services
 663  * @chancnt: how many DMA channels are supported
 664  * @privatecnt: how many DMA channels are requested by dma_request_channel
 665  * @channels: the list of struct dma_chan
 666  * @global_node: list_head for global dma_device_list
 667  * @filter: information for device/slave to filter function/param mapping
 668  * @cap_mask: one or more dma_capability flags
 669  * @max_xor: maximum number of xor sources, 0 if no capability
 670  * @max_pq: maximum number of PQ sources and PQ-continue capability
 671  * @copy_align: alignment shift for memcpy operations
 672  * @xor_align: alignment shift for xor operations
 673  * @pq_align: alignment shift for pq operations
 674  * @fill_align: alignment shift for memset operations
 675  * @dev_id: unique device ID
 676  * @dev: struct device reference for dma mapping api
 677  * @owner: owner module (automatically set based on the provided dev)
 678  * @src_addr_widths: bit mask of src addr widths the device supports
 679  *      Width is specified in bytes, e.g. for a device supporting
 680  *      a width of 4 the mask should have BIT(4) set.
 681  * @dst_addr_widths: bit mask of dst addr widths the device supports
 682  * @directions: bit mask of slave directions the device supports.
 683  *      Since the enum dma_transfer_direction is not defined as bit flag for
 684  *      each type, the dma controller should set BIT(<TYPE>) and same
 685  *      should be checked by controller as well
 686  * @max_burst: max burst capability per-transfer
 687  * @residue_granularity: granularity of the transfer residue reported
 688  *      by tx_status
 689  * @device_alloc_chan_resources: allocate resources and return the
 690  *      number of allocated descriptors
 691  * @device_free_chan_resources: release DMA channel's resources
 692  * @device_prep_dma_memcpy: prepares a memcpy operation
 693  * @device_prep_dma_xor: prepares a xor operation
 694  * @device_prep_dma_xor_val: prepares a xor validation operation
 695  * @device_prep_dma_pq: prepares a pq operation
 696  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
 697  * @device_prep_dma_memset: prepares a memset operation
 698  * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
 699  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 700  * @device_prep_slave_sg: prepares a slave dma operation
 701  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
 702  *      The function takes a buffer of size buf_len. The callback function will
 703  *      be called after period_len bytes have been transferred.
 704  * @device_prep_interleaved_dma: Transfer expression in a generic way.
 705  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
 706  * @device_config: Pushes a new configuration to a channel, return 0 or an error
 707  *      code
 708  * @device_pause: Pauses any transfer happening on a channel. Returns
 709  *      0 or an error code
 710  * @device_resume: Resumes any transfer on a channel previously
 711  *      paused. Returns 0 or an error code
 712  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
 713  *      or an error code
 714  * @device_synchronize: Synchronizes the termination of a transfers to the
 715  *  current context.
 716  * @device_tx_status: poll for transaction completion, the optional
 717  *      txstate parameter can be supplied with a pointer to get a
 718  *      struct with auxiliary transfer status information, otherwise the call
 719  *      will just return a simple status code
 720  * @device_issue_pending: push pending transactions to hardware
 721  * @descriptor_reuse: a submitted transfer can be resubmitted after completion
 722  */
 723 struct dma_device {
 724 
 725         unsigned int chancnt;
 726         unsigned int privatecnt;
 727         struct list_head channels;
 728         struct list_head global_node;
 729         struct dma_filter filter;
 730         dma_cap_mask_t  cap_mask;
 731         unsigned short max_xor;
 732         unsigned short max_pq;
 733         enum dmaengine_alignment copy_align;
 734         enum dmaengine_alignment xor_align;
 735         enum dmaengine_alignment pq_align;
 736         enum dmaengine_alignment fill_align;
 737         #define DMA_HAS_PQ_CONTINUE (1 << 15)
 738 
 739         int dev_id;
 740         struct device *dev;
 741         struct module *owner;
 742 
 743         u32 src_addr_widths;
 744         u32 dst_addr_widths;
 745         u32 directions;
 746         u32 max_burst;
 747         bool descriptor_reuse;
 748         enum dma_residue_granularity residue_granularity;
 749 
 750         int (*device_alloc_chan_resources)(struct dma_chan *chan);
 751         void (*device_free_chan_resources)(struct dma_chan *chan);
 752 
 753         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
 754                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
 755                 size_t len, unsigned long flags);
 756         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
 757                 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
 758                 unsigned int src_cnt, size_t len, unsigned long flags);
 759         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
 760                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
 761                 size_t len, enum sum_check_flags *result, unsigned long flags);
 762         struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
 763                 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
 764                 unsigned int src_cnt, const unsigned char *scf,
 765                 size_t len, unsigned long flags);
 766         struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
 767                 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
 768                 unsigned int src_cnt, const unsigned char *scf, size_t len,
 769                 enum sum_check_flags *pqres, unsigned long flags);
 770         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
 771                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
 772                 unsigned long flags);
 773         struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
 774                 struct dma_chan *chan, struct scatterlist *sg,
 775                 unsigned int nents, int value, unsigned long flags);
 776         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
 777                 struct dma_chan *chan, unsigned long flags);
 778 
 779         struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 780                 struct dma_chan *chan, struct scatterlist *sgl,
 781                 unsigned int sg_len, enum dma_transfer_direction direction,
 782                 unsigned long flags, void *context);
 783         struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
 784                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 785                 size_t period_len, enum dma_transfer_direction direction,
 786                 unsigned long flags);
 787         struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
 788                 struct dma_chan *chan, struct dma_interleaved_template *xt,
 789                 unsigned long flags);
 790         struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
 791                 struct dma_chan *chan, dma_addr_t dst, u64 data,
 792                 unsigned long flags);
 793 
 794         int (*device_config)(struct dma_chan *chan,
 795                              struct dma_slave_config *config);
 796         int (*device_pause)(struct dma_chan *chan);
 797         int (*device_resume)(struct dma_chan *chan);
 798         int (*device_terminate_all)(struct dma_chan *chan);
 799         void (*device_synchronize)(struct dma_chan *chan);
 800 
 801         enum dma_status (*device_tx_status)(struct dma_chan *chan,
 802                                             dma_cookie_t cookie,
 803                                             struct dma_tx_state *txstate);
 804         void (*device_issue_pending)(struct dma_chan *chan);
 805 };
 806 
 807 static inline int dmaengine_slave_config(struct dma_chan *chan,
 808                                           struct dma_slave_config *config)
 809 {
 810         if (chan->device->device_config)
 811                 return chan->device->device_config(chan, config);
 812 
 813         return -ENOSYS;
 814 }
 815 
 816 static inline bool is_slave_direction(enum dma_transfer_direction direction)
 817 {
 818         return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
 819 }
 820 
 821 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
 822         struct dma_chan *chan, dma_addr_t buf, size_t len,
 823         enum dma_transfer_direction dir, unsigned long flags)
 824 {
 825         struct scatterlist sg;
 826         sg_init_table(&sg, 1);
 827         sg_dma_address(&sg) = buf;
 828         sg_dma_len(&sg) = len;
 829 
 830         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
 831                 return NULL;
 832 
 833         return chan->device->device_prep_slave_sg(chan, &sg, 1,
 834                                                   dir, flags, NULL);
 835 }
 836 
 837 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
 838         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 839         enum dma_transfer_direction dir, unsigned long flags)
 840 {
 841         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
 842                 return NULL;
 843 
 844         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
 845                                                   dir, flags, NULL);
 846 }
 847 
 848 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 849 struct rio_dma_ext;
 850 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
 851         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 852         enum dma_transfer_direction dir, unsigned long flags,
 853         struct rio_dma_ext *rio_ext)
 854 {
 855         if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
 856                 return NULL;
 857 
 858         return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
 859                                                   dir, flags, rio_ext);
 860 }
 861 #endif
 862 
 863 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
 864                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 865                 size_t period_len, enum dma_transfer_direction dir,
 866                 unsigned long flags)
 867 {
 868         if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
 869                 return NULL;
 870 
 871         return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
 872                                                 period_len, dir, flags);
 873 }
 874 
 875 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
 876                 struct dma_chan *chan, struct dma_interleaved_template *xt,
 877                 unsigned long flags)
 878 {
 879         if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
 880                 return NULL;
 881 
 882         return chan->device->device_prep_interleaved_dma(chan, xt, flags);
 883 }
 884 
 885 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
 886                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
 887                 unsigned long flags)
 888 {
 889         if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
 890                 return NULL;
 891 
 892         return chan->device->device_prep_dma_memset(chan, dest, value,
 893                                                     len, flags);
 894 }
 895 
 896 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
 897                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 898                 size_t len, unsigned long flags)
 899 {
 900         if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
 901                 return NULL;
 902 
 903         return chan->device->device_prep_dma_memcpy(chan, dest, src,
 904                                                     len, flags);
 905 }
 906 
 907 /**
 908  * dmaengine_terminate_all() - Terminate all active DMA transfers
 909  * @chan: The channel for which to terminate the transfers
 910  *
 911  * This function is DEPRECATED use either dmaengine_terminate_sync() or
 912  * dmaengine_terminate_async() instead.
 913  */
 914 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 915 {
 916         if (chan->device->device_terminate_all)
 917                 return chan->device->device_terminate_all(chan);
 918 
 919         return -ENOSYS;
 920 }
 921 
 922 /**
 923  * dmaengine_terminate_async() - Terminate all active DMA transfers
 924  * @chan: The channel for which to terminate the transfers
 925  *
 926  * Calling this function will terminate all active and pending descriptors
 927  * that have previously been submitted to the channel. It is not guaranteed
 928  * though that the transfer for the active descriptor has stopped when the
 929  * function returns. Furthermore it is possible the complete callback of a
 930  * submitted transfer is still running when this function returns.
 931  *
 932  * dmaengine_synchronize() needs to be called before it is safe to free
 933  * any memory that is accessed by previously submitted descriptors or before
 934  * freeing any resources accessed from within the completion callback of any
 935  * perviously submitted descriptors.
 936  *
 937  * This function can be called from atomic context as well as from within a
 938  * complete callback of a descriptor submitted on the same channel.
 939  *
 940  * If none of the two conditions above apply consider using
 941  * dmaengine_terminate_sync() instead.
 942  */
 943 static inline int dmaengine_terminate_async(struct dma_chan *chan)
 944 {
 945         if (chan->device->device_terminate_all)
 946                 return chan->device->device_terminate_all(chan);
 947 
 948         return -EINVAL;
 949 }
 950 
 951 /**
 952  * dmaengine_synchronize() - Synchronize DMA channel termination
 953  * @chan: The channel to synchronize
 954  *
 955  * Synchronizes to the DMA channel termination to the current context. When this
 956  * function returns it is guaranteed that all transfers for previously issued
 957  * descriptors have stopped and and it is safe to free the memory assoicated
 958  * with them. Furthermore it is guaranteed that all complete callback functions
 959  * for a previously submitted descriptor have finished running and it is safe to
 960  * free resources accessed from within the complete callbacks.
 961  *
 962  * The behavior of this function is undefined if dma_async_issue_pending() has
 963  * been called between dmaengine_terminate_async() and this function.
 964  *
 965  * This function must only be called from non-atomic context and must not be
 966  * called from within a complete callback of a descriptor submitted on the same
 967  * channel.
 968  */
 969 static inline void dmaengine_synchronize(struct dma_chan *chan)
 970 {
 971         might_sleep();
 972 
 973         if (chan->device->device_synchronize)
 974                 chan->device->device_synchronize(chan);
 975 }
 976 
 977 /**
 978  * dmaengine_terminate_sync() - Terminate all active DMA transfers
 979  * @chan: The channel for which to terminate the transfers
 980  *
 981  * Calling this function will terminate all active and pending transfers
 982  * that have previously been submitted to the channel. It is similar to
 983  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
 984  * stopped and that all complete callbacks have finished running when the
 985  * function returns.
 986  *
 987  * This function must only be called from non-atomic context and must not be
 988  * called from within a complete callback of a descriptor submitted on the same
 989  * channel.
 990  */
 991 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
 992 {
 993         int ret;
 994 
 995         ret = dmaengine_terminate_async(chan);
 996         if (ret)
 997                 return ret;
 998 
 999         dmaengine_synchronize(chan);
1000 
1001         return 0;
1002 }
1003 
1004 static inline int dmaengine_pause(struct dma_chan *chan)
1005 {
1006         if (chan->device->device_pause)
1007                 return chan->device->device_pause(chan);
1008 
1009         return -ENOSYS;
1010 }
1011 
1012 static inline int dmaengine_resume(struct dma_chan *chan)
1013 {
1014         if (chan->device->device_resume)
1015                 return chan->device->device_resume(chan);
1016 
1017         return -ENOSYS;
1018 }
1019 
1020 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1021         dma_cookie_t cookie, struct dma_tx_state *state)
1022 {
1023         return chan->device->device_tx_status(chan, cookie, state);
1024 }
1025 
1026 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1027 {
1028         return desc->tx_submit(desc);
1029 }
1030 
1031 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1032                                          size_t off1, size_t off2, size_t len)
1033 {
1034         size_t mask;
1035 
1036         if (!align)
1037                 return true;
1038         mask = (1 << align) - 1;
1039         if (mask & (off1 | off2 | len))
1040                 return false;
1041         return true;
1042 }
1043 
1044 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1045                                        size_t off2, size_t len)
1046 {
1047         return dmaengine_check_align(dev->copy_align, off1, off2, len);
1048 }
1049 
1050 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1051                                       size_t off2, size_t len)
1052 {
1053         return dmaengine_check_align(dev->xor_align, off1, off2, len);
1054 }
1055 
1056 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1057                                      size_t off2, size_t len)
1058 {
1059         return dmaengine_check_align(dev->pq_align, off1, off2, len);
1060 }
1061 
1062 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1063                                        size_t off2, size_t len)
1064 {
1065         return dmaengine_check_align(dev->fill_align, off1, off2, len);
1066 }
1067 
1068 static inline void
1069 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1070 {
1071         dma->max_pq = maxpq;
1072         if (has_pq_continue)
1073                 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1074 }
1075 
1076 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1077 {
1078         return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1079 }
1080 
1081 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1082 {
1083         enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1084 
1085         return (flags & mask) == mask;
1086 }
1087 
1088 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1089 {
1090         return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1091 }
1092 
1093 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1094 {
1095         return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1096 }
1097 
1098 /* dma_maxpq - reduce maxpq in the face of continued operations
1099  * @dma - dma device with PQ capability
1100  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1101  *
1102  * When an engine does not support native continuation we need 3 extra
1103  * source slots to reuse P and Q with the following coefficients:
1104  * 1/ {00} * P : remove P from Q', but use it as a source for P'
1105  * 2/ {01} * Q : use Q to continue Q' calculation
1106  * 3/ {00} * Q : subtract Q from P' to cancel (2)
1107  *
1108  * In the case where P is disabled we only need 1 extra source:
1109  * 1/ {01} * Q : use Q to continue Q' calculation
1110  */
1111 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1112 {
1113         if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1114                 return dma_dev_to_maxpq(dma);
1115         else if (dmaf_p_disabled_continue(flags))
1116                 return dma_dev_to_maxpq(dma) - 1;
1117         else if (dmaf_continue(flags))
1118                 return dma_dev_to_maxpq(dma) - 3;
1119         BUG();
1120 }
1121 
1122 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1123                                       size_t dir_icg)
1124 {
1125         if (inc) {
1126                 if (dir_icg)
1127                         return dir_icg;
1128                 else if (sgl)
1129                         return icg;
1130         }
1131 
1132         return 0;
1133 }
1134 
1135 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1136                                            struct data_chunk *chunk)
1137 {
1138         return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1139                                  chunk->icg, chunk->dst_icg);
1140 }
1141 
1142 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1143                                            struct data_chunk *chunk)
1144 {
1145         return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1146                                  chunk->icg, chunk->src_icg);
1147 }
1148 
1149 /* --- public DMA engine API --- */
1150 
1151 #ifdef CONFIG_DMA_ENGINE
1152 void dmaengine_get(void);
1153 void dmaengine_put(void);
1154 #else
1155 static inline void dmaengine_get(void)
1156 {
1157 }
1158 static inline void dmaengine_put(void)
1159 {
1160 }
1161 #endif
1162 
1163 #ifdef CONFIG_ASYNC_TX_DMA
1164 #define async_dmaengine_get()   dmaengine_get()
1165 #define async_dmaengine_put()   dmaengine_put()
1166 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1167 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1168 #else
1169 #define async_dma_find_channel(type) dma_find_channel(type)
1170 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1171 #else
1172 static inline void async_dmaengine_get(void)
1173 {
1174 }
1175 static inline void async_dmaengine_put(void)
1176 {
1177 }
1178 static inline struct dma_chan *
1179 async_dma_find_channel(enum dma_transaction_type type)
1180 {
1181         return NULL;
1182 }
1183 #endif /* CONFIG_ASYNC_TX_DMA */
1184 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1185                                   struct dma_chan *chan);
1186 
1187 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1188 {
1189         tx->flags |= DMA_CTRL_ACK;
1190 }
1191 
1192 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1193 {
1194         tx->flags &= ~DMA_CTRL_ACK;
1195 }
1196 
1197 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1198 {
1199         return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1200 }
1201 
1202 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1203 static inline void
1204 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1205 {
1206         set_bit(tx_type, dstp->bits);
1207 }
1208 
1209 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1210 static inline void
1211 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1212 {
1213         clear_bit(tx_type, dstp->bits);
1214 }
1215 
1216 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1217 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1218 {
1219         bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1220 }
1221 
1222 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1223 static inline int
1224 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1225 {
1226         return test_bit(tx_type, srcp->bits);
1227 }
1228 
1229 #define for_each_dma_cap_mask(cap, mask) \
1230         for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1231 
1232 /**
1233  * dma_async_issue_pending - flush pending transactions to HW
1234  * @chan: target DMA channel
1235  *
1236  * This allows drivers to push copies to HW in batches,
1237  * reducing MMIO writes where possible.
1238  */
1239 static inline void dma_async_issue_pending(struct dma_chan *chan)
1240 {
1241         chan->device->device_issue_pending(chan);
1242 }
1243 
1244 /**
1245  * dma_async_is_tx_complete - poll for transaction completion
1246  * @chan: DMA channel
1247  * @cookie: transaction identifier to check status of
1248  * @last: returns last completed cookie, can be NULL
1249  * @used: returns last issued cookie, can be NULL
1250  *
1251  * If @last and @used are passed in, upon return they reflect the driver
1252  * internal state and can be used with dma_async_is_complete() to check
1253  * the status of multiple cookies without re-checking hardware state.
1254  */
1255 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1256         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1257 {
1258         struct dma_tx_state state;
1259         enum dma_status status;
1260 
1261         status = chan->device->device_tx_status(chan, cookie, &state);
1262         if (last)
1263                 *last = state.last;
1264         if (used)
1265                 *used = state.used;
1266         return status;
1267 }
1268 
1269 /**
1270  * dma_async_is_complete - test a cookie against chan state
1271  * @cookie: transaction identifier to test status of
1272  * @last_complete: last know completed transaction
1273  * @last_used: last cookie value handed out
1274  *
1275  * dma_async_is_complete() is used in dma_async_is_tx_complete()
1276  * the test logic is separated for lightweight testing of multiple cookies
1277  */
1278 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1279                         dma_cookie_t last_complete, dma_cookie_t last_used)
1280 {
1281         if (last_complete <= last_used) {
1282                 if ((cookie <= last_complete) || (cookie > last_used))
1283                         return DMA_COMPLETE;
1284         } else {
1285                 if ((cookie <= last_complete) && (cookie > last_used))
1286                         return DMA_COMPLETE;
1287         }
1288         return DMA_IN_PROGRESS;
1289 }
1290 
1291 static inline void
1292 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1293 {
1294         if (st) {
1295                 st->last = last;
1296                 st->used = used;
1297                 st->residue = residue;
1298         }
1299 }
1300 
1301 #ifdef CONFIG_DMA_ENGINE
1302 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1303 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1304 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1305 void dma_issue_pending_all(void);
1306 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1307                                        dma_filter_fn fn, void *fn_param,
1308                                        struct device_node *np);
1309 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1310 
1311 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1312 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1313 
1314 void dma_release_channel(struct dma_chan *chan);
1315 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1316 #else
1317 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1318 {
1319         return NULL;
1320 }
1321 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1322 {
1323         return DMA_COMPLETE;
1324 }
1325 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1326 {
1327         return DMA_COMPLETE;
1328 }
1329 static inline void dma_issue_pending_all(void)
1330 {
1331 }
1332 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1333                                                      dma_filter_fn fn,
1334                                                      void *fn_param,
1335                                                      struct device_node *np)
1336 {
1337         return NULL;
1338 }
1339 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1340                                                          const char *name)
1341 {
1342         return NULL;
1343 }
1344 static inline struct dma_chan *dma_request_chan(struct device *dev,
1345                                                 const char *name)
1346 {
1347         return ERR_PTR(-ENODEV);
1348 }
1349 static inline struct dma_chan *dma_request_chan_by_mask(
1350                                                 const dma_cap_mask_t *mask)
1351 {
1352         return ERR_PTR(-ENODEV);
1353 }
1354 static inline void dma_release_channel(struct dma_chan *chan)
1355 {
1356 }
1357 static inline int dma_get_slave_caps(struct dma_chan *chan,
1358                                      struct dma_slave_caps *caps)
1359 {
1360         return -ENXIO;
1361 }
1362 #endif
1363 
1364 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1365 
1366 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1367 {
1368         struct dma_slave_caps caps;
1369         int ret;
1370 
1371         ret = dma_get_slave_caps(tx->chan, &caps);
1372         if (ret)
1373                 return ret;
1374 
1375         if (caps.descriptor_reuse) {
1376                 tx->flags |= DMA_CTRL_REUSE;
1377                 return 0;
1378         } else {
1379                 return -EPERM;
1380         }
1381 }
1382 
1383 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1384 {
1385         tx->flags &= ~DMA_CTRL_REUSE;
1386 }
1387 
1388 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1389 {
1390         return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1391 }
1392 
1393 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1394 {
1395         /* this is supported for reusable desc, so check that */
1396         if (dmaengine_desc_test_reuse(desc))
1397                 return desc->desc_free(desc);
1398         else
1399                 return -EPERM;
1400 }
1401 
1402 /* --- DMA device --- */
1403 
1404 int dma_async_device_register(struct dma_device *device);
1405 int dmaenginem_async_device_register(struct dma_device *device);
1406 void dma_async_device_unregister(struct dma_device *device);
1407 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1408 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1409 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1410 #define dma_request_channel(mask, x, y) \
1411         __dma_request_channel(&(mask), x, y, NULL)
1412 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1413         __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1414 
1415 static inline struct dma_chan
1416 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1417                                   dma_filter_fn fn, void *fn_param,
1418                                   struct device *dev, const char *name)
1419 {
1420         struct dma_chan *chan;
1421 
1422         chan = dma_request_slave_channel(dev, name);
1423         if (chan)
1424                 return chan;
1425 
1426         if (!fn || !fn_param)
1427                 return NULL;
1428 
1429         return __dma_request_channel(mask, fn, fn_param, NULL);
1430 }
1431 #endif /* DMAENGINE_H */
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root/include/linux/dmaengine.h

INCLUDED FROM

DEFINITIONS
