1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2009 Texas Instruments Inc
4 *
5 * vpss - video processing subsystem module header file.
6 *
7 * Include this header file if a driver needs to configure vpss system
8 * module. It exports a set of library functions for video drivers to
9 * configure vpss system module functions such as clock enable/disable,
10 * vpss interrupt mux to arm, and other common vpss system module
11 * functions.
12 */
13 #ifndef _VPSS_H
14 #define _VPSS_H
15
16 /* selector for ccdc input selection on DM355 */
17 enum vpss_ccdc_source_sel {
18 VPSS_CCDCIN,
19 VPSS_HSSIIN,
20 VPSS_PGLPBK, /* for DM365 only */
21 VPSS_CCDCPG /* for DM365 only */
22 };
23
24 struct vpss_sync_pol {
25 unsigned int ccdpg_hdpol:1;
26 unsigned int ccdpg_vdpol:1;
27 };
28
29 struct vpss_pg_frame_size {
30 short hlpfr;
31 short pplen;
32 };
33
34 /* Used for enable/disable VPSS Clock */
35 enum vpss_clock_sel {
36 /* DM355/DM365 */
37 VPSS_CCDC_CLOCK,
38 VPSS_IPIPE_CLOCK,
39 VPSS_H3A_CLOCK,
40 VPSS_CFALD_CLOCK,
41 /*
42 * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
43 * following applies:-
44 * en = 0 selects ENC_CLK
45 * en = 1 selects ENC_CLK/2
46 */
47 VPSS_VENC_CLOCK_SEL,
48 VPSS_VPBE_CLOCK,
49 /* DM365 only clocks */
50 VPSS_IPIPEIF_CLOCK,
51 VPSS_RSZ_CLOCK,
52 VPSS_BL_CLOCK,
53 /*
54 * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
55 * following applies:-
56 * en = 0 disable internal PCLK
57 * en = 1 enables internal PCLK
58 */
59 VPSS_PCLK_INTERNAL,
60 /*
61 * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
62 * following applies:-
63 * en = 0 enables MMR clock
64 * en = 1 enables VPSS clock
65 */
66 VPSS_PSYNC_CLOCK_SEL,
67 VPSS_LDC_CLOCK_SEL,
68 VPSS_OSD_CLOCK_SEL,
69 VPSS_FDIF_CLOCK,
70 VPSS_LDC_CLOCK
71 };
72
73 /* select input to ccdc on dm355 */
74 int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
75 /* enable/disable a vpss clock, 0 - success, -1 - failure */
76 int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
77 /* set sync polarity, only for DM365*/
78 void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
79 /* set the PG_FRAME_SIZE register, only for DM365 */
80 void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
81
82 /* wbl reset for dm644x */
83 enum vpss_wbl_sel {
84 VPSS_PCR_AEW_WBL_0 = 16,
85 VPSS_PCR_AF_WBL_0,
86 VPSS_PCR_RSZ4_WBL_0,
87 VPSS_PCR_RSZ3_WBL_0,
88 VPSS_PCR_RSZ2_WBL_0,
89 VPSS_PCR_RSZ1_WBL_0,
90 VPSS_PCR_PREV_WBL_0,
91 VPSS_PCR_CCDC_WBL_O,
92 };
93 /* clear wbl overflow flag for DM6446 */
94 int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
95
96 /* set sync polarity*/
97 void vpss_set_sync_pol(struct vpss_sync_pol sync);
98 /* set the PG_FRAME_SIZE register */
99 void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size);
100 /*
101 * vpss_check_and_clear_interrupt - check and clear interrupt
102 * @irq - common enumerator for IRQ
103 *
104 * Following return values used:-
105 * 0 - interrupt occurred and cleared
106 * 1 - interrupt not occurred
107 * 2 - interrupt status not available
108 */
109 int vpss_dma_complete_interrupt(void);
110
111 #endif