This source file includes following definitions.
- snd_hdac_stream_get_pos_lpib
- snd_hdac_stream_get_pos_posbuf
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8 #ifndef __SOUND_HDA_REGISTER_H
9 #define __SOUND_HDA_REGISTER_H
10
11 #include <linux/io.h>
12 #include <sound/hdaudio.h>
13
14 #define AZX_REG_GCAP 0x00
15 #define AZX_GCAP_64OK (1 << 0)
16 #define AZX_GCAP_NSDO (3 << 1)
17 #define AZX_GCAP_BSS (31 << 3)
18 #define AZX_GCAP_ISS (15 << 8)
19 #define AZX_GCAP_OSS (15 << 12)
20 #define AZX_REG_VMIN 0x02
21 #define AZX_REG_VMAJ 0x03
22 #define AZX_REG_OUTPAY 0x04
23 #define AZX_REG_INPAY 0x06
24 #define AZX_REG_GCTL 0x08
25 #define AZX_GCTL_RESET (1 << 0)
26 #define AZX_GCTL_FCNTRL (1 << 1)
27 #define AZX_GCTL_UNSOL (1 << 8)
28 #define AZX_REG_WAKEEN 0x0c
29 #define AZX_REG_STATESTS 0x0e
30 #define AZX_REG_GSTS 0x10
31 #define AZX_GSTS_FSTS (1 << 1)
32 #define AZX_REG_GCAP2 0x12
33 #define AZX_REG_LLCH 0x14
34 #define AZX_REG_OUTSTRMPAY 0x18
35 #define AZX_REG_INSTRMPAY 0x1A
36 #define AZX_REG_INTCTL 0x20
37 #define AZX_REG_INTSTS 0x24
38 #define AZX_REG_WALLCLK 0x30
39 #define AZX_REG_OLD_SSYNC 0x34
40 #define AZX_REG_SSYNC 0x38
41 #define AZX_REG_CORBLBASE 0x40
42 #define AZX_REG_CORBUBASE 0x44
43 #define AZX_REG_CORBWP 0x48
44 #define AZX_REG_CORBRP 0x4a
45 #define AZX_CORBRP_RST (1 << 15)
46 #define AZX_REG_CORBCTL 0x4c
47 #define AZX_CORBCTL_RUN (1 << 1)
48 #define AZX_CORBCTL_CMEIE (1 << 0)
49 #define AZX_REG_CORBSTS 0x4d
50 #define AZX_CORBSTS_CMEI (1 << 0)
51 #define AZX_REG_CORBSIZE 0x4e
52
53 #define AZX_REG_RIRBLBASE 0x50
54 #define AZX_REG_RIRBUBASE 0x54
55 #define AZX_REG_RIRBWP 0x58
56 #define AZX_RIRBWP_RST (1 << 15)
57 #define AZX_REG_RINTCNT 0x5a
58 #define AZX_REG_RIRBCTL 0x5c
59 #define AZX_RBCTL_IRQ_EN (1 << 0)
60 #define AZX_RBCTL_DMA_EN (1 << 1)
61 #define AZX_RBCTL_OVERRUN_EN (1 << 2)
62 #define AZX_REG_RIRBSTS 0x5d
63 #define AZX_RBSTS_IRQ (1 << 0)
64 #define AZX_RBSTS_OVERRUN (1 << 2)
65 #define AZX_REG_RIRBSIZE 0x5e
66
67 #define AZX_REG_IC 0x60
68 #define AZX_REG_IR 0x64
69 #define AZX_REG_IRS 0x68
70 #define AZX_IRS_VALID (1<<1)
71 #define AZX_IRS_BUSY (1<<0)
72
73 #define AZX_REG_DPLBASE 0x70
74 #define AZX_REG_DPUBASE 0x74
75 #define AZX_DPLBASE_ENABLE 0x1
76
77
78 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
79
80
81 #define AZX_REG_SD_CTL 0x00
82 #define AZX_REG_SD_CTL_3B 0x02
83 #define AZX_REG_SD_STS 0x03
84 #define AZX_REG_SD_LPIB 0x04
85 #define AZX_REG_SD_CBL 0x08
86 #define AZX_REG_SD_LVI 0x0c
87 #define AZX_REG_SD_FIFOW 0x0e
88 #define AZX_REG_SD_FIFOSIZE 0x10
89 #define AZX_REG_SD_FORMAT 0x12
90 #define AZX_REG_SD_FIFOL 0x14
91 #define AZX_REG_SD_BDLPL 0x18
92 #define AZX_REG_SD_BDLPU 0x1c
93
94
95 #define AZX_REG_LLCH 0x14
96
97 #define AZX_REG_GTS_BASE 0x520
98
99 #define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00)
100 #define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04)
101 #define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08)
102 #define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C)
103 #define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14)
104 #define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18)
105 #define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C)
106
107
108 #define AZX_REG_HSW_EM4 0x100c
109 #define AZX_REG_HSW_EM5 0x1010
110
111
112 #define AZX_REG_VS_EM1 0x1000
113 #define AZX_REG_VS_INRC 0x1004
114 #define AZX_REG_VS_OUTRC 0x1008
115 #define AZX_REG_VS_FIFOTRK 0x100C
116 #define AZX_REG_VS_FIFOTRK2 0x1010
117 #define AZX_REG_VS_EM2 0x1030
118 #define AZX_REG_VS_EM3L 0x1038
119 #define AZX_REG_VS_EM3U 0x103C
120 #define AZX_REG_VS_EM4L 0x1040
121 #define AZX_REG_VS_EM4U 0x1044
122 #define AZX_REG_VS_LTRC 0x1048
123 #define AZX_REG_VS_D0I3C 0x104A
124 #define AZX_REG_VS_PCE 0x104B
125 #define AZX_REG_VS_L2MAGC 0x1050
126 #define AZX_REG_VS_L2LAHPT 0x1054
127 #define AZX_REG_VS_SDXDPIB_XBASE 0x1084
128 #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
129 #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
130 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
131
132
133 #define AZX_PCIREG_TCSEL 0x44
134
135
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137
138
139
140 #define BDL_SIZE 4096
141 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
142 #define AZX_MAX_FRAG 32
143
144 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
145
146
147 #define RIRB_INT_RESPONSE 0x01
148 #define RIRB_INT_OVERRUN 0x04
149 #define RIRB_INT_MASK 0x05
150
151
152 #define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)
153
154
155 #define SD_CTL_STREAM_RESET 0x01
156 #define SD_CTL_DMA_START 0x02
157 #define SD_CTL_STRIPE (3 << 16)
158 #define SD_CTL_TRAFFIC_PRIO (1 << 18)
159 #define SD_CTL_DIR (1 << 19)
160 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
161 #define SD_CTL_STREAM_TAG_SHIFT 20
162
163
164 #define SD_INT_DESC_ERR 0x10
165 #define SD_INT_FIFO_ERR 0x08
166 #define SD_INT_COMPLETE 0x04
167 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
168 SD_INT_COMPLETE)
169 #define SD_CTL_STRIPE_MASK 0x3
170
171
172 #define SD_STS_FIFO_READY 0x20
173
174
175 #define AZX_INT_ALL_STREAM 0xff
176 #define AZX_INT_CTRL_EN 0x40000000
177 #define AZX_INT_GLOBAL_EN 0x80000000
178
179
180 #define AZX_MAX_CORB_ENTRIES 256
181 #define AZX_MAX_RIRB_ENTRIES 256
182
183
184 #define AZX_REG_CAP_HDR 0x0
185 #define AZX_CAP_HDR_VER_OFF 28
186 #define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF)
187 #define AZX_CAP_HDR_ID_OFF 16
188 #define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF)
189 #define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF
190
191
192 #define AZX_SPB_CAP_ID 0x4
193 #define AZX_REG_SPB_BASE_ADDR 0x700
194 #define AZX_REG_SPB_SPBFCH 0x00
195 #define AZX_REG_SPB_SPBFCCTL 0x04
196
197 #define AZX_SPB_BASE 0x08
198
199 #define AZX_SPB_INTERVAL 0x08
200
201 #define AZX_SPB_SPIB 0x00
202
203 #define AZX_SPB_MAXFIFO 0x04
204
205
206 #define AZX_GTS_CAP_ID 0x1
207 #define AZX_REG_GTS_GTSCH 0x00
208 #define AZX_REG_GTS_GTSCD 0x04
209 #define AZX_REG_GTS_GTSCTLAC 0x0C
210 #define AZX_GTS_BASE 0x20
211 #define AZX_GTS_INTERVAL 0x20
212
213
214 #define AZX_PP_CAP_ID 0x3
215 #define AZX_REG_PP_PPCH 0x10
216 #define AZX_REG_PP_PPCTL 0x04
217 #define AZX_PPCTL_PIE (1<<31)
218 #define AZX_PPCTL_GPROCEN (1<<30)
219
220 #define AZX_PPCTL_PROCEN(_X_) (1<<(_X_))
221
222 #define AZX_REG_PP_PPSTS 0x08
223
224 #define AZX_PPHC_BASE 0x10
225 #define AZX_PPHC_INTERVAL 0x10
226
227 #define AZX_REG_PPHCLLPL 0x0
228 #define AZX_REG_PPHCLLPU 0x4
229 #define AZX_REG_PPHCLDPL 0x8
230 #define AZX_REG_PPHCLDPU 0xC
231
232 #define AZX_PPLC_BASE 0x10
233 #define AZX_PPLC_MULTI 0x10
234 #define AZX_PPLC_INTERVAL 0x10
235
236 #define AZX_REG_PPLCCTL 0x0
237 #define AZX_PPLCCTL_STRM_BITS 4
238 #define AZX_PPLCCTL_STRM_SHIFT 20
239 #define AZX_REG_MASK(bit_num, offset) \
240 (((1 << (bit_num)) - 1) << (offset))
241 #define AZX_PPLCCTL_STRM_MASK \
242 AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
243 #define AZX_PPLCCTL_RUN (1<<1)
244 #define AZX_PPLCCTL_STRST (1<<0)
245
246 #define AZX_REG_PPLCFMT 0x4
247 #define AZX_REG_PPLCLLPL 0x8
248 #define AZX_REG_PPLCLLPU 0xC
249
250
251 #define AZX_ML_CAP_ID 0x2
252 #define AZX_REG_ML_MLCH 0x00
253 #define AZX_REG_ML_MLCD 0x04
254 #define AZX_ML_BASE 0x40
255 #define AZX_ML_INTERVAL 0x40
256
257 #define AZX_REG_ML_LCAP 0x00
258 #define AZX_REG_ML_LCTL 0x04
259 #define AZX_REG_ML_LOSIDV 0x08
260 #define AZX_REG_ML_LSDIID 0x0C
261 #define AZX_REG_ML_LPSOO 0x10
262 #define AZX_REG_ML_LPSIO 0x12
263 #define AZX_REG_ML_LWALFC 0x18
264 #define AZX_REG_ML_LOUTPAY 0x20
265 #define AZX_REG_ML_LINPAY 0x30
266
267
268 #define ML_LOSIDV_STREAM_MASK 0xFFFE
269
270 #define ML_LCTL_SCF_MASK 0xF
271 #define AZX_MLCTL_SPA (0x1 << 16)
272 #define AZX_MLCTL_CPA (0x1 << 23)
273 #define AZX_MLCTL_SPA_SHIFT 16
274 #define AZX_MLCTL_CPA_SHIFT 23
275
276
277 #define AZX_DRSM_CAP_ID 0x5
278 #define AZX_REG_DRSM_CTL 0x4
279
280 #define AZX_DRSM_BASE 0x08
281
282 #define AZX_DRSM_INTERVAL 0x08
283
284
285 #define GTSCC_TSCCD_MASK 0x80000000
286 #define GTSCC_TSCCD_SHIFT BIT(31)
287 #define GTSCC_TSCCI_MASK 0x20
288 #define GTSCC_CDMAS_DMA_DIR_SHIFT 4
289
290 #define WALFCC_CIF_MASK 0x1FF
291 #define WALFCC_FN_SHIFT 9
292 #define HDA_CLK_CYCLES_PER_FRAME 512
293
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298
299 #define HDA_MAX_CYCLE_VALUE 499
300 #define HDA_MAX_CYCLE_OFFSET 10
301 #define HDA_MAX_CYCLE_READ_RETRY 10
302
303 #define TSCCU_CCU_SHIFT 32
304 #define LLPC_CCU_SHIFT 32
305
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308
309
310 static inline unsigned int
311 snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
312 {
313 return snd_hdac_stream_readl(stream, SD_LPIB);
314 }
315
316 static inline unsigned int
317 snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
318 {
319 return le32_to_cpu(*stream->posbuf);
320 }
321
322 #endif