1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 */
8
9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
11
12 #include <sound/sof/header.h>
13
14 /*
15 * Component
16 */
17
18 /* types of component */
19 enum sof_comp_type {
20 SOF_COMP_NONE = 0,
21 SOF_COMP_HOST,
22 SOF_COMP_DAI,
23 SOF_COMP_SG_HOST, /**< scatter gather variant */
24 SOF_COMP_SG_DAI, /**< scatter gather variant */
25 SOF_COMP_VOLUME,
26 SOF_COMP_MIXER,
27 SOF_COMP_MUX,
28 SOF_COMP_SRC,
29 SOF_COMP_SPLITTER,
30 SOF_COMP_TONE,
31 SOF_COMP_SWITCH,
32 SOF_COMP_BUFFER,
33 SOF_COMP_EQ_IIR,
34 SOF_COMP_EQ_FIR,
35 SOF_COMP_KEYWORD_DETECT,
36 SOF_COMP_KPB, /* A key phrase buffer component */
37 SOF_COMP_SELECTOR, /**< channel selector component */
38 SOF_COMP_DEMUX,
39 /* keep FILEREAD/FILEWRITE as the last ones */
40 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
41 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
42 };
43
44 /* XRUN action for component */
45 #define SOF_XRUN_STOP 1 /**< stop stream */
46 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
47 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
48
49 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
50 struct sof_ipc_comp {
51 struct sof_ipc_cmd_hdr hdr;
52 uint32_t id;
53 enum sof_comp_type type;
54 uint32_t pipeline_id;
55
56 /* reserved for future use */
57 uint32_t reserved[2];
58 } __packed;
59
60 /*
61 * Component Buffers
62 */
63
64 /*
65 * SOF memory capabilities, add new ones at the end
66 */
67 #define SOF_MEM_CAPS_RAM (1 << 0)
68 #define SOF_MEM_CAPS_ROM (1 << 1)
69 #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */
70 #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */
71 #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */
72 #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */
73 #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */
74 #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */
75
76 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
77 struct sof_ipc_buffer {
78 struct sof_ipc_comp comp;
79 uint32_t size; /**< buffer size in bytes */
80 uint32_t caps; /**< SOF_MEM_CAPS_ */
81 } __packed;
82
83 /* generic component config data - must always be after struct sof_ipc_comp */
84 struct sof_ipc_comp_config {
85 struct sof_ipc_cmd_hdr hdr;
86 uint32_t periods_sink; /**< 0 means variable */
87 uint32_t periods_source;/**< 0 means variable */
88 uint32_t reserved1; /**< reserved */
89 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
90 uint32_t xrun_action;
91
92 /* reserved for future use */
93 uint32_t reserved[2];
94 } __packed;
95
96 /* generic host component */
97 struct sof_ipc_comp_host {
98 struct sof_ipc_comp comp;
99 struct sof_ipc_comp_config config;
100 uint32_t direction; /**< SOF_IPC_STREAM_ */
101 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
102 uint32_t dmac_config; /**< DMA engine specific */
103 } __packed;
104
105 /* generic DAI component */
106 struct sof_ipc_comp_dai {
107 struct sof_ipc_comp comp;
108 struct sof_ipc_comp_config config;
109 uint32_t direction; /**< SOF_IPC_STREAM_ */
110 uint32_t dai_index; /**< index of this type dai */
111 uint32_t type; /**< DAI type - SOF_DAI_ */
112 uint32_t reserved; /**< reserved */
113 } __packed;
114
115 /* generic mixer component */
116 struct sof_ipc_comp_mixer {
117 struct sof_ipc_comp comp;
118 struct sof_ipc_comp_config config;
119 } __packed;
120
121 /* volume ramping types */
122 enum sof_volume_ramp {
123 SOF_VOLUME_LINEAR = 0,
124 SOF_VOLUME_LOG,
125 SOF_VOLUME_LINEAR_ZC,
126 SOF_VOLUME_LOG_ZC,
127 };
128
129 /* generic volume component */
130 struct sof_ipc_comp_volume {
131 struct sof_ipc_comp comp;
132 struct sof_ipc_comp_config config;
133 uint32_t channels;
134 uint32_t min_value;
135 uint32_t max_value;
136 uint32_t ramp; /**< SOF_VOLUME_ */
137 uint32_t initial_ramp; /**< ramp space in ms */
138 } __packed;
139
140 /* generic SRC component */
141 struct sof_ipc_comp_src {
142 struct sof_ipc_comp comp;
143 struct sof_ipc_comp_config config;
144 /* either source or sink rate must be non zero */
145 uint32_t source_rate; /**< source rate or 0 for variable */
146 uint32_t sink_rate; /**< sink rate or 0 for variable */
147 uint32_t rate_mask; /**< SOF_RATE_ supported rates */
148 } __packed;
149
150 /* generic MUX component */
151 struct sof_ipc_comp_mux {
152 struct sof_ipc_comp comp;
153 struct sof_ipc_comp_config config;
154 } __packed;
155
156 /* generic tone generator component */
157 struct sof_ipc_comp_tone {
158 struct sof_ipc_comp comp;
159 struct sof_ipc_comp_config config;
160 int32_t sample_rate;
161 int32_t frequency;
162 int32_t amplitude;
163 int32_t freq_mult;
164 int32_t ampl_mult;
165 int32_t length;
166 int32_t period;
167 int32_t repeats;
168 int32_t ramp_step;
169 } __packed;
170
171 /** \brief Types of processing components */
172 enum sof_ipc_process_type {
173 SOF_PROCESS_NONE = 0, /**< None */
174 SOF_PROCESS_EQFIR, /**< Intel FIR */
175 SOF_PROCESS_EQIIR, /**< Intel IIR */
176 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
177 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
178 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
179 SOF_PROCESS_MUX,
180 SOF_PROCESS_DEMUX,
181 };
182
183 /* generic "effect", "codec" or proprietary processing component */
184 struct sof_ipc_comp_process {
185 struct sof_ipc_comp comp;
186 struct sof_ipc_comp_config config;
187 uint32_t size; /**< size of bespoke data section in bytes */
188 uint32_t type; /**< sof_ipc_process_type */
189
190 /* reserved for future use */
191 uint32_t reserved[7];
192
193 unsigned char data[0];
194 } __packed;
195
196 /* frees components, buffers and pipelines
197 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
198 */
199 struct sof_ipc_free {
200 struct sof_ipc_cmd_hdr hdr;
201 uint32_t id;
202 } __packed;
203
204 struct sof_ipc_comp_reply {
205 struct sof_ipc_reply rhdr;
206 uint32_t id;
207 uint32_t offset;
208 } __packed;
209
210 /*
211 * Pipeline
212 */
213
214 /** \brief Types of pipeline scheduling time domains */
215 enum sof_ipc_pipe_sched_time_domain {
216 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
217 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
218 };
219
220 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
221 struct sof_ipc_pipe_new {
222 struct sof_ipc_cmd_hdr hdr;
223 uint32_t comp_id; /**< component id for pipeline */
224 uint32_t pipeline_id; /**< pipeline id */
225 uint32_t sched_id; /**< Scheduling component id */
226 uint32_t core; /**< core we run on */
227 uint32_t period; /**< execution period in us*/
228 uint32_t priority; /**< priority level 0 (low) to 10 (max) */
229 uint32_t period_mips; /**< worst case instruction count per period */
230 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
231 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
232 uint32_t time_domain; /**< scheduling time domain */
233 } __packed;
234
235 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
236 struct sof_ipc_pipe_ready {
237 struct sof_ipc_cmd_hdr hdr;
238 uint32_t comp_id;
239 } __packed;
240
241 struct sof_ipc_pipe_free {
242 struct sof_ipc_cmd_hdr hdr;
243 uint32_t comp_id;
244 } __packed;
245
246 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
247 struct sof_ipc_pipe_comp_connect {
248 struct sof_ipc_cmd_hdr hdr;
249 uint32_t source_id;
250 uint32_t sink_id;
251 } __packed;
252
253 /* external events */
254 enum sof_event_types {
255 SOF_EVENT_NONE = 0,
256 SOF_KEYWORD_DETECT_DAPM_EVENT,
257 };
258
259 #endif