This source file includes following definitions.
- io_queue_depth_set
- sq_idx
- cq_idx
- to_nvme_dev
- max_io_queues
- max_queue_count
- nvme_dbbuf_size
- nvme_dbbuf_dma_alloc
- nvme_dbbuf_dma_free
- nvme_dbbuf_init
- nvme_dbbuf_set
- nvme_dbbuf_need_event
- nvme_dbbuf_update_and_check_event
- nvme_npages
- nvme_pci_npages_sgl
- nvme_pci_iod_alloc_size
- nvme_admin_init_hctx
- nvme_init_hctx
- nvme_init_request
- queue_irq_offset
- nvme_pci_map_queues
- nvme_write_sq_db
- nvme_submit_cmd
- nvme_commit_rqs
- nvme_pci_iod_list
- nvme_pci_use_sgls
- nvme_unmap_data
- nvme_print_sgl
- nvme_pci_setup_prps
- nvme_pci_sgl_set_data
- nvme_pci_sgl_set_seg
- nvme_pci_setup_sgls
- nvme_setup_prp_simple
- nvme_setup_sgl_simple
- nvme_map_data
- nvme_map_metadata
- nvme_queue_rq
- nvme_pci_complete_rq
- nvme_cqe_pending
- nvme_ring_cq_doorbell
- nvme_queue_tagset
- nvme_handle_cqe
- nvme_complete_cqes
- nvme_update_cq_head
- nvme_process_cq
- nvme_irq
- nvme_irq_check
- nvme_poll_irqdisable
- nvme_poll
- nvme_pci_submit_async_event
- adapter_delete_queue
- adapter_alloc_cq
- adapter_alloc_sq
- adapter_delete_cq
- adapter_delete_sq
- abort_endio
- nvme_should_reset
- nvme_warn_reset
- nvme_timeout
- nvme_free_queue
- nvme_free_queues
- nvme_suspend_queue
- nvme_suspend_io_queues
- nvme_disable_admin_queue
- nvme_reap_pending_cqes
- nvme_cmb_qdepth
- nvme_alloc_sq_cmds
- nvme_alloc_queue
- queue_request_irq
- nvme_init_queue
- nvme_create_queue
- nvme_dev_remove_admin
- nvme_alloc_admin_tags
- db_bar_size
- nvme_remap_bar
- nvme_pci_configure_admin_queue
- nvme_create_io_queues
- nvme_cmb_show
- nvme_cmb_size_unit
- nvme_cmb_size
- nvme_map_cmb
- nvme_release_cmb
- nvme_set_host_mem
- nvme_free_host_mem
- __nvme_alloc_host_mem
- nvme_alloc_host_mem
- nvme_setup_host_mem
- nvme_calc_irq_sets
- nvme_setup_irqs
- nvme_disable_io_queues
- nvme_setup_io_queues
- nvme_del_queue_end
- nvme_del_cq_end
- nvme_delete_queue
- __nvme_disable_io_queues
- nvme_dev_add
- nvme_pci_enable
- nvme_dev_unmap
- nvme_pci_disable
- nvme_dev_disable
- nvme_disable_prepare_reset
- nvme_setup_prp_pools
- nvme_release_prp_pools
- nvme_free_tagset
- nvme_pci_free_ctrl
- nvme_remove_dead_ctrl
- nvme_reset_work
- nvme_remove_dead_ctrl_work
- nvme_pci_reg_read32
- nvme_pci_reg_write32
- nvme_pci_reg_read64
- nvme_pci_get_address
- nvme_dev_map
- check_vendor_combination_bug
- nvme_async_probe
- nvme_probe
- nvme_reset_prepare
- nvme_reset_done
- nvme_shutdown
- nvme_remove
- nvme_get_power_state
- nvme_set_power_state
- nvme_resume
- nvme_suspend
- nvme_simple_suspend
- nvme_simple_resume
- nvme_error_detected
- nvme_slot_reset
- nvme_error_resume
- nvme_init
- nvme_exit
1
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5
6
7 #include <linux/aer.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
27
28 #include "trace.h"
29 #include "nvme.h"
30
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
33
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
35
36
37
38
39
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
42
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
45
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65 };
66
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
71 static unsigned int write_queues;
72 module_param(write_queues, uint, 0644);
73 MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
77 static unsigned int poll_queues;
78 module_param(poll_queues, uint, 0644);
79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
81 struct nvme_dev;
82 struct nvme_queue;
83
84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
86
87
88
89
90 struct nvme_dev {
91 struct nvme_queue *queues;
92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
98 unsigned online_queues;
99 unsigned max_qid;
100 unsigned io_queues[HCTX_MAX_TYPES];
101 unsigned int num_vecs;
102 int q_depth;
103 int io_sqes;
104 u32 db_stride;
105 void __iomem *bar;
106 unsigned long bar_mapped_size;
107 struct work_struct remove_work;
108 struct mutex shutdown_lock;
109 bool subsystem;
110 u64 cmb_size;
111 bool cmb_use_sqes;
112 u32 cmbsz;
113 u32 cmbloc;
114 struct nvme_ctrl ctrl;
115 u32 last_ps;
116
117 mempool_t *iod_mempool;
118
119
120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
124
125
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
128 dma_addr_t host_mem_descs_dma;
129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
131 };
132
133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134 {
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142 }
143
144 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145 {
146 return qid * 2 * stride;
147 }
148
149 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150 {
151 return (qid * 2 + 1) * stride;
152 }
153
154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155 {
156 return container_of(ctrl, struct nvme_dev, ctrl);
157 }
158
159
160
161
162
163 struct nvme_queue {
164 struct nvme_dev *dev;
165 spinlock_t sq_lock;
166 void *sq_cmds;
167
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
169 volatile struct nvme_completion *cqes;
170 dma_addr_t sq_dma_addr;
171 dma_addr_t cq_dma_addr;
172 u32 __iomem *q_db;
173 u16 q_depth;
174 u16 cq_vector;
175 u16 sq_tail;
176 u16 last_sq_tail;
177 u16 cq_head;
178 u16 last_cq_head;
179 u16 qid;
180 u8 cq_phase;
181 u8 sqes;
182 unsigned long flags;
183 #define NVMEQ_ENABLED 0
184 #define NVMEQ_SQ_CMB 1
185 #define NVMEQ_DELETE_ERROR 2
186 #define NVMEQ_POLLED 3
187 u32 *dbbuf_sq_db;
188 u32 *dbbuf_cq_db;
189 u32 *dbbuf_sq_ei;
190 u32 *dbbuf_cq_ei;
191 struct completion delete_done;
192 };
193
194
195
196
197
198
199
200 struct nvme_iod {
201 struct nvme_request req;
202 struct nvme_queue *nvmeq;
203 bool use_sgl;
204 int aborted;
205 int npages;
206 int nents;
207 dma_addr_t first_dma;
208 unsigned int dma_len;
209 dma_addr_t meta_dma;
210 struct scatterlist *sg;
211 };
212
213 static unsigned int max_io_queues(void)
214 {
215 return num_possible_cpus() + write_queues + poll_queues;
216 }
217
218 static unsigned int max_queue_count(void)
219 {
220
221 return 1 + max_io_queues();
222 }
223
224 static inline unsigned int nvme_dbbuf_size(u32 stride)
225 {
226 return (max_queue_count() * 8 * stride);
227 }
228
229 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
230 {
231 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
232
233 if (dev->dbbuf_dbs)
234 return 0;
235
236 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
237 &dev->dbbuf_dbs_dma_addr,
238 GFP_KERNEL);
239 if (!dev->dbbuf_dbs)
240 return -ENOMEM;
241 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
242 &dev->dbbuf_eis_dma_addr,
243 GFP_KERNEL);
244 if (!dev->dbbuf_eis) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 return -ENOMEM;
249 }
250
251 return 0;
252 }
253
254 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
255 {
256 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
257
258 if (dev->dbbuf_dbs) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
262 }
263 if (dev->dbbuf_eis) {
264 dma_free_coherent(dev->dev, mem_size,
265 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
266 dev->dbbuf_eis = NULL;
267 }
268 }
269
270 static void nvme_dbbuf_init(struct nvme_dev *dev,
271 struct nvme_queue *nvmeq, int qid)
272 {
273 if (!dev->dbbuf_dbs || !qid)
274 return;
275
276 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
277 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
279 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
280 }
281
282 static void nvme_dbbuf_set(struct nvme_dev *dev)
283 {
284 struct nvme_command c;
285
286 if (!dev->dbbuf_dbs)
287 return;
288
289 memset(&c, 0, sizeof(c));
290 c.dbbuf.opcode = nvme_admin_dbbuf;
291 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
292 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
293
294 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
295 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
296
297 nvme_dbbuf_dma_free(dev);
298 }
299 }
300
301 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
302 {
303 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
304 }
305
306
307 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
308 volatile u32 *dbbuf_ei)
309 {
310 if (dbbuf_db) {
311 u16 old_value;
312
313
314
315
316
317 wmb();
318
319 old_value = *dbbuf_db;
320 *dbbuf_db = value;
321
322
323
324
325
326
327
328 mb();
329
330 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
331 return false;
332 }
333
334 return true;
335 }
336
337
338
339
340
341
342 static int nvme_npages(unsigned size, struct nvme_dev *dev)
343 {
344 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
345 dev->ctrl.page_size);
346 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
347 }
348
349
350
351
352
353 static int nvme_pci_npages_sgl(unsigned int num_seg)
354 {
355 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
356 }
357
358 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
359 unsigned int size, unsigned int nseg, bool use_sgl)
360 {
361 size_t alloc_size;
362
363 if (use_sgl)
364 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
365 else
366 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
367
368 return alloc_size + sizeof(struct scatterlist) * nseg;
369 }
370
371 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
372 unsigned int hctx_idx)
373 {
374 struct nvme_dev *dev = data;
375 struct nvme_queue *nvmeq = &dev->queues[0];
376
377 WARN_ON(hctx_idx != 0);
378 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
379
380 hctx->driver_data = nvmeq;
381 return 0;
382 }
383
384 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
385 unsigned int hctx_idx)
386 {
387 struct nvme_dev *dev = data;
388 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
389
390 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
391 hctx->driver_data = nvmeq;
392 return 0;
393 }
394
395 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
396 unsigned int hctx_idx, unsigned int numa_node)
397 {
398 struct nvme_dev *dev = set->driver_data;
399 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
400 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
401 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
402
403 BUG_ON(!nvmeq);
404 iod->nvmeq = nvmeq;
405
406 nvme_req(req)->ctrl = &dev->ctrl;
407 return 0;
408 }
409
410 static int queue_irq_offset(struct nvme_dev *dev)
411 {
412
413 if (dev->num_vecs > 1)
414 return 1;
415
416 return 0;
417 }
418
419 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
420 {
421 struct nvme_dev *dev = set->driver_data;
422 int i, qoff, offset;
423
424 offset = queue_irq_offset(dev);
425 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
426 struct blk_mq_queue_map *map = &set->map[i];
427
428 map->nr_queues = dev->io_queues[i];
429 if (!map->nr_queues) {
430 BUG_ON(i == HCTX_TYPE_DEFAULT);
431 continue;
432 }
433
434
435
436
437
438 map->queue_offset = qoff;
439 if (i != HCTX_TYPE_POLL && offset)
440 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
441 else
442 blk_mq_map_queues(map);
443 qoff += map->nr_queues;
444 offset += map->nr_queues;
445 }
446
447 return 0;
448 }
449
450
451
452
453 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
454 {
455 if (!write_sq) {
456 u16 next_tail = nvmeq->sq_tail + 1;
457
458 if (next_tail == nvmeq->q_depth)
459 next_tail = 0;
460 if (next_tail != nvmeq->last_sq_tail)
461 return;
462 }
463
464 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
465 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
466 writel(nvmeq->sq_tail, nvmeq->q_db);
467 nvmeq->last_sq_tail = nvmeq->sq_tail;
468 }
469
470
471
472
473
474
475
476 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
477 bool write_sq)
478 {
479 spin_lock(&nvmeq->sq_lock);
480 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
481 cmd, sizeof(*cmd));
482 if (++nvmeq->sq_tail == nvmeq->q_depth)
483 nvmeq->sq_tail = 0;
484 nvme_write_sq_db(nvmeq, write_sq);
485 spin_unlock(&nvmeq->sq_lock);
486 }
487
488 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
489 {
490 struct nvme_queue *nvmeq = hctx->driver_data;
491
492 spin_lock(&nvmeq->sq_lock);
493 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
494 nvme_write_sq_db(nvmeq, true);
495 spin_unlock(&nvmeq->sq_lock);
496 }
497
498 static void **nvme_pci_iod_list(struct request *req)
499 {
500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
501 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
502 }
503
504 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
505 {
506 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
507 int nseg = blk_rq_nr_phys_segments(req);
508 unsigned int avg_seg_size;
509
510 if (nseg == 0)
511 return false;
512
513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
514
515 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
516 return false;
517 if (!iod->nvmeq->qid)
518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522 }
523
524 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
525 {
526 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
527 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
528 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
529 int i;
530
531 if (iod->dma_len) {
532 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
533 rq_dma_dir(req));
534 return;
535 }
536
537 WARN_ON_ONCE(!iod->nents);
538
539 if (is_pci_p2pdma_page(sg_page(iod->sg)))
540 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
541 rq_dma_dir(req));
542 else
543 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
544
545
546 if (iod->npages == 0)
547 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
548 dma_addr);
549
550 for (i = 0; i < iod->npages; i++) {
551 void *addr = nvme_pci_iod_list(req)[i];
552
553 if (iod->use_sgl) {
554 struct nvme_sgl_desc *sg_list = addr;
555
556 next_dma_addr =
557 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
558 } else {
559 __le64 *prp_list = addr;
560
561 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
562 }
563
564 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
565 dma_addr = next_dma_addr;
566 }
567
568 mempool_free(iod->sg, dev->iod_mempool);
569 }
570
571 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
572 {
573 int i;
574 struct scatterlist *sg;
575
576 for_each_sg(sgl, sg, nents, i) {
577 dma_addr_t phys = sg_phys(sg);
578 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
579 "dma_address:%pad dma_length:%d\n",
580 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
581 sg_dma_len(sg));
582 }
583 }
584
585 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
586 struct request *req, struct nvme_rw_command *cmnd)
587 {
588 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
589 struct dma_pool *pool;
590 int length = blk_rq_payload_bytes(req);
591 struct scatterlist *sg = iod->sg;
592 int dma_len = sg_dma_len(sg);
593 u64 dma_addr = sg_dma_address(sg);
594 u32 page_size = dev->ctrl.page_size;
595 int offset = dma_addr & (page_size - 1);
596 __le64 *prp_list;
597 void **list = nvme_pci_iod_list(req);
598 dma_addr_t prp_dma;
599 int nprps, i;
600
601 length -= (page_size - offset);
602 if (length <= 0) {
603 iod->first_dma = 0;
604 goto done;
605 }
606
607 dma_len -= (page_size - offset);
608 if (dma_len) {
609 dma_addr += (page_size - offset);
610 } else {
611 sg = sg_next(sg);
612 dma_addr = sg_dma_address(sg);
613 dma_len = sg_dma_len(sg);
614 }
615
616 if (length <= page_size) {
617 iod->first_dma = dma_addr;
618 goto done;
619 }
620
621 nprps = DIV_ROUND_UP(length, page_size);
622 if (nprps <= (256 / 8)) {
623 pool = dev->prp_small_pool;
624 iod->npages = 0;
625 } else {
626 pool = dev->prp_page_pool;
627 iod->npages = 1;
628 }
629
630 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
631 if (!prp_list) {
632 iod->first_dma = dma_addr;
633 iod->npages = -1;
634 return BLK_STS_RESOURCE;
635 }
636 list[0] = prp_list;
637 iod->first_dma = prp_dma;
638 i = 0;
639 for (;;) {
640 if (i == page_size >> 3) {
641 __le64 *old_prp_list = prp_list;
642 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
643 if (!prp_list)
644 return BLK_STS_RESOURCE;
645 list[iod->npages++] = prp_list;
646 prp_list[0] = old_prp_list[i - 1];
647 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
648 i = 1;
649 }
650 prp_list[i++] = cpu_to_le64(dma_addr);
651 dma_len -= page_size;
652 dma_addr += page_size;
653 length -= page_size;
654 if (length <= 0)
655 break;
656 if (dma_len > 0)
657 continue;
658 if (unlikely(dma_len < 0))
659 goto bad_sgl;
660 sg = sg_next(sg);
661 dma_addr = sg_dma_address(sg);
662 dma_len = sg_dma_len(sg);
663 }
664
665 done:
666 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
667 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
668
669 return BLK_STS_OK;
670
671 bad_sgl:
672 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
673 "Invalid SGL for payload:%d nents:%d\n",
674 blk_rq_payload_bytes(req), iod->nents);
675 return BLK_STS_IOERR;
676 }
677
678 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
679 struct scatterlist *sg)
680 {
681 sge->addr = cpu_to_le64(sg_dma_address(sg));
682 sge->length = cpu_to_le32(sg_dma_len(sg));
683 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
684 }
685
686 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
687 dma_addr_t dma_addr, int entries)
688 {
689 sge->addr = cpu_to_le64(dma_addr);
690 if (entries < SGES_PER_PAGE) {
691 sge->length = cpu_to_le32(entries * sizeof(*sge));
692 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
693 } else {
694 sge->length = cpu_to_le32(PAGE_SIZE);
695 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
696 }
697 }
698
699 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
700 struct request *req, struct nvme_rw_command *cmd, int entries)
701 {
702 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
703 struct dma_pool *pool;
704 struct nvme_sgl_desc *sg_list;
705 struct scatterlist *sg = iod->sg;
706 dma_addr_t sgl_dma;
707 int i = 0;
708
709
710 cmd->flags = NVME_CMD_SGL_METABUF;
711
712 if (entries == 1) {
713 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
714 return BLK_STS_OK;
715 }
716
717 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
718 pool = dev->prp_small_pool;
719 iod->npages = 0;
720 } else {
721 pool = dev->prp_page_pool;
722 iod->npages = 1;
723 }
724
725 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
726 if (!sg_list) {
727 iod->npages = -1;
728 return BLK_STS_RESOURCE;
729 }
730
731 nvme_pci_iod_list(req)[0] = sg_list;
732 iod->first_dma = sgl_dma;
733
734 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
735
736 do {
737 if (i == SGES_PER_PAGE) {
738 struct nvme_sgl_desc *old_sg_desc = sg_list;
739 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
740
741 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
742 if (!sg_list)
743 return BLK_STS_RESOURCE;
744
745 i = 0;
746 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
747 sg_list[i++] = *link;
748 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
749 }
750
751 nvme_pci_sgl_set_data(&sg_list[i++], sg);
752 sg = sg_next(sg);
753 } while (--entries > 0);
754
755 return BLK_STS_OK;
756 }
757
758 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
759 struct request *req, struct nvme_rw_command *cmnd,
760 struct bio_vec *bv)
761 {
762 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
763 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
764 unsigned int first_prp_len = dev->ctrl.page_size - offset;
765
766 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
767 if (dma_mapping_error(dev->dev, iod->first_dma))
768 return BLK_STS_RESOURCE;
769 iod->dma_len = bv->bv_len;
770
771 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
772 if (bv->bv_len > first_prp_len)
773 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
774 return 0;
775 }
776
777 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
778 struct request *req, struct nvme_rw_command *cmnd,
779 struct bio_vec *bv)
780 {
781 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
782
783 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
784 if (dma_mapping_error(dev->dev, iod->first_dma))
785 return BLK_STS_RESOURCE;
786 iod->dma_len = bv->bv_len;
787
788 cmnd->flags = NVME_CMD_SGL_METABUF;
789 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
790 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
791 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
792 return 0;
793 }
794
795 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
796 struct nvme_command *cmnd)
797 {
798 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
799 blk_status_t ret = BLK_STS_RESOURCE;
800 int nr_mapped;
801
802 if (blk_rq_nr_phys_segments(req) == 1) {
803 struct bio_vec bv = req_bvec(req);
804
805 if (!is_pci_p2pdma_page(bv.bv_page)) {
806 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
807 return nvme_setup_prp_simple(dev, req,
808 &cmnd->rw, &bv);
809
810 if (iod->nvmeq->qid &&
811 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
812 return nvme_setup_sgl_simple(dev, req,
813 &cmnd->rw, &bv);
814 }
815 }
816
817 iod->dma_len = 0;
818 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
819 if (!iod->sg)
820 return BLK_STS_RESOURCE;
821 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
822 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
823 if (!iod->nents)
824 goto out;
825
826 if (is_pci_p2pdma_page(sg_page(iod->sg)))
827 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
828 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
829 else
830 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
831 rq_dma_dir(req), DMA_ATTR_NO_WARN);
832 if (!nr_mapped)
833 goto out;
834
835 iod->use_sgl = nvme_pci_use_sgls(dev, req);
836 if (iod->use_sgl)
837 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
838 else
839 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
840 out:
841 if (ret != BLK_STS_OK)
842 nvme_unmap_data(dev, req);
843 return ret;
844 }
845
846 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
847 struct nvme_command *cmnd)
848 {
849 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
850
851 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
852 rq_dma_dir(req), 0);
853 if (dma_mapping_error(dev->dev, iod->meta_dma))
854 return BLK_STS_IOERR;
855 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
856 return 0;
857 }
858
859
860
861
862 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
863 const struct blk_mq_queue_data *bd)
864 {
865 struct nvme_ns *ns = hctx->queue->queuedata;
866 struct nvme_queue *nvmeq = hctx->driver_data;
867 struct nvme_dev *dev = nvmeq->dev;
868 struct request *req = bd->rq;
869 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
870 struct nvme_command cmnd;
871 blk_status_t ret;
872
873 iod->aborted = 0;
874 iod->npages = -1;
875 iod->nents = 0;
876
877
878
879
880
881 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
882 return BLK_STS_IOERR;
883
884 ret = nvme_setup_cmd(ns, req, &cmnd);
885 if (ret)
886 return ret;
887
888 if (blk_rq_nr_phys_segments(req)) {
889 ret = nvme_map_data(dev, req, &cmnd);
890 if (ret)
891 goto out_free_cmd;
892 }
893
894 if (blk_integrity_rq(req)) {
895 ret = nvme_map_metadata(dev, req, &cmnd);
896 if (ret)
897 goto out_unmap_data;
898 }
899
900 blk_mq_start_request(req);
901 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
902 return BLK_STS_OK;
903 out_unmap_data:
904 nvme_unmap_data(dev, req);
905 out_free_cmd:
906 nvme_cleanup_cmd(req);
907 return ret;
908 }
909
910 static void nvme_pci_complete_rq(struct request *req)
911 {
912 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
913 struct nvme_dev *dev = iod->nvmeq->dev;
914
915 nvme_cleanup_cmd(req);
916 if (blk_integrity_rq(req))
917 dma_unmap_page(dev->dev, iod->meta_dma,
918 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
919 if (blk_rq_nr_phys_segments(req))
920 nvme_unmap_data(dev, req);
921 nvme_complete_rq(req);
922 }
923
924
925 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
926 {
927 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
928 nvmeq->cq_phase;
929 }
930
931 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
932 {
933 u16 head = nvmeq->cq_head;
934
935 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
936 nvmeq->dbbuf_cq_ei))
937 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
938 }
939
940 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
941 {
942 if (!nvmeq->qid)
943 return nvmeq->dev->admin_tagset.tags[0];
944 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
945 }
946
947 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
948 {
949 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
950 struct request *req;
951
952 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
953 dev_warn(nvmeq->dev->ctrl.device,
954 "invalid id %d completed on queue %d\n",
955 cqe->command_id, le16_to_cpu(cqe->sq_id));
956 return;
957 }
958
959
960
961
962
963
964
965 if (unlikely(nvmeq->qid == 0 &&
966 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
967 nvme_complete_async_event(&nvmeq->dev->ctrl,
968 cqe->status, &cqe->result);
969 return;
970 }
971
972 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
973 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
974 nvme_end_request(req, cqe->status, cqe->result);
975 }
976
977 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
978 {
979 while (start != end) {
980 nvme_handle_cqe(nvmeq, start);
981 if (++start == nvmeq->q_depth)
982 start = 0;
983 }
984 }
985
986 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
987 {
988 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
989 nvmeq->cq_head = 0;
990 nvmeq->cq_phase = !nvmeq->cq_phase;
991 } else {
992 nvmeq->cq_head++;
993 }
994 }
995
996 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
997 u16 *end, unsigned int tag)
998 {
999 int found = 0;
1000
1001 *start = nvmeq->cq_head;
1002 while (nvme_cqe_pending(nvmeq)) {
1003 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1004 found++;
1005 nvme_update_cq_head(nvmeq);
1006 }
1007 *end = nvmeq->cq_head;
1008
1009 if (*start != *end)
1010 nvme_ring_cq_doorbell(nvmeq);
1011 return found;
1012 }
1013
1014 static irqreturn_t nvme_irq(int irq, void *data)
1015 {
1016 struct nvme_queue *nvmeq = data;
1017 irqreturn_t ret = IRQ_NONE;
1018 u16 start, end;
1019
1020
1021
1022
1023
1024 rmb();
1025 if (nvmeq->cq_head != nvmeq->last_cq_head)
1026 ret = IRQ_HANDLED;
1027 nvme_process_cq(nvmeq, &start, &end, -1);
1028 nvmeq->last_cq_head = nvmeq->cq_head;
1029 wmb();
1030
1031 if (start != end) {
1032 nvme_complete_cqes(nvmeq, start, end);
1033 return IRQ_HANDLED;
1034 }
1035
1036 return ret;
1037 }
1038
1039 static irqreturn_t nvme_irq_check(int irq, void *data)
1040 {
1041 struct nvme_queue *nvmeq = data;
1042 if (nvme_cqe_pending(nvmeq))
1043 return IRQ_WAKE_THREAD;
1044 return IRQ_NONE;
1045 }
1046
1047
1048
1049
1050
1051 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1052 {
1053 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1054 u16 start, end;
1055 int found;
1056
1057
1058
1059
1060
1061
1062 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
1063 spin_lock(&nvmeq->cq_poll_lock);
1064 found = nvme_process_cq(nvmeq, &start, &end, tag);
1065 spin_unlock(&nvmeq->cq_poll_lock);
1066 } else {
1067 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1068 found = nvme_process_cq(nvmeq, &start, &end, tag);
1069 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1070 }
1071
1072 nvme_complete_cqes(nvmeq, start, end);
1073 return found;
1074 }
1075
1076 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1077 {
1078 struct nvme_queue *nvmeq = hctx->driver_data;
1079 u16 start, end;
1080 bool found;
1081
1082 if (!nvme_cqe_pending(nvmeq))
1083 return 0;
1084
1085 spin_lock(&nvmeq->cq_poll_lock);
1086 found = nvme_process_cq(nvmeq, &start, &end, -1);
1087 nvme_complete_cqes(nvmeq, start, end);
1088 spin_unlock(&nvmeq->cq_poll_lock);
1089
1090 return found;
1091 }
1092
1093 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1094 {
1095 struct nvme_dev *dev = to_nvme_dev(ctrl);
1096 struct nvme_queue *nvmeq = &dev->queues[0];
1097 struct nvme_command c;
1098
1099 memset(&c, 0, sizeof(c));
1100 c.common.opcode = nvme_admin_async_event;
1101 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1102 nvme_submit_cmd(nvmeq, &c, true);
1103 }
1104
1105 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1106 {
1107 struct nvme_command c;
1108
1109 memset(&c, 0, sizeof(c));
1110 c.delete_queue.opcode = opcode;
1111 c.delete_queue.qid = cpu_to_le16(id);
1112
1113 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1114 }
1115
1116 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1117 struct nvme_queue *nvmeq, s16 vector)
1118 {
1119 struct nvme_command c;
1120 int flags = NVME_QUEUE_PHYS_CONTIG;
1121
1122 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1123 flags |= NVME_CQ_IRQ_ENABLED;
1124
1125
1126
1127
1128
1129 memset(&c, 0, sizeof(c));
1130 c.create_cq.opcode = nvme_admin_create_cq;
1131 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1132 c.create_cq.cqid = cpu_to_le16(qid);
1133 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1134 c.create_cq.cq_flags = cpu_to_le16(flags);
1135 c.create_cq.irq_vector = cpu_to_le16(vector);
1136
1137 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1138 }
1139
1140 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1141 struct nvme_queue *nvmeq)
1142 {
1143 struct nvme_ctrl *ctrl = &dev->ctrl;
1144 struct nvme_command c;
1145 int flags = NVME_QUEUE_PHYS_CONTIG;
1146
1147
1148
1149
1150
1151
1152 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1153 flags |= NVME_SQ_PRIO_MEDIUM;
1154
1155
1156
1157
1158
1159 memset(&c, 0, sizeof(c));
1160 c.create_sq.opcode = nvme_admin_create_sq;
1161 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1162 c.create_sq.sqid = cpu_to_le16(qid);
1163 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1164 c.create_sq.sq_flags = cpu_to_le16(flags);
1165 c.create_sq.cqid = cpu_to_le16(qid);
1166
1167 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1168 }
1169
1170 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1171 {
1172 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1173 }
1174
1175 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1176 {
1177 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1178 }
1179
1180 static void abort_endio(struct request *req, blk_status_t error)
1181 {
1182 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = iod->nvmeq;
1184
1185 dev_warn(nvmeq->dev->ctrl.device,
1186 "Abort status: 0x%x", nvme_req(req)->status);
1187 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1188 blk_mq_free_request(req);
1189 }
1190
1191 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1192 {
1193
1194
1195
1196
1197 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1198
1199
1200 switch (dev->ctrl.state) {
1201 case NVME_CTRL_RESETTING:
1202 case NVME_CTRL_CONNECTING:
1203 return false;
1204 default:
1205 break;
1206 }
1207
1208
1209
1210
1211 if (!(csts & NVME_CSTS_CFS) && !nssro)
1212 return false;
1213
1214 return true;
1215 }
1216
1217 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1218 {
1219
1220 u16 pci_status;
1221 int result;
1222
1223 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1224 &pci_status);
1225 if (result == PCIBIOS_SUCCESSFUL)
1226 dev_warn(dev->ctrl.device,
1227 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1228 csts, pci_status);
1229 else
1230 dev_warn(dev->ctrl.device,
1231 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1232 csts, result);
1233 }
1234
1235 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1236 {
1237 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1238 struct nvme_queue *nvmeq = iod->nvmeq;
1239 struct nvme_dev *dev = nvmeq->dev;
1240 struct request *abort_req;
1241 struct nvme_command cmd;
1242 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1243
1244
1245
1246
1247 mb();
1248 if (pci_channel_offline(to_pci_dev(dev->dev)))
1249 return BLK_EH_RESET_TIMER;
1250
1251
1252
1253
1254 if (nvme_should_reset(dev, csts)) {
1255 nvme_warn_reset(dev, csts);
1256 nvme_dev_disable(dev, false);
1257 nvme_reset_ctrl(&dev->ctrl);
1258 return BLK_EH_DONE;
1259 }
1260
1261
1262
1263
1264 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1265 dev_warn(dev->ctrl.device,
1266 "I/O %d QID %d timeout, completion polled\n",
1267 req->tag, nvmeq->qid);
1268 return BLK_EH_DONE;
1269 }
1270
1271
1272
1273
1274
1275
1276
1277 switch (dev->ctrl.state) {
1278 case NVME_CTRL_CONNECTING:
1279 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1280
1281 case NVME_CTRL_DELETING:
1282 dev_warn_ratelimited(dev->ctrl.device,
1283 "I/O %d QID %d timeout, disable controller\n",
1284 req->tag, nvmeq->qid);
1285 nvme_dev_disable(dev, true);
1286 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1287 return BLK_EH_DONE;
1288 case NVME_CTRL_RESETTING:
1289 return BLK_EH_RESET_TIMER;
1290 default:
1291 break;
1292 }
1293
1294
1295
1296
1297
1298
1299 if (!nvmeq->qid || iod->aborted) {
1300 dev_warn(dev->ctrl.device,
1301 "I/O %d QID %d timeout, reset controller\n",
1302 req->tag, nvmeq->qid);
1303 nvme_dev_disable(dev, false);
1304 nvme_reset_ctrl(&dev->ctrl);
1305
1306 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1307 return BLK_EH_DONE;
1308 }
1309
1310 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1311 atomic_inc(&dev->ctrl.abort_limit);
1312 return BLK_EH_RESET_TIMER;
1313 }
1314 iod->aborted = 1;
1315
1316 memset(&cmd, 0, sizeof(cmd));
1317 cmd.abort.opcode = nvme_admin_abort_cmd;
1318 cmd.abort.cid = req->tag;
1319 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1320
1321 dev_warn(nvmeq->dev->ctrl.device,
1322 "I/O %d QID %d timeout, aborting\n",
1323 req->tag, nvmeq->qid);
1324
1325 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1326 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1327 if (IS_ERR(abort_req)) {
1328 atomic_inc(&dev->ctrl.abort_limit);
1329 return BLK_EH_RESET_TIMER;
1330 }
1331
1332 abort_req->timeout = ADMIN_TIMEOUT;
1333 abort_req->end_io_data = NULL;
1334 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1335
1336
1337
1338
1339
1340
1341 return BLK_EH_RESET_TIMER;
1342 }
1343
1344 static void nvme_free_queue(struct nvme_queue *nvmeq)
1345 {
1346 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1347 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1348 if (!nvmeq->sq_cmds)
1349 return;
1350
1351 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1352 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1353 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1354 } else {
1355 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1356 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1357 }
1358 }
1359
1360 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1361 {
1362 int i;
1363
1364 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1365 dev->ctrl.queue_count--;
1366 nvme_free_queue(&dev->queues[i]);
1367 }
1368 }
1369
1370
1371
1372
1373
1374 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1375 {
1376 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1377 return 1;
1378
1379
1380 mb();
1381
1382 nvmeq->dev->online_queues--;
1383 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1384 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1385 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1386 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1387 return 0;
1388 }
1389
1390 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1391 {
1392 int i;
1393
1394 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1395 nvme_suspend_queue(&dev->queues[i]);
1396 }
1397
1398 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1399 {
1400 struct nvme_queue *nvmeq = &dev->queues[0];
1401
1402 if (shutdown)
1403 nvme_shutdown_ctrl(&dev->ctrl);
1404 else
1405 nvme_disable_ctrl(&dev->ctrl);
1406
1407 nvme_poll_irqdisable(nvmeq, -1);
1408 }
1409
1410
1411
1412
1413
1414
1415
1416 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1417 {
1418 u16 start, end;
1419 int i;
1420
1421 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1422 nvme_process_cq(&dev->queues[i], &start, &end, -1);
1423 nvme_complete_cqes(&dev->queues[i], start, end);
1424 }
1425 }
1426
1427 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1428 int entry_size)
1429 {
1430 int q_depth = dev->q_depth;
1431 unsigned q_size_aligned = roundup(q_depth * entry_size,
1432 dev->ctrl.page_size);
1433
1434 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1435 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1436 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1437 q_depth = div_u64(mem_per_q, entry_size);
1438
1439
1440
1441
1442
1443
1444 if (q_depth < 64)
1445 return -ENOMEM;
1446 }
1447
1448 return q_depth;
1449 }
1450
1451 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1452 int qid)
1453 {
1454 struct pci_dev *pdev = to_pci_dev(dev->dev);
1455
1456 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1457 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1458 if (nvmeq->sq_cmds) {
1459 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1460 nvmeq->sq_cmds);
1461 if (nvmeq->sq_dma_addr) {
1462 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1463 return 0;
1464 }
1465
1466 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1467 }
1468 }
1469
1470 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1471 &nvmeq->sq_dma_addr, GFP_KERNEL);
1472 if (!nvmeq->sq_cmds)
1473 return -ENOMEM;
1474 return 0;
1475 }
1476
1477 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1478 {
1479 struct nvme_queue *nvmeq = &dev->queues[qid];
1480
1481 if (dev->ctrl.queue_count > qid)
1482 return 0;
1483
1484 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1485 nvmeq->q_depth = depth;
1486 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1487 &nvmeq->cq_dma_addr, GFP_KERNEL);
1488 if (!nvmeq->cqes)
1489 goto free_nvmeq;
1490
1491 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1492 goto free_cqdma;
1493
1494 nvmeq->dev = dev;
1495 spin_lock_init(&nvmeq->sq_lock);
1496 spin_lock_init(&nvmeq->cq_poll_lock);
1497 nvmeq->cq_head = 0;
1498 nvmeq->cq_phase = 1;
1499 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1500 nvmeq->qid = qid;
1501 dev->ctrl.queue_count++;
1502
1503 return 0;
1504
1505 free_cqdma:
1506 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1507 nvmeq->cq_dma_addr);
1508 free_nvmeq:
1509 return -ENOMEM;
1510 }
1511
1512 static int queue_request_irq(struct nvme_queue *nvmeq)
1513 {
1514 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1515 int nr = nvmeq->dev->ctrl.instance;
1516
1517 if (use_threaded_interrupts) {
1518 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1519 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1520 } else {
1521 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1522 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1523 }
1524 }
1525
1526 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1527 {
1528 struct nvme_dev *dev = nvmeq->dev;
1529
1530 nvmeq->sq_tail = 0;
1531 nvmeq->last_sq_tail = 0;
1532 nvmeq->cq_head = 0;
1533 nvmeq->cq_phase = 1;
1534 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1535 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1536 nvme_dbbuf_init(dev, nvmeq, qid);
1537 dev->online_queues++;
1538 wmb();
1539 }
1540
1541 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1542 {
1543 struct nvme_dev *dev = nvmeq->dev;
1544 int result;
1545 u16 vector = 0;
1546
1547 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1548
1549
1550
1551
1552
1553 if (!polled)
1554 vector = dev->num_vecs == 1 ? 0 : qid;
1555 else
1556 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1557
1558 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1559 if (result)
1560 return result;
1561
1562 result = adapter_alloc_sq(dev, qid, nvmeq);
1563 if (result < 0)
1564 return result;
1565 else if (result)
1566 goto release_cq;
1567
1568 nvmeq->cq_vector = vector;
1569 nvme_init_queue(nvmeq, qid);
1570
1571 if (!polled) {
1572 result = queue_request_irq(nvmeq);
1573 if (result < 0)
1574 goto release_sq;
1575 }
1576
1577 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1578 return result;
1579
1580 release_sq:
1581 dev->online_queues--;
1582 adapter_delete_sq(dev, qid);
1583 release_cq:
1584 adapter_delete_cq(dev, qid);
1585 return result;
1586 }
1587
1588 static const struct blk_mq_ops nvme_mq_admin_ops = {
1589 .queue_rq = nvme_queue_rq,
1590 .complete = nvme_pci_complete_rq,
1591 .init_hctx = nvme_admin_init_hctx,
1592 .init_request = nvme_init_request,
1593 .timeout = nvme_timeout,
1594 };
1595
1596 static const struct blk_mq_ops nvme_mq_ops = {
1597 .queue_rq = nvme_queue_rq,
1598 .complete = nvme_pci_complete_rq,
1599 .commit_rqs = nvme_commit_rqs,
1600 .init_hctx = nvme_init_hctx,
1601 .init_request = nvme_init_request,
1602 .map_queues = nvme_pci_map_queues,
1603 .timeout = nvme_timeout,
1604 .poll = nvme_poll,
1605 };
1606
1607 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1608 {
1609 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1610
1611
1612
1613
1614
1615 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1616 blk_cleanup_queue(dev->ctrl.admin_q);
1617 blk_mq_free_tag_set(&dev->admin_tagset);
1618 }
1619 }
1620
1621 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1622 {
1623 if (!dev->ctrl.admin_q) {
1624 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1625 dev->admin_tagset.nr_hw_queues = 1;
1626
1627 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1628 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1629 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1630 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1631 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1632 dev->admin_tagset.driver_data = dev;
1633
1634 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1635 return -ENOMEM;
1636 dev->ctrl.admin_tagset = &dev->admin_tagset;
1637
1638 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1639 if (IS_ERR(dev->ctrl.admin_q)) {
1640 blk_mq_free_tag_set(&dev->admin_tagset);
1641 return -ENOMEM;
1642 }
1643 if (!blk_get_queue(dev->ctrl.admin_q)) {
1644 nvme_dev_remove_admin(dev);
1645 dev->ctrl.admin_q = NULL;
1646 return -ENODEV;
1647 }
1648 } else
1649 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1650
1651 return 0;
1652 }
1653
1654 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1655 {
1656 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1657 }
1658
1659 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1660 {
1661 struct pci_dev *pdev = to_pci_dev(dev->dev);
1662
1663 if (size <= dev->bar_mapped_size)
1664 return 0;
1665 if (size > pci_resource_len(pdev, 0))
1666 return -ENOMEM;
1667 if (dev->bar)
1668 iounmap(dev->bar);
1669 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1670 if (!dev->bar) {
1671 dev->bar_mapped_size = 0;
1672 return -ENOMEM;
1673 }
1674 dev->bar_mapped_size = size;
1675 dev->dbs = dev->bar + NVME_REG_DBS;
1676
1677 return 0;
1678 }
1679
1680 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1681 {
1682 int result;
1683 u32 aqa;
1684 struct nvme_queue *nvmeq;
1685
1686 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1687 if (result < 0)
1688 return result;
1689
1690 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1691 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1692
1693 if (dev->subsystem &&
1694 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1695 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1696
1697 result = nvme_disable_ctrl(&dev->ctrl);
1698 if (result < 0)
1699 return result;
1700
1701 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1702 if (result)
1703 return result;
1704
1705 nvmeq = &dev->queues[0];
1706 aqa = nvmeq->q_depth - 1;
1707 aqa |= aqa << 16;
1708
1709 writel(aqa, dev->bar + NVME_REG_AQA);
1710 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1711 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1712
1713 result = nvme_enable_ctrl(&dev->ctrl);
1714 if (result)
1715 return result;
1716
1717 nvmeq->cq_vector = 0;
1718 nvme_init_queue(nvmeq, 0);
1719 result = queue_request_irq(nvmeq);
1720 if (result) {
1721 dev->online_queues--;
1722 return result;
1723 }
1724
1725 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1726 return result;
1727 }
1728
1729 static int nvme_create_io_queues(struct nvme_dev *dev)
1730 {
1731 unsigned i, max, rw_queues;
1732 int ret = 0;
1733
1734 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1735 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1736 ret = -ENOMEM;
1737 break;
1738 }
1739 }
1740
1741 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1742 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1743 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1744 dev->io_queues[HCTX_TYPE_READ];
1745 } else {
1746 rw_queues = max;
1747 }
1748
1749 for (i = dev->online_queues; i <= max; i++) {
1750 bool polled = i > rw_queues;
1751
1752 ret = nvme_create_queue(&dev->queues[i], i, polled);
1753 if (ret)
1754 break;
1755 }
1756
1757
1758
1759
1760
1761
1762
1763 return ret >= 0 ? 0 : ret;
1764 }
1765
1766 static ssize_t nvme_cmb_show(struct device *dev,
1767 struct device_attribute *attr,
1768 char *buf)
1769 {
1770 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1771
1772 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1773 ndev->cmbloc, ndev->cmbsz);
1774 }
1775 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1776
1777 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1778 {
1779 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1780
1781 return 1ULL << (12 + 4 * szu);
1782 }
1783
1784 static u32 nvme_cmb_size(struct nvme_dev *dev)
1785 {
1786 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1787 }
1788
1789 static void nvme_map_cmb(struct nvme_dev *dev)
1790 {
1791 u64 size, offset;
1792 resource_size_t bar_size;
1793 struct pci_dev *pdev = to_pci_dev(dev->dev);
1794 int bar;
1795
1796 if (dev->cmb_size)
1797 return;
1798
1799 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1800 if (!dev->cmbsz)
1801 return;
1802 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1803
1804 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1805 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1806 bar = NVME_CMB_BIR(dev->cmbloc);
1807 bar_size = pci_resource_len(pdev, bar);
1808
1809 if (offset > bar_size)
1810 return;
1811
1812
1813
1814
1815
1816
1817 if (size > bar_size - offset)
1818 size = bar_size - offset;
1819
1820 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1821 dev_warn(dev->ctrl.device,
1822 "failed to register the CMB\n");
1823 return;
1824 }
1825
1826 dev->cmb_size = size;
1827 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1828
1829 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1830 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1831 pci_p2pmem_publish(pdev, true);
1832
1833 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1834 &dev_attr_cmb.attr, NULL))
1835 dev_warn(dev->ctrl.device,
1836 "failed to add sysfs attribute for CMB\n");
1837 }
1838
1839 static inline void nvme_release_cmb(struct nvme_dev *dev)
1840 {
1841 if (dev->cmb_size) {
1842 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1843 &dev_attr_cmb.attr, NULL);
1844 dev->cmb_size = 0;
1845 }
1846 }
1847
1848 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1849 {
1850 u64 dma_addr = dev->host_mem_descs_dma;
1851 struct nvme_command c;
1852 int ret;
1853
1854 memset(&c, 0, sizeof(c));
1855 c.features.opcode = nvme_admin_set_features;
1856 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1857 c.features.dword11 = cpu_to_le32(bits);
1858 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1859 ilog2(dev->ctrl.page_size));
1860 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1861 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1862 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1863
1864 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1865 if (ret) {
1866 dev_warn(dev->ctrl.device,
1867 "failed to set host mem (err %d, flags %#x).\n",
1868 ret, bits);
1869 }
1870 return ret;
1871 }
1872
1873 static void nvme_free_host_mem(struct nvme_dev *dev)
1874 {
1875 int i;
1876
1877 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1878 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1879 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1880
1881 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1882 le64_to_cpu(desc->addr),
1883 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1884 }
1885
1886 kfree(dev->host_mem_desc_bufs);
1887 dev->host_mem_desc_bufs = NULL;
1888 dma_free_coherent(dev->dev,
1889 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1890 dev->host_mem_descs, dev->host_mem_descs_dma);
1891 dev->host_mem_descs = NULL;
1892 dev->nr_host_mem_descs = 0;
1893 }
1894
1895 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1896 u32 chunk_size)
1897 {
1898 struct nvme_host_mem_buf_desc *descs;
1899 u32 max_entries, len;
1900 dma_addr_t descs_dma;
1901 int i = 0;
1902 void **bufs;
1903 u64 size, tmp;
1904
1905 tmp = (preferred + chunk_size - 1);
1906 do_div(tmp, chunk_size);
1907 max_entries = tmp;
1908
1909 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1910 max_entries = dev->ctrl.hmmaxd;
1911
1912 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1913 &descs_dma, GFP_KERNEL);
1914 if (!descs)
1915 goto out;
1916
1917 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1918 if (!bufs)
1919 goto out_free_descs;
1920
1921 for (size = 0; size < preferred && i < max_entries; size += len) {
1922 dma_addr_t dma_addr;
1923
1924 len = min_t(u64, chunk_size, preferred - size);
1925 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1926 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1927 if (!bufs[i])
1928 break;
1929
1930 descs[i].addr = cpu_to_le64(dma_addr);
1931 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1932 i++;
1933 }
1934
1935 if (!size)
1936 goto out_free_bufs;
1937
1938 dev->nr_host_mem_descs = i;
1939 dev->host_mem_size = size;
1940 dev->host_mem_descs = descs;
1941 dev->host_mem_descs_dma = descs_dma;
1942 dev->host_mem_desc_bufs = bufs;
1943 return 0;
1944
1945 out_free_bufs:
1946 while (--i >= 0) {
1947 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1948
1949 dma_free_attrs(dev->dev, size, bufs[i],
1950 le64_to_cpu(descs[i].addr),
1951 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1952 }
1953
1954 kfree(bufs);
1955 out_free_descs:
1956 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1957 descs_dma);
1958 out:
1959 dev->host_mem_descs = NULL;
1960 return -ENOMEM;
1961 }
1962
1963 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1964 {
1965 u32 chunk_size;
1966
1967
1968 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1969 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1970 chunk_size /= 2) {
1971 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1972 if (!min || dev->host_mem_size >= min)
1973 return 0;
1974 nvme_free_host_mem(dev);
1975 }
1976 }
1977
1978 return -ENOMEM;
1979 }
1980
1981 static int nvme_setup_host_mem(struct nvme_dev *dev)
1982 {
1983 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1984 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1985 u64 min = (u64)dev->ctrl.hmmin * 4096;
1986 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1987 int ret;
1988
1989 preferred = min(preferred, max);
1990 if (min > max) {
1991 dev_warn(dev->ctrl.device,
1992 "min host memory (%lld MiB) above limit (%d MiB).\n",
1993 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1994 nvme_free_host_mem(dev);
1995 return 0;
1996 }
1997
1998
1999
2000
2001 if (dev->host_mem_descs) {
2002 if (dev->host_mem_size >= min)
2003 enable_bits |= NVME_HOST_MEM_RETURN;
2004 else
2005 nvme_free_host_mem(dev);
2006 }
2007
2008 if (!dev->host_mem_descs) {
2009 if (nvme_alloc_host_mem(dev, min, preferred)) {
2010 dev_warn(dev->ctrl.device,
2011 "failed to allocate host memory buffer.\n");
2012 return 0;
2013 }
2014
2015 dev_info(dev->ctrl.device,
2016 "allocated %lld MiB host memory buffer.\n",
2017 dev->host_mem_size >> ilog2(SZ_1M));
2018 }
2019
2020 ret = nvme_set_host_mem(dev, enable_bits);
2021 if (ret)
2022 nvme_free_host_mem(dev);
2023 return ret;
2024 }
2025
2026
2027
2028
2029
2030 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2031 {
2032 struct nvme_dev *dev = affd->priv;
2033 unsigned int nr_read_queues;
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046 if (!nrirqs) {
2047 nrirqs = 1;
2048 nr_read_queues = 0;
2049 } else if (nrirqs == 1 || !write_queues) {
2050 nr_read_queues = 0;
2051 } else if (write_queues >= nrirqs) {
2052 nr_read_queues = 1;
2053 } else {
2054 nr_read_queues = nrirqs - write_queues;
2055 }
2056
2057 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2058 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2059 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2060 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2061 affd->nr_sets = nr_read_queues ? 2 : 1;
2062 }
2063
2064 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2065 {
2066 struct pci_dev *pdev = to_pci_dev(dev->dev);
2067 struct irq_affinity affd = {
2068 .pre_vectors = 1,
2069 .calc_sets = nvme_calc_irq_sets,
2070 .priv = dev,
2071 };
2072 unsigned int irq_queues, this_p_queues;
2073
2074
2075
2076
2077
2078 this_p_queues = poll_queues;
2079 if (this_p_queues >= nr_io_queues) {
2080 this_p_queues = nr_io_queues - 1;
2081 irq_queues = 1;
2082 } else {
2083 irq_queues = nr_io_queues - this_p_queues + 1;
2084 }
2085 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2086
2087
2088 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2089 dev->io_queues[HCTX_TYPE_READ] = 0;
2090
2091
2092
2093
2094
2095 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2096 irq_queues = 1;
2097
2098 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2099 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2100 }
2101
2102 static void nvme_disable_io_queues(struct nvme_dev *dev)
2103 {
2104 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2105 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2106 }
2107
2108 static int nvme_setup_io_queues(struct nvme_dev *dev)
2109 {
2110 struct nvme_queue *adminq = &dev->queues[0];
2111 struct pci_dev *pdev = to_pci_dev(dev->dev);
2112 int result, nr_io_queues;
2113 unsigned long size;
2114
2115 nr_io_queues = max_io_queues();
2116
2117
2118
2119
2120
2121 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2122 nr_io_queues = 1;
2123
2124 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2125 if (result < 0)
2126 return result;
2127
2128 if (nr_io_queues == 0)
2129 return 0;
2130
2131 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2132
2133 if (dev->cmb_use_sqes) {
2134 result = nvme_cmb_qdepth(dev, nr_io_queues,
2135 sizeof(struct nvme_command));
2136 if (result > 0)
2137 dev->q_depth = result;
2138 else
2139 dev->cmb_use_sqes = false;
2140 }
2141
2142 do {
2143 size = db_bar_size(dev, nr_io_queues);
2144 result = nvme_remap_bar(dev, size);
2145 if (!result)
2146 break;
2147 if (!--nr_io_queues)
2148 return -ENOMEM;
2149 } while (1);
2150 adminq->q_db = dev->dbs;
2151
2152 retry:
2153
2154 pci_free_irq(pdev, 0, adminq);
2155
2156
2157
2158
2159
2160 pci_free_irq_vectors(pdev);
2161
2162 result = nvme_setup_irqs(dev, nr_io_queues);
2163 if (result <= 0)
2164 return -EIO;
2165
2166 dev->num_vecs = result;
2167 result = max(result - 1, 1);
2168 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2169
2170
2171
2172
2173
2174
2175
2176 result = queue_request_irq(adminq);
2177 if (result)
2178 return result;
2179 set_bit(NVMEQ_ENABLED, &adminq->flags);
2180
2181 result = nvme_create_io_queues(dev);
2182 if (result || dev->online_queues < 2)
2183 return result;
2184
2185 if (dev->online_queues - 1 < dev->max_qid) {
2186 nr_io_queues = dev->online_queues - 1;
2187 nvme_disable_io_queues(dev);
2188 nvme_suspend_io_queues(dev);
2189 goto retry;
2190 }
2191 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2192 dev->io_queues[HCTX_TYPE_DEFAULT],
2193 dev->io_queues[HCTX_TYPE_READ],
2194 dev->io_queues[HCTX_TYPE_POLL]);
2195 return 0;
2196 }
2197
2198 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2199 {
2200 struct nvme_queue *nvmeq = req->end_io_data;
2201
2202 blk_mq_free_request(req);
2203 complete(&nvmeq->delete_done);
2204 }
2205
2206 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2207 {
2208 struct nvme_queue *nvmeq = req->end_io_data;
2209
2210 if (error)
2211 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2212
2213 nvme_del_queue_end(req, error);
2214 }
2215
2216 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2217 {
2218 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2219 struct request *req;
2220 struct nvme_command cmd;
2221
2222 memset(&cmd, 0, sizeof(cmd));
2223 cmd.delete_queue.opcode = opcode;
2224 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2225
2226 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2227 if (IS_ERR(req))
2228 return PTR_ERR(req);
2229
2230 req->timeout = ADMIN_TIMEOUT;
2231 req->end_io_data = nvmeq;
2232
2233 init_completion(&nvmeq->delete_done);
2234 blk_execute_rq_nowait(q, NULL, req, false,
2235 opcode == nvme_admin_delete_cq ?
2236 nvme_del_cq_end : nvme_del_queue_end);
2237 return 0;
2238 }
2239
2240 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2241 {
2242 int nr_queues = dev->online_queues - 1, sent = 0;
2243 unsigned long timeout;
2244
2245 retry:
2246 timeout = ADMIN_TIMEOUT;
2247 while (nr_queues > 0) {
2248 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2249 break;
2250 nr_queues--;
2251 sent++;
2252 }
2253 while (sent) {
2254 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2255
2256 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2257 timeout);
2258 if (timeout == 0)
2259 return false;
2260
2261 sent--;
2262 if (nr_queues)
2263 goto retry;
2264 }
2265 return true;
2266 }
2267
2268 static void nvme_dev_add(struct nvme_dev *dev)
2269 {
2270 int ret;
2271
2272 if (!dev->ctrl.tagset) {
2273 dev->tagset.ops = &nvme_mq_ops;
2274 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2275 dev->tagset.nr_maps = 2;
2276 if (dev->io_queues[HCTX_TYPE_POLL])
2277 dev->tagset.nr_maps++;
2278 dev->tagset.timeout = NVME_IO_TIMEOUT;
2279 dev->tagset.numa_node = dev_to_node(dev->dev);
2280 dev->tagset.queue_depth =
2281 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2282 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2283 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2284 dev->tagset.driver_data = dev;
2285
2286
2287
2288
2289
2290
2291 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2292 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2293
2294 ret = blk_mq_alloc_tag_set(&dev->tagset);
2295 if (ret) {
2296 dev_warn(dev->ctrl.device,
2297 "IO queues tagset allocation failed %d\n", ret);
2298 return;
2299 }
2300 dev->ctrl.tagset = &dev->tagset;
2301 } else {
2302 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2303
2304
2305 nvme_free_queues(dev, dev->online_queues);
2306 }
2307
2308 nvme_dbbuf_set(dev);
2309 }
2310
2311 static int nvme_pci_enable(struct nvme_dev *dev)
2312 {
2313 int result = -ENOMEM;
2314 struct pci_dev *pdev = to_pci_dev(dev->dev);
2315
2316 if (pci_enable_device_mem(pdev))
2317 return result;
2318
2319 pci_set_master(pdev);
2320
2321 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2322 goto disable;
2323
2324 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2325 result = -ENODEV;
2326 goto disable;
2327 }
2328
2329
2330
2331
2332
2333
2334 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2335 if (result < 0)
2336 return result;
2337
2338 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2339
2340 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2341 io_queue_depth);
2342 dev->ctrl.sqsize = dev->q_depth - 1;
2343 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2344 dev->dbs = dev->bar + 4096;
2345
2346
2347
2348
2349
2350
2351 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2352 dev->io_sqes = 7;
2353 else
2354 dev->io_sqes = NVME_NVM_IOSQES;
2355
2356
2357
2358
2359
2360 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2361 dev->q_depth = 2;
2362 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2363 "set queue depth=%u to work around controller resets\n",
2364 dev->q_depth);
2365 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2366 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2367 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2368 dev->q_depth = 64;
2369 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2370 "set queue depth=%u\n", dev->q_depth);
2371 }
2372
2373
2374
2375
2376
2377 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2378 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2379 dev->q_depth = NVME_AQ_DEPTH + 2;
2380 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2381 dev->q_depth);
2382 }
2383
2384
2385 nvme_map_cmb(dev);
2386
2387 pci_enable_pcie_error_reporting(pdev);
2388 pci_save_state(pdev);
2389 return 0;
2390
2391 disable:
2392 pci_disable_device(pdev);
2393 return result;
2394 }
2395
2396 static void nvme_dev_unmap(struct nvme_dev *dev)
2397 {
2398 if (dev->bar)
2399 iounmap(dev->bar);
2400 pci_release_mem_regions(to_pci_dev(dev->dev));
2401 }
2402
2403 static void nvme_pci_disable(struct nvme_dev *dev)
2404 {
2405 struct pci_dev *pdev = to_pci_dev(dev->dev);
2406
2407 pci_free_irq_vectors(pdev);
2408
2409 if (pci_is_enabled(pdev)) {
2410 pci_disable_pcie_error_reporting(pdev);
2411 pci_disable_device(pdev);
2412 }
2413 }
2414
2415 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2416 {
2417 bool dead = true, freeze = false;
2418 struct pci_dev *pdev = to_pci_dev(dev->dev);
2419
2420 mutex_lock(&dev->shutdown_lock);
2421 if (pci_is_enabled(pdev)) {
2422 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2423
2424 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2425 dev->ctrl.state == NVME_CTRL_RESETTING) {
2426 freeze = true;
2427 nvme_start_freeze(&dev->ctrl);
2428 }
2429 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2430 pdev->error_state != pci_channel_io_normal);
2431 }
2432
2433
2434
2435
2436
2437 if (!dead && shutdown && freeze)
2438 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2439
2440 nvme_stop_queues(&dev->ctrl);
2441
2442 if (!dead && dev->ctrl.queue_count > 0) {
2443 nvme_disable_io_queues(dev);
2444 nvme_disable_admin_queue(dev, shutdown);
2445 }
2446 nvme_suspend_io_queues(dev);
2447 nvme_suspend_queue(&dev->queues[0]);
2448 nvme_pci_disable(dev);
2449 nvme_reap_pending_cqes(dev);
2450
2451 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2452 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2453 blk_mq_tagset_wait_completed_request(&dev->tagset);
2454 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2455
2456
2457
2458
2459
2460
2461 if (shutdown) {
2462 nvme_start_queues(&dev->ctrl);
2463 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2464 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2465 }
2466 mutex_unlock(&dev->shutdown_lock);
2467 }
2468
2469 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2470 {
2471 if (!nvme_wait_reset(&dev->ctrl))
2472 return -EBUSY;
2473 nvme_dev_disable(dev, shutdown);
2474 return 0;
2475 }
2476
2477 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2478 {
2479 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2480 PAGE_SIZE, PAGE_SIZE, 0);
2481 if (!dev->prp_page_pool)
2482 return -ENOMEM;
2483
2484
2485 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2486 256, 256, 0);
2487 if (!dev->prp_small_pool) {
2488 dma_pool_destroy(dev->prp_page_pool);
2489 return -ENOMEM;
2490 }
2491 return 0;
2492 }
2493
2494 static void nvme_release_prp_pools(struct nvme_dev *dev)
2495 {
2496 dma_pool_destroy(dev->prp_page_pool);
2497 dma_pool_destroy(dev->prp_small_pool);
2498 }
2499
2500 static void nvme_free_tagset(struct nvme_dev *dev)
2501 {
2502 if (dev->tagset.tags)
2503 blk_mq_free_tag_set(&dev->tagset);
2504 dev->ctrl.tagset = NULL;
2505 }
2506
2507 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2508 {
2509 struct nvme_dev *dev = to_nvme_dev(ctrl);
2510
2511 nvme_dbbuf_dma_free(dev);
2512 put_device(dev->dev);
2513 nvme_free_tagset(dev);
2514 if (dev->ctrl.admin_q)
2515 blk_put_queue(dev->ctrl.admin_q);
2516 kfree(dev->queues);
2517 free_opal_dev(dev->ctrl.opal_dev);
2518 mempool_destroy(dev->iod_mempool);
2519 kfree(dev);
2520 }
2521
2522 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2523 {
2524
2525
2526
2527
2528 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2529 nvme_get_ctrl(&dev->ctrl);
2530 nvme_dev_disable(dev, false);
2531 nvme_kill_queues(&dev->ctrl);
2532 if (!queue_work(nvme_wq, &dev->remove_work))
2533 nvme_put_ctrl(&dev->ctrl);
2534 }
2535
2536 static void nvme_reset_work(struct work_struct *work)
2537 {
2538 struct nvme_dev *dev =
2539 container_of(work, struct nvme_dev, ctrl.reset_work);
2540 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2541 int result;
2542
2543 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2544 result = -ENODEV;
2545 goto out;
2546 }
2547
2548
2549
2550
2551
2552 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2553 nvme_dev_disable(dev, false);
2554 nvme_sync_queues(&dev->ctrl);
2555
2556 mutex_lock(&dev->shutdown_lock);
2557 result = nvme_pci_enable(dev);
2558 if (result)
2559 goto out_unlock;
2560
2561 result = nvme_pci_configure_admin_queue(dev);
2562 if (result)
2563 goto out_unlock;
2564
2565 result = nvme_alloc_admin_tags(dev);
2566 if (result)
2567 goto out_unlock;
2568
2569
2570
2571
2572
2573 dev->ctrl.max_hw_sectors = min_t(u32,
2574 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2575 dev->ctrl.max_segments = NVME_MAX_SEGS;
2576
2577
2578
2579
2580 dma_set_max_seg_size(dev->dev, 0xffffffff);
2581
2582 mutex_unlock(&dev->shutdown_lock);
2583
2584
2585
2586
2587
2588 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2589 dev_warn(dev->ctrl.device,
2590 "failed to mark controller CONNECTING\n");
2591 result = -EBUSY;
2592 goto out;
2593 }
2594
2595 result = nvme_init_identify(&dev->ctrl);
2596 if (result)
2597 goto out;
2598
2599 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2600 if (!dev->ctrl.opal_dev)
2601 dev->ctrl.opal_dev =
2602 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2603 else if (was_suspend)
2604 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2605 } else {
2606 free_opal_dev(dev->ctrl.opal_dev);
2607 dev->ctrl.opal_dev = NULL;
2608 }
2609
2610 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2611 result = nvme_dbbuf_dma_alloc(dev);
2612 if (result)
2613 dev_warn(dev->dev,
2614 "unable to allocate dma for dbbuf\n");
2615 }
2616
2617 if (dev->ctrl.hmpre) {
2618 result = nvme_setup_host_mem(dev);
2619 if (result < 0)
2620 goto out;
2621 }
2622
2623 result = nvme_setup_io_queues(dev);
2624 if (result)
2625 goto out;
2626
2627
2628
2629
2630
2631 if (dev->online_queues < 2) {
2632 dev_warn(dev->ctrl.device, "IO queues not created\n");
2633 nvme_kill_queues(&dev->ctrl);
2634 nvme_remove_namespaces(&dev->ctrl);
2635 nvme_free_tagset(dev);
2636 } else {
2637 nvme_start_queues(&dev->ctrl);
2638 nvme_wait_freeze(&dev->ctrl);
2639 nvme_dev_add(dev);
2640 nvme_unfreeze(&dev->ctrl);
2641 }
2642
2643
2644
2645
2646
2647 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2648 dev_warn(dev->ctrl.device,
2649 "failed to mark controller live state\n");
2650 result = -ENODEV;
2651 goto out;
2652 }
2653
2654 nvme_start_ctrl(&dev->ctrl);
2655 return;
2656
2657 out_unlock:
2658 mutex_unlock(&dev->shutdown_lock);
2659 out:
2660 if (result)
2661 dev_warn(dev->ctrl.device,
2662 "Removing after probe failure status: %d\n", result);
2663 nvme_remove_dead_ctrl(dev);
2664 }
2665
2666 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2667 {
2668 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2669 struct pci_dev *pdev = to_pci_dev(dev->dev);
2670
2671 if (pci_get_drvdata(pdev))
2672 device_release_driver(&pdev->dev);
2673 nvme_put_ctrl(&dev->ctrl);
2674 }
2675
2676 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2677 {
2678 *val = readl(to_nvme_dev(ctrl)->bar + off);
2679 return 0;
2680 }
2681
2682 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2683 {
2684 writel(val, to_nvme_dev(ctrl)->bar + off);
2685 return 0;
2686 }
2687
2688 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2689 {
2690 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2691 return 0;
2692 }
2693
2694 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2695 {
2696 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2697
2698 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2699 }
2700
2701 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2702 .name = "pcie",
2703 .module = THIS_MODULE,
2704 .flags = NVME_F_METADATA_SUPPORTED |
2705 NVME_F_PCI_P2PDMA,
2706 .reg_read32 = nvme_pci_reg_read32,
2707 .reg_write32 = nvme_pci_reg_write32,
2708 .reg_read64 = nvme_pci_reg_read64,
2709 .free_ctrl = nvme_pci_free_ctrl,
2710 .submit_async_event = nvme_pci_submit_async_event,
2711 .get_address = nvme_pci_get_address,
2712 };
2713
2714 static int nvme_dev_map(struct nvme_dev *dev)
2715 {
2716 struct pci_dev *pdev = to_pci_dev(dev->dev);
2717
2718 if (pci_request_mem_regions(pdev, "nvme"))
2719 return -ENODEV;
2720
2721 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2722 goto release;
2723
2724 return 0;
2725 release:
2726 pci_release_mem_regions(pdev);
2727 return -ENODEV;
2728 }
2729
2730 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2731 {
2732 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2733
2734
2735
2736
2737
2738
2739
2740
2741 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2742 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2743 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2744 return NVME_QUIRK_NO_DEEPEST_PS;
2745 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2746
2747
2748
2749
2750
2751
2752 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2753 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2754 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2755 return NVME_QUIRK_NO_APST;
2756 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2757 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2758 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2759
2760
2761
2762
2763
2764
2765 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2766 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2767 return NVME_QUIRK_SIMPLE_SUSPEND;
2768 }
2769
2770 return 0;
2771 }
2772
2773 static void nvme_async_probe(void *data, async_cookie_t cookie)
2774 {
2775 struct nvme_dev *dev = data;
2776
2777 flush_work(&dev->ctrl.reset_work);
2778 flush_work(&dev->ctrl.scan_work);
2779 nvme_put_ctrl(&dev->ctrl);
2780 }
2781
2782 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2783 {
2784 int node, result = -ENOMEM;
2785 struct nvme_dev *dev;
2786 unsigned long quirks = id->driver_data;
2787 size_t alloc_size;
2788
2789 node = dev_to_node(&pdev->dev);
2790 if (node == NUMA_NO_NODE)
2791 set_dev_node(&pdev->dev, first_memory_node);
2792
2793 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2794 if (!dev)
2795 return -ENOMEM;
2796
2797 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2798 GFP_KERNEL, node);
2799 if (!dev->queues)
2800 goto free;
2801
2802 dev->dev = get_device(&pdev->dev);
2803 pci_set_drvdata(pdev, dev);
2804
2805 result = nvme_dev_map(dev);
2806 if (result)
2807 goto put_pci;
2808
2809 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2810 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2811 mutex_init(&dev->shutdown_lock);
2812
2813 result = nvme_setup_prp_pools(dev);
2814 if (result)
2815 goto unmap;
2816
2817 quirks |= check_vendor_combination_bug(pdev);
2818
2819
2820
2821
2822
2823 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2824 NVME_MAX_SEGS, true);
2825 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2826
2827 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2828 mempool_kfree,
2829 (void *) alloc_size,
2830 GFP_KERNEL, node);
2831 if (!dev->iod_mempool) {
2832 result = -ENOMEM;
2833 goto release_pools;
2834 }
2835
2836 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2837 quirks);
2838 if (result)
2839 goto release_mempool;
2840
2841 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2842
2843 nvme_reset_ctrl(&dev->ctrl);
2844 nvme_get_ctrl(&dev->ctrl);
2845 async_schedule(nvme_async_probe, dev);
2846
2847 return 0;
2848
2849 release_mempool:
2850 mempool_destroy(dev->iod_mempool);
2851 release_pools:
2852 nvme_release_prp_pools(dev);
2853 unmap:
2854 nvme_dev_unmap(dev);
2855 put_pci:
2856 put_device(dev->dev);
2857 free:
2858 kfree(dev->queues);
2859 kfree(dev);
2860 return result;
2861 }
2862
2863 static void nvme_reset_prepare(struct pci_dev *pdev)
2864 {
2865 struct nvme_dev *dev = pci_get_drvdata(pdev);
2866
2867
2868
2869
2870
2871
2872 nvme_disable_prepare_reset(dev, false);
2873 nvme_sync_queues(&dev->ctrl);
2874 }
2875
2876 static void nvme_reset_done(struct pci_dev *pdev)
2877 {
2878 struct nvme_dev *dev = pci_get_drvdata(pdev);
2879
2880 if (!nvme_try_sched_reset(&dev->ctrl))
2881 flush_work(&dev->ctrl.reset_work);
2882 }
2883
2884 static void nvme_shutdown(struct pci_dev *pdev)
2885 {
2886 struct nvme_dev *dev = pci_get_drvdata(pdev);
2887 nvme_disable_prepare_reset(dev, true);
2888 }
2889
2890
2891
2892
2893
2894
2895 static void nvme_remove(struct pci_dev *pdev)
2896 {
2897 struct nvme_dev *dev = pci_get_drvdata(pdev);
2898
2899 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2900 pci_set_drvdata(pdev, NULL);
2901
2902 if (!pci_device_is_present(pdev)) {
2903 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2904 nvme_dev_disable(dev, true);
2905 nvme_dev_remove_admin(dev);
2906 }
2907
2908 flush_work(&dev->ctrl.reset_work);
2909 nvme_stop_ctrl(&dev->ctrl);
2910 nvme_remove_namespaces(&dev->ctrl);
2911 nvme_dev_disable(dev, true);
2912 nvme_release_cmb(dev);
2913 nvme_free_host_mem(dev);
2914 nvme_dev_remove_admin(dev);
2915 nvme_free_queues(dev, 0);
2916 nvme_uninit_ctrl(&dev->ctrl);
2917 nvme_release_prp_pools(dev);
2918 nvme_dev_unmap(dev);
2919 nvme_put_ctrl(&dev->ctrl);
2920 }
2921
2922 #ifdef CONFIG_PM_SLEEP
2923 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2924 {
2925 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2926 }
2927
2928 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2929 {
2930 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2931 }
2932
2933 static int nvme_resume(struct device *dev)
2934 {
2935 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2936 struct nvme_ctrl *ctrl = &ndev->ctrl;
2937
2938 if (ndev->last_ps == U32_MAX ||
2939 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2940 return nvme_try_sched_reset(&ndev->ctrl);
2941 return 0;
2942 }
2943
2944 static int nvme_suspend(struct device *dev)
2945 {
2946 struct pci_dev *pdev = to_pci_dev(dev);
2947 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2948 struct nvme_ctrl *ctrl = &ndev->ctrl;
2949 int ret = -EBUSY;
2950
2951 ndev->last_ps = U32_MAX;
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966 if (pm_suspend_via_firmware() || !ctrl->npss ||
2967 !pcie_aspm_enabled(pdev) ||
2968 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2969 return nvme_disable_prepare_reset(ndev, true);
2970
2971 nvme_start_freeze(ctrl);
2972 nvme_wait_freeze(ctrl);
2973 nvme_sync_queues(ctrl);
2974
2975 if (ctrl->state != NVME_CTRL_LIVE)
2976 goto unfreeze;
2977
2978 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2979 if (ret < 0)
2980 goto unfreeze;
2981
2982
2983
2984
2985
2986
2987 pci_save_state(pdev);
2988
2989 ret = nvme_set_power_state(ctrl, ctrl->npss);
2990 if (ret < 0)
2991 goto unfreeze;
2992
2993 if (ret) {
2994
2995 pci_load_saved_state(pdev, NULL);
2996
2997
2998
2999
3000
3001 ret = nvme_disable_prepare_reset(ndev, true);
3002 ctrl->npss = 0;
3003 }
3004 unfreeze:
3005 nvme_unfreeze(ctrl);
3006 return ret;
3007 }
3008
3009 static int nvme_simple_suspend(struct device *dev)
3010 {
3011 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3012 return nvme_disable_prepare_reset(ndev, true);
3013 }
3014
3015 static int nvme_simple_resume(struct device *dev)
3016 {
3017 struct pci_dev *pdev = to_pci_dev(dev);
3018 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3019
3020 return nvme_try_sched_reset(&ndev->ctrl);
3021 }
3022
3023 static const struct dev_pm_ops nvme_dev_pm_ops = {
3024 .suspend = nvme_suspend,
3025 .resume = nvme_resume,
3026 .freeze = nvme_simple_suspend,
3027 .thaw = nvme_simple_resume,
3028 .poweroff = nvme_simple_suspend,
3029 .restore = nvme_simple_resume,
3030 };
3031 #endif
3032
3033 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3034 pci_channel_state_t state)
3035 {
3036 struct nvme_dev *dev = pci_get_drvdata(pdev);
3037
3038
3039
3040
3041
3042
3043 switch (state) {
3044 case pci_channel_io_normal:
3045 return PCI_ERS_RESULT_CAN_RECOVER;
3046 case pci_channel_io_frozen:
3047 dev_warn(dev->ctrl.device,
3048 "frozen state error detected, reset controller\n");
3049 nvme_dev_disable(dev, false);
3050 return PCI_ERS_RESULT_NEED_RESET;
3051 case pci_channel_io_perm_failure:
3052 dev_warn(dev->ctrl.device,
3053 "failure state error detected, request disconnect\n");
3054 return PCI_ERS_RESULT_DISCONNECT;
3055 }
3056 return PCI_ERS_RESULT_NEED_RESET;
3057 }
3058
3059 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3060 {
3061 struct nvme_dev *dev = pci_get_drvdata(pdev);
3062
3063 dev_info(dev->ctrl.device, "restart after slot reset\n");
3064 pci_restore_state(pdev);
3065 nvme_reset_ctrl(&dev->ctrl);
3066 return PCI_ERS_RESULT_RECOVERED;
3067 }
3068
3069 static void nvme_error_resume(struct pci_dev *pdev)
3070 {
3071 struct nvme_dev *dev = pci_get_drvdata(pdev);
3072
3073 flush_work(&dev->ctrl.reset_work);
3074 }
3075
3076 static const struct pci_error_handlers nvme_err_handler = {
3077 .error_detected = nvme_error_detected,
3078 .slot_reset = nvme_slot_reset,
3079 .resume = nvme_error_resume,
3080 .reset_prepare = nvme_reset_prepare,
3081 .reset_done = nvme_reset_done,
3082 };
3083
3084 static const struct pci_device_id nvme_id_table[] = {
3085 { PCI_VDEVICE(INTEL, 0x0953),
3086 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3087 NVME_QUIRK_DEALLOCATE_ZEROES, },
3088 { PCI_VDEVICE(INTEL, 0x0a53),
3089 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3090 NVME_QUIRK_DEALLOCATE_ZEROES, },
3091 { PCI_VDEVICE(INTEL, 0x0a54),
3092 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3093 NVME_QUIRK_DEALLOCATE_ZEROES, },
3094 { PCI_VDEVICE(INTEL, 0x0a55),
3095 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3096 NVME_QUIRK_DEALLOCATE_ZEROES, },
3097 { PCI_VDEVICE(INTEL, 0xf1a5),
3098 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3099 NVME_QUIRK_MEDIUM_PRIO_SQ },
3100 { PCI_VDEVICE(INTEL, 0xf1a6),
3101 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3102 { PCI_VDEVICE(INTEL, 0x5845),
3103 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3104 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3105 { PCI_DEVICE(0x1bb1, 0x0100),
3106 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3107 { PCI_DEVICE(0x1c58, 0x0003),
3108 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3109 { PCI_DEVICE(0x1c58, 0x0023),
3110 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3111 { PCI_DEVICE(0x1c5f, 0x0540),
3112 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3113 { PCI_DEVICE(0x144d, 0xa821),
3114 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3115 { PCI_DEVICE(0x144d, 0xa822),
3116 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3117 { PCI_DEVICE(0x1d1d, 0x1f1f),
3118 .driver_data = NVME_QUIRK_LIGHTNVM, },
3119 { PCI_DEVICE(0x1d1d, 0x2807),
3120 .driver_data = NVME_QUIRK_LIGHTNVM, },
3121 { PCI_DEVICE(0x1d1d, 0x2601),
3122 .driver_data = NVME_QUIRK_LIGHTNVM, },
3123 { PCI_DEVICE(0x10ec, 0x5762),
3124 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3125 { PCI_DEVICE(0x1cc1, 0x8201),
3126 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3127 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3128 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3129 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3130 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3131 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3132 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3133 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3134 NVME_QUIRK_128_BYTES_SQES |
3135 NVME_QUIRK_SHARED_TAGS },
3136 { 0, }
3137 };
3138 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3139
3140 static struct pci_driver nvme_driver = {
3141 .name = "nvme",
3142 .id_table = nvme_id_table,
3143 .probe = nvme_probe,
3144 .remove = nvme_remove,
3145 .shutdown = nvme_shutdown,
3146 #ifdef CONFIG_PM_SLEEP
3147 .driver = {
3148 .pm = &nvme_dev_pm_ops,
3149 },
3150 #endif
3151 .sriov_configure = pci_sriov_configure_simple,
3152 .err_handler = &nvme_err_handler,
3153 };
3154
3155 static int __init nvme_init(void)
3156 {
3157 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3158 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3159 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3160 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3161 return pci_register_driver(&nvme_driver);
3162 }
3163
3164 static void __exit nvme_exit(void)
3165 {
3166 pci_unregister_driver(&nvme_driver);
3167 flush_workqueue(nvme_wq);
3168 }
3169
3170 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3171 MODULE_LICENSE("GPL");
3172 MODULE_VERSION("1.0");
3173 module_init(nvme_init);
3174 module_exit(nvme_exit);