drivers/parisc/dino.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
DINO_DEV
pci_dev_is_behind_card_dino
dino_cfg_read
dino_cfg_write
dino_mask_irq
dino_unmask_irq
dino_isr
dino_assign_irq
dino_choose_irq
quirk_cirrus_cardbus
pci_fixup_tulip
dino_bios_init
dino_card_setup
dino_card_fixup
dino_fixup_bus
dino_card_init
dino_bridge_init
dino_common_init
dino_probe
dino_init
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3 **      DINO manager
   4 **
   5 **      (c) Copyright 1999 Red Hat Software
   6 **      (c) Copyright 1999 SuSE GmbH
   7 **      (c) Copyright 1999,2000 Hewlett-Packard Company
   8 **      (c) Copyright 2000 Grant Grundler
   9 **      (c) Copyright 2006-2019 Helge Deller
  10 **
  11 **
  12 **      This module provides access to Dino PCI bus (config/IOport spaces)
  13 **      and helps manage Dino IRQ lines.
  14 **
  15 **      Dino interrupt handling is a bit complicated.
  16 **      Dino always writes to the broadcast EIR via irr0 for now.
  17 **      (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
  18 **      Only one processor interrupt is used for the 11 IRQ line 
  19 **      inputs to dino.
  20 **
  21 **      The different between Built-in Dino and Card-Mode
  22 **      dino is in chip initialization and pci device initialization.
  23 **
  24 **      Linux drivers can only use Card-Mode Dino if pci devices I/O port
  25 **      BARs are configured and used by the driver. Programming MMIO address 
  26 **      requires substantial knowledge of available Host I/O address ranges
  27 **      is currently not supported.  Port/Config accessor functions are the
  28 **      same. "BIOS" differences are handled within the existing routines.
  29 */
  30 
  31 /*      Changes :
  32 **      2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
  33 **              - added support for the integrated RS232.       
  34 */
  35 
  36 /*
  37 ** TODO: create a virtual address for each Dino HPA.
  38 **       GSC code might be able to do this since IODC data tells us
  39 **       how many pages are used. PCI subsystem could (must?) do this
  40 **       for PCI drivers devices which implement/use MMIO registers.
  41 */
  42 
  43 #include <linux/delay.h>
  44 #include <linux/types.h>
  45 #include <linux/kernel.h>
  46 #include <linux/pci.h>
  47 #include <linux/init.h>
  48 #include <linux/ioport.h>
  49 #include <linux/slab.h>
  50 #include <linux/interrupt.h>    /* for struct irqaction */
  51 #include <linux/spinlock.h>     /* for spinlock_t and prototypes */
  52 
  53 #include <asm/pdc.h>
  54 #include <asm/page.h>
  55 #include <asm/io.h>
  56 #include <asm/hardware.h>
  57 
  58 #include "gsc.h"
  59 #include "iommu.h"
  60 
  61 #undef DINO_DEBUG
  62 
  63 #ifdef DINO_DEBUG
  64 #define DBG(x...) printk(x)
  65 #else
  66 #define DBG(x...)
  67 #endif
  68 
  69 /*
  70 ** Config accessor functions only pass in the 8-bit bus number
  71 ** and not the 8-bit "PCI Segment" number. Each Dino will be
  72 ** assigned a PCI bus number based on "when" it's discovered.
  73 **
  74 ** The "secondary" bus number is set to this before calling
  75 ** pci_scan_bus(). If any PPB's are present, the scan will
  76 ** discover them and update the "secondary" and "subordinate"
  77 ** fields in Dino's pci_bus structure.
  78 **
  79 ** Changes in the configuration *will* result in a different
  80 ** bus number for each dino.
  81 */
  82 
  83 #define is_card_dino(id)        ((id)->hw_type == HPHW_A_DMA)
  84 #define is_cujo(id)             ((id)->hversion == 0x682)
  85 
  86 #define DINO_IAR0               0x004
  87 #define DINO_IODC_ADDR          0x008
  88 #define DINO_IODC_DATA_0        0x008
  89 #define DINO_IODC_DATA_1        0x008
  90 #define DINO_IRR0               0x00C
  91 #define DINO_IAR1               0x010
  92 #define DINO_IRR1               0x014
  93 #define DINO_IMR                0x018
  94 #define DINO_IPR                0x01C
  95 #define DINO_TOC_ADDR           0x020
  96 #define DINO_ICR                0x024
  97 #define DINO_ILR                0x028
  98 #define DINO_IO_COMMAND         0x030
  99 #define DINO_IO_STATUS          0x034
 100 #define DINO_IO_CONTROL         0x038
 101 #define DINO_IO_GSC_ERR_RESP    0x040
 102 #define DINO_IO_ERR_INFO        0x044
 103 #define DINO_IO_PCI_ERR_RESP    0x048
 104 #define DINO_IO_FBB_EN          0x05c
 105 #define DINO_IO_ADDR_EN         0x060
 106 #define DINO_PCI_ADDR           0x064
 107 #define DINO_CONFIG_DATA        0x068
 108 #define DINO_IO_DATA            0x06c
 109 #define DINO_MEM_DATA           0x070   /* Dino 3.x only */
 110 #define DINO_GSC2X_CONFIG       0x7b4
 111 #define DINO_GMASK              0x800
 112 #define DINO_PAMR               0x804
 113 #define DINO_PAPR               0x808
 114 #define DINO_DAMODE             0x80c
 115 #define DINO_PCICMD             0x810
 116 #define DINO_PCISTS             0x814
 117 #define DINO_MLTIM              0x81c
 118 #define DINO_BRDG_FEAT          0x820
 119 #define DINO_PCIROR             0x824
 120 #define DINO_PCIWOR             0x828
 121 #define DINO_TLTIM              0x830
 122 
 123 #define DINO_IRQS 11            /* bits 0-10 are architected */
 124 #define DINO_IRR_MASK   0x5ff   /* only 10 bits are implemented */
 125 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
 126 
 127 #define DINO_MASK_IRQ(x)        (1<<(x))
 128 
 129 #define PCIINTA   0x001
 130 #define PCIINTB   0x002
 131 #define PCIINTC   0x004
 132 #define PCIINTD   0x008
 133 #define PCIINTE   0x010
 134 #define PCIINTF   0x020
 135 #define GSCEXTINT 0x040
 136 /* #define xxx       0x080 - bit 7 is "default" */
 137 /* #define xxx    0x100 - bit 8 not used */
 138 /* #define xxx    0x200 - bit 9 not used */
 139 #define RS232INT  0x400
 140 
 141 struct dino_device
 142 {
 143         struct pci_hba_data     hba;    /* 'C' inheritance - must be first */
 144         spinlock_t              dinosaur_pen;
 145         unsigned long           txn_addr; /* EIR addr to generate interrupt */ 
 146         u32                     txn_data; /* EIR data assign to each dino */ 
 147         u32                     imr;      /* IRQ's which are enabled */ 
 148         int                     global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
 149 #ifdef DINO_DEBUG
 150         unsigned int            dino_irr0; /* save most recent IRQ line stat */
 151 #endif
 152 };
 153 
 154 static inline struct dino_device *DINO_DEV(struct pci_hba_data *hba)
 155 {
 156         return container_of(hba, struct dino_device, hba);
 157 }
 158 
 159 /* Check if PCI device is behind a Card-mode Dino. */
 160 static int pci_dev_is_behind_card_dino(struct pci_dev *dev)
 161 {
 162         struct dino_device *dino_dev;
 163 
 164         dino_dev = DINO_DEV(parisc_walk_tree(dev->bus->bridge));
 165         return is_card_dino(&dino_dev->hba.dev->id);
 166 }
 167 
 168 /*
 169  * Dino Configuration Space Accessor Functions
 170  */
 171 
 172 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
 173 
 174 /*
 175  * keep the current highest bus count to assist in allocating busses.  This
 176  * tries to keep a global bus count total so that when we discover an 
 177  * entirely new bus, it can be given a unique bus number.
 178  */
 179 static int dino_current_bus = 0;
 180 
 181 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
 182                 int size, u32 *val)
 183 {
 184         struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 185         u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 186         u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 187         void __iomem *base_addr = d->hba.base_addr;
 188         unsigned long flags;
 189 
 190         DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
 191                                                                         size);
 192         spin_lock_irqsave(&d->dinosaur_pen, flags);
 193 
 194         /* tell HW which CFG address */
 195         __raw_writel(v, base_addr + DINO_PCI_ADDR);
 196 
 197         /* generate cfg read cycle */
 198         if (size == 1) {
 199                 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
 200         } else if (size == 2) {
 201                 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
 202         } else if (size == 4) {
 203                 *val = readl(base_addr + DINO_CONFIG_DATA);
 204         }
 205 
 206         spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 207         return 0;
 208 }
 209 
 210 /*
 211  * Dino address stepping "feature":
 212  * When address stepping, Dino attempts to drive the bus one cycle too soon
 213  * even though the type of cycle (config vs. MMIO) might be different. 
 214  * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
 215  */
 216 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
 217         int size, u32 val)
 218 {
 219         struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 220         u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 221         u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 222         void __iomem *base_addr = d->hba.base_addr;
 223         unsigned long flags;
 224 
 225         DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
 226                                                                         size);
 227         spin_lock_irqsave(&d->dinosaur_pen, flags);
 228 
 229         /* avoid address stepping feature */
 230         __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
 231         __raw_readl(base_addr + DINO_CONFIG_DATA);
 232 
 233         /* tell HW which CFG address */
 234         __raw_writel(v, base_addr + DINO_PCI_ADDR);
 235         /* generate cfg read cycle */
 236         if (size == 1) {
 237                 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
 238         } else if (size == 2) {
 239                 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
 240         } else if (size == 4) {
 241                 writel(val, base_addr + DINO_CONFIG_DATA);
 242         }
 243 
 244         spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 245         return 0;
 246 }
 247 
 248 static struct pci_ops dino_cfg_ops = {
 249         .read =         dino_cfg_read,
 250         .write =        dino_cfg_write,
 251 };
 252 
 253 
 254 /*
 255  * Dino "I/O Port" Space Accessor Functions
 256  *
 257  * Many PCI devices don't require use of I/O port space (eg Tulip,
 258  * NCR720) since they export the same registers to both MMIO and
 259  * I/O port space.  Performance is going to stink if drivers use
 260  * I/O port instead of MMIO.
 261  */
 262 
 263 #define DINO_PORT_IN(type, size, mask) \
 264 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
 265 { \
 266         u##size v; \
 267         unsigned long flags; \
 268         spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 269         /* tell HW which IO Port address */ \
 270         __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 271         /* generate I/O PORT read cycle */ \
 272         v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
 273         spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 274         return v; \
 275 }
 276 
 277 DINO_PORT_IN(b,  8, 3)
 278 DINO_PORT_IN(w, 16, 2)
 279 DINO_PORT_IN(l, 32, 0)
 280 
 281 #define DINO_PORT_OUT(type, size, mask) \
 282 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
 283 { \
 284         unsigned long flags; \
 285         spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 286         /* tell HW which IO port address */ \
 287         __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 288         /* generate cfg write cycle */ \
 289         write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
 290         spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 291 }
 292 
 293 DINO_PORT_OUT(b,  8, 3)
 294 DINO_PORT_OUT(w, 16, 2)
 295 DINO_PORT_OUT(l, 32, 0)
 296 
 297 static struct pci_port_ops dino_port_ops = {
 298         .inb    = dino_in8,
 299         .inw    = dino_in16,
 300         .inl    = dino_in32,
 301         .outb   = dino_out8,
 302         .outw   = dino_out16,
 303         .outl   = dino_out32
 304 };
 305 
 306 static void dino_mask_irq(struct irq_data *d)
 307 {
 308         struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
 309         int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 310 
 311         DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
 312 
 313         /* Clear the matching bit in the IMR register */
 314         dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
 315         __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 316 }
 317 
 318 static void dino_unmask_irq(struct irq_data *d)
 319 {
 320         struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
 321         int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 322         u32 tmp;
 323 
 324         DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
 325 
 326         /*
 327         ** clear pending IRQ bits
 328         **
 329         ** This does NOT change ILR state!
 330         ** See comment below for ILR usage.
 331         */
 332         __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
 333 
 334         /* set the matching bit in the IMR register */
 335         dino_dev->imr |= DINO_MASK_IRQ(local_irq);      /* used in dino_isr() */
 336         __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 337 
 338         /* Emulate "Level Triggered" Interrupt
 339         ** Basically, a driver is blowing it if the IRQ line is asserted
 340         ** while the IRQ is disabled.  But tulip.c seems to do that....
 341         ** Give 'em a kluge award and a nice round of applause!
 342         **
 343         ** The gsc_write will generate an interrupt which invokes dino_isr().
 344         ** dino_isr() will read IPR and find nothing. But then catch this
 345         ** when it also checks ILR.
 346         */
 347         tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
 348         if (tmp & DINO_MASK_IRQ(local_irq)) {
 349                 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
 350                                 __func__, tmp);
 351                 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
 352         }
 353 }
 354 
 355 static struct irq_chip dino_interrupt_type = {
 356         .name           = "GSC-PCI",
 357         .irq_unmask     = dino_unmask_irq,
 358         .irq_mask       = dino_mask_irq,
 359 };
 360 
 361 
 362 /*
 363  * Handle a Processor interrupt generated by Dino.
 364  *
 365  * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
 366  * wedging the CPU. Could be removed or made optional at some point.
 367  */
 368 static irqreturn_t dino_isr(int irq, void *intr_dev)
 369 {
 370         struct dino_device *dino_dev = intr_dev;
 371         u32 mask;
 372         int ilr_loop = 100;
 373 
 374         /* read and acknowledge pending interrupts */
 375 #ifdef DINO_DEBUG
 376         dino_dev->dino_irr0 =
 377 #endif
 378         mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
 379 
 380         if (mask == 0)
 381                 return IRQ_NONE;
 382 
 383 ilr_again:
 384         do {
 385                 int local_irq = __ffs(mask);
 386                 int irq = dino_dev->global_irq[local_irq];
 387                 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
 388                         __func__, irq, intr_dev, mask);
 389                 generic_handle_irq(irq);
 390                 mask &= ~DINO_MASK_IRQ(local_irq);
 391         } while (mask);
 392 
 393         /* Support for level triggered IRQ lines.
 394         ** 
 395         ** Dropping this support would make this routine *much* faster.
 396         ** But since PCI requires level triggered IRQ line to share lines...
 397         ** device drivers may assume lines are level triggered (and not
 398         ** edge triggered like EISA/ISA can be).
 399         */
 400         mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
 401         if (mask) {
 402                 if (--ilr_loop > 0)
 403                         goto ilr_again;
 404                 pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n",
 405                        dino_dev->hba.base_addr, mask);
 406         }
 407         return IRQ_HANDLED;
 408 }
 409 
 410 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
 411 {
 412         int irq = gsc_assign_irq(&dino_interrupt_type, dino);
 413         if (irq == NO_IRQ)
 414                 return;
 415 
 416         *irqp = irq;
 417         dino->global_irq[local_irq] = irq;
 418 }
 419 
 420 static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
 421 {
 422         int irq;
 423         struct dino_device *dino = ctrl;
 424 
 425         switch (dev->id.sversion) {
 426                 case 0x00084:   irq =  8; break; /* PS/2 */
 427                 case 0x0008c:   irq = 10; break; /* RS232 */
 428                 case 0x00096:   irq =  8; break; /* PS/2 */
 429                 default:        return;          /* Unknown */
 430         }
 431 
 432         dino_assign_irq(dino, irq, &dev->irq);
 433 }
 434 
 435 
 436 /*
 437  * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
 438  * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
 439  */
 440 static void quirk_cirrus_cardbus(struct pci_dev *dev)
 441 {
 442         u8 new_irq = dev->irq - 1;
 443         printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
 444                         pci_name(dev), dev->irq, new_irq);
 445         dev->irq = new_irq;
 446 }
 447 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
 448 
 449 #ifdef CONFIG_TULIP
 450 static void pci_fixup_tulip(struct pci_dev *dev)
 451 {
 452         if (!pci_dev_is_behind_card_dino(dev))
 453                 return;
 454         if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM))
 455                 return;
 456         pr_warn("%s: HP HSC-PCI Cards with card-mode Dino not yet supported.\n",
 457                 pci_name(dev));
 458         /* Disable this card by zeroing the PCI resources */
 459         memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
 460         memset(&dev->resource[1], 0, sizeof(dev->resource[1]));
 461 }
 462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_DEC, PCI_ANY_ID, pci_fixup_tulip);
 463 #endif /* CONFIG_TULIP */
 464 
 465 static void __init
 466 dino_bios_init(void)
 467 {
 468         DBG("dino_bios_init\n");
 469 }
 470 
 471 /*
 472  * dino_card_setup - Set up the memory space for a Dino in card mode.
 473  * @bus: the bus under this dino
 474  *
 475  * Claim an 8MB chunk of unused IO space and call the generic PCI routines
 476  * to set up the addresses of the devices on this bus.
 477  */
 478 #define _8MB 0x00800000UL
 479 static void __init
 480 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
 481 {
 482         int i;
 483         struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 484         struct resource *res;
 485         char name[128];
 486         int size;
 487 
 488         res = &dino_dev->hba.lmmio_space;
 489         res->flags = IORESOURCE_MEM;
 490         size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 
 491                          dev_name(bus->bridge));
 492         res->name = kmalloc(size+1, GFP_KERNEL);
 493         if(res->name)
 494                 strcpy((char *)res->name, name);
 495         else
 496                 res->name = dino_dev->hba.lmmio_space.name;
 497         
 498 
 499         if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
 500                                 F_EXTEND(0xf0000000UL) | _8MB,
 501                                 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
 502                 struct pci_dev *dev, *tmp;
 503 
 504                 printk(KERN_ERR "Dino: cannot attach bus %s\n",
 505                        dev_name(bus->bridge));
 506                 /* kill the bus, we can't do anything with it */
 507                 list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
 508                         list_del(&dev->bus_list);
 509                 }
 510                         
 511                 return;
 512         }
 513         bus->resource[1] = res;
 514         bus->resource[0] = &(dino_dev->hba.io_space);
 515 
 516         /* Now tell dino what range it has */
 517         for (i = 1; i < 31; i++) {
 518                 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
 519                         break;
 520         }
 521         DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
 522             i, res->start, base_addr + DINO_IO_ADDR_EN);
 523         __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
 524 }
 525 
 526 static void __init
 527 dino_card_fixup(struct pci_dev *dev)
 528 {
 529         u32 irq_pin;
 530 
 531         /*
 532         ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
 533         **         Not sure they were ever productized.
 534         **         Die here since we'll die later in dino_inb() anyway.
 535         */
 536         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 537                 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
 538         }
 539 
 540         /*
 541         ** Set Latency Timer to 0xff (not a shared bus)
 542         ** Set CACHELINE_SIZE.
 543         */
 544         dino_cfg_write(dev->bus, dev->devfn, 
 545                        PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 
 546 
 547         /*
 548         ** Program INT_LINE for card-mode devices.
 549         ** The cards are hardwired according to this algorithm.
 550         ** And it doesn't matter if PPB's are present or not since
 551         ** the IRQ lines bypass the PPB.
 552         **
 553         ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
 554         ** The additional "-1" adjusts for skewing the IRQ<->slot.
 555         */
 556         dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 
 557         dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
 558 
 559         /* Shouldn't really need to do this but it's in case someone tries
 560         ** to bypass PCI services and look at the card themselves.
 561         */
 562         dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 
 563 }
 564 
 565 /* The alignment contraints for PCI bridges under dino */
 566 #define DINO_BRIDGE_ALIGN 0x100000
 567 
 568 
 569 static void __init
 570 dino_fixup_bus(struct pci_bus *bus)
 571 {
 572         struct pci_dev *dev;
 573         struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 574 
 575         DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n",
 576             __func__, bus, bus->busn_res.start,
 577             bus->bridge->platform_data);
 578 
 579         /* Firmware doesn't set up card-mode dino, so we have to */
 580         if (is_card_dino(&dino_dev->hba.dev->id)) {
 581                 dino_card_setup(bus, dino_dev->hba.base_addr);
 582         } else if (bus->parent) {
 583                 int i;
 584 
 585                 pci_read_bridge_bases(bus);
 586 
 587 
 588                 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
 589                         if((bus->self->resource[i].flags & 
 590                             (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
 591                                 continue;
 592                         
 593                         if(bus->self->resource[i].flags & IORESOURCE_MEM) {
 594                                 /* There's a quirk to alignment of
 595                                  * bridge memory resources: the start
 596                                  * is the alignment and start-end is
 597                                  * the size.  However, firmware will
 598                                  * have assigned start and end, so we
 599                                  * need to take this into account */
 600                                 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
 601                                 bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
 602                                 
 603                         }
 604                                         
 605                         DBG("DEBUG %s assigning %d [%pR]\n",
 606                             dev_name(&bus->self->dev), i,
 607                             &bus->self->resource[i]);
 608                         WARN_ON(pci_assign_resource(bus->self, i));
 609                         DBG("DEBUG %s after assign %d [%pR]\n",
 610                             dev_name(&bus->self->dev), i,
 611                             &bus->self->resource[i]);
 612                 }
 613         }
 614 
 615 
 616         list_for_each_entry(dev, &bus->devices, bus_list) {
 617                 if (is_card_dino(&dino_dev->hba.dev->id))
 618                         dino_card_fixup(dev);
 619 
 620                 /*
 621                 ** P2PB's only have 2 BARs, no IRQs.
 622                 ** I'd like to just ignore them for now.
 623                 */
 624                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)  {
 625                         pcibios_init_bridge(dev);
 626                         continue;
 627                 }
 628 
 629                 /* null out the ROM resource if there is one (we don't
 630                  * care about an expansion rom on parisc, since it
 631                  * usually contains (x86) bios code) */
 632                 dev->resource[PCI_ROM_RESOURCE].flags = 0;
 633                                 
 634                 if(dev->irq == 255) {
 635 
 636 #define DINO_FIX_UNASSIGNED_INTERRUPTS
 637 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
 638 
 639                         /* This code tries to assign an unassigned
 640                          * interrupt.  Leave it disabled unless you
 641                          * *really* know what you're doing since the
 642                          * pin<->interrupt line mapping varies by bus
 643                          * and machine */
 644 
 645                         u32 irq_pin;
 646                         
 647                         dino_cfg_read(dev->bus, dev->devfn, 
 648                                       PCI_INTERRUPT_PIN, 1, &irq_pin);
 649                         irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
 650                         printk(KERN_WARNING "Device %s has undefined IRQ, "
 651                                         "setting to %d\n", pci_name(dev), irq_pin);
 652                         dino_cfg_write(dev->bus, dev->devfn, 
 653                                        PCI_INTERRUPT_LINE, 1, irq_pin);
 654                         dino_assign_irq(dino_dev, irq_pin, &dev->irq);
 655 #else
 656                         dev->irq = 65535;
 657                         printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
 658 #endif
 659                 } else {
 660                         /* Adjust INT_LINE for that busses region */
 661                         dino_assign_irq(dino_dev, dev->irq, &dev->irq);
 662                 }
 663         }
 664 }
 665 
 666 
 667 static struct pci_bios_ops dino_bios_ops = {
 668         .init           = dino_bios_init,
 669         .fixup_bus      = dino_fixup_bus
 670 };
 671 
 672 
 673 /*
 674  *      Initialise a DINO controller chip
 675  */
 676 static void __init
 677 dino_card_init(struct dino_device *dino_dev)
 678 {
 679         u32 brdg_feat = 0x00784e05;
 680         unsigned long status;
 681 
 682         status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
 683         if (status & 0x0000ff80) {
 684                 __raw_writel(0x00000005,
 685                                 dino_dev->hba.base_addr+DINO_IO_COMMAND);
 686                 udelay(1);
 687         }
 688 
 689         __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
 690         __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
 691         __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
 692 
 693 #if 1
 694 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
 695         /*
 696         ** PCX-L processors don't support XQL like Dino wants it.
 697         ** PCX-L2 ignore XQL signal and it doesn't matter.
 698         */
 699         brdg_feat &= ~0x4;      /* UXQL */
 700 #endif
 701         __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
 702 
 703         /*
 704         ** Don't enable address decoding until we know which I/O range
 705         ** currently is available from the host. Only affects MMIO
 706         ** and not I/O port space.
 707         */
 708         __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
 709 
 710         __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
 711         __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
 712         __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
 713 
 714         __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
 715         __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
 716         __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
 717 
 718         /* Disable PAMR before writing PAPR */
 719         __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
 720         __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
 721         __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
 722 
 723         /*
 724         ** Dino ERS encourages enabling FBB (0x6f).
 725         ** We can't until we know *all* devices below us can support it.
 726         ** (Something in device configuration header tells us).
 727         */
 728         __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
 729 
 730         /* Somewhere, the PCI spec says give devices 1 second
 731         ** to recover from the #RESET being de-asserted.
 732         ** Experience shows most devices only need 10ms.
 733         ** This short-cut speeds up booting significantly.
 734         */
 735         mdelay(pci_post_reset_delay);
 736 }
 737 
 738 static int __init
 739 dino_bridge_init(struct dino_device *dino_dev, const char *name)
 740 {
 741         unsigned long io_addr;
 742         int result, i, count=0;
 743         struct resource *res, *prevres = NULL;
 744         /*
 745          * Decoding IO_ADDR_EN only works for Built-in Dino
 746          * since PDC has already initialized this.
 747          */
 748 
 749         io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
 750         if (io_addr == 0) {
 751                 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
 752                 return -ENODEV;
 753         }
 754 
 755         res = &dino_dev->hba.lmmio_space;
 756         for (i = 0; i < 32; i++) {
 757                 unsigned long start, end;
 758 
 759                 if((io_addr & (1 << i)) == 0)
 760                         continue;
 761 
 762                 start = F_EXTEND(0xf0000000UL) | (i << 23);
 763                 end = start + 8 * 1024 * 1024 - 1;
 764 
 765                 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
 766                     start, end);
 767 
 768                 if(prevres && prevres->end + 1 == start) {
 769                         prevres->end = end;
 770                 } else {
 771                         if(count >= DINO_MAX_LMMIO_RESOURCES) {
 772                                 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
 773                                 break;
 774                         }
 775                         prevres = res;
 776                         res->start = start;
 777                         res->end = end;
 778                         res->flags = IORESOURCE_MEM;
 779                         res->name = kmalloc(64, GFP_KERNEL);
 780                         if(res->name)
 781                                 snprintf((char *)res->name, 64, "%s LMMIO %d",
 782                                          name, count);
 783                         res++;
 784                         count++;
 785                 }
 786         }
 787 
 788         res = &dino_dev->hba.lmmio_space;
 789 
 790         for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 791                 if(res[i].flags == 0)
 792                         break;
 793 
 794                 result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
 795                 if (result < 0) {
 796                         printk(KERN_ERR "%s: failed to claim PCI Bus address "
 797                                "space %d (%pR)!\n", name, i, &res[i]);
 798                         return result;
 799                 }
 800         }
 801         return 0;
 802 }
 803 
 804 static int __init dino_common_init(struct parisc_device *dev,
 805                 struct dino_device *dino_dev, const char *name)
 806 {
 807         int status;
 808         u32 eim;
 809         struct gsc_irq gsc_irq;
 810         struct resource *res;
 811 
 812         pcibios_register_hba(&dino_dev->hba);
 813 
 814         pci_bios = &dino_bios_ops;   /* used by pci_scan_bus() */
 815         pci_port = &dino_port_ops;
 816 
 817         /*
 818         ** Note: SMP systems can make use of IRR1/IAR1 registers
 819         **   But it won't buy much performance except in very
 820         **   specific applications/configurations. Note Dino
 821         **   still only has 11 IRQ input lines - just map some of them
 822         **   to a different processor.
 823         */
 824         dev->irq = gsc_alloc_irq(&gsc_irq);
 825         dino_dev->txn_addr = gsc_irq.txn_addr;
 826         dino_dev->txn_data = gsc_irq.txn_data;
 827         eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
 828 
 829         /* 
 830         ** Dino needs a PA "IRQ" to get a processor's attention.
 831         ** arch/parisc/kernel/irq.c returns an EIRR bit.
 832         */
 833         if (dev->irq < 0) {
 834                 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
 835                 return 1;
 836         }
 837 
 838         status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
 839         if (status) {
 840                 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 
 841                         name, status);
 842                 return 1;
 843         }
 844 
 845         /* Support the serial port which is sometimes attached on built-in
 846          * Dino / Cujo chips.
 847          */
 848 
 849         gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
 850 
 851         /*
 852         ** This enables DINO to generate interrupts when it sees
 853         ** any of its inputs *change*. Just asserting an IRQ
 854         ** before it's enabled (ie unmasked) isn't good enough.
 855         */
 856         __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
 857 
 858         /*
 859         ** Some platforms don't clear Dino's IRR0 register at boot time.
 860         ** Reading will clear it now.
 861         */
 862         __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
 863 
 864         /* allocate I/O Port resource region */
 865         res = &dino_dev->hba.io_space;
 866         if (!is_cujo(&dev->id)) {
 867                 res->name = "Dino I/O Port";
 868         } else {
 869                 res->name = "Cujo I/O Port";
 870         }
 871         res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
 872         res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
 873         res->flags = IORESOURCE_IO; /* do not mark it busy ! */
 874         if (request_resource(&ioport_resource, res) < 0) {
 875                 printk(KERN_ERR "%s: request I/O Port region failed "
 876                        "0x%lx/%lx (hpa 0x%px)\n",
 877                        name, (unsigned long)res->start, (unsigned long)res->end,
 878                        dino_dev->hba.base_addr);
 879                 return 1;
 880         }
 881 
 882         return 0;
 883 }
 884 
 885 #define CUJO_RAVEN_ADDR         F_EXTEND(0xf1000000UL)
 886 #define CUJO_FIREHAWK_ADDR      F_EXTEND(0xf1604000UL)
 887 #define CUJO_RAVEN_BADPAGE      0x01003000UL
 888 #define CUJO_FIREHAWK_BADPAGE   0x01607000UL
 889 
 890 static const char dino_vers[][4] = {
 891         "2.0",
 892         "2.1",
 893         "3.0",
 894         "3.1"
 895 };
 896 
 897 static const char cujo_vers[][4] = {
 898         "1.0",
 899         "2.0"
 900 };
 901 
 902 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
 903 
 904 /*
 905 ** Determine if dino should claim this chip (return 0) or not (return 1).
 906 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
 907 ** Much of the initialization is common though.
 908 */
 909 static int __init dino_probe(struct parisc_device *dev)
 910 {
 911         struct dino_device *dino_dev;   // Dino specific control struct
 912         const char *version = "unknown";
 913         char *name;
 914         int is_cujo = 0;
 915         LIST_HEAD(resources);
 916         struct pci_bus *bus;
 917         unsigned long hpa = dev->hpa.start;
 918         int max;
 919 
 920         name = "Dino";
 921         if (is_card_dino(&dev->id)) {
 922                 version = "3.x (card mode)";
 923         } else {
 924                 if (!is_cujo(&dev->id)) {
 925                         if (dev->id.hversion_rev < 4) {
 926                                 version = dino_vers[dev->id.hversion_rev];
 927                         }
 928                 } else {
 929                         name = "Cujo";
 930                         is_cujo = 1;
 931                         if (dev->id.hversion_rev < 2) {
 932                                 version = cujo_vers[dev->id.hversion_rev];
 933                         }
 934                 }
 935         }
 936 
 937         printk("%s version %s found at 0x%lx\n", name, version, hpa);
 938 
 939         if (!request_mem_region(hpa, PAGE_SIZE, name)) {
 940                 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
 941                         hpa);
 942                 return 1;
 943         }
 944 
 945         /* Check for bugs */
 946         if (is_cujo && dev->id.hversion_rev == 1) {
 947 #ifdef CONFIG_IOMMU_CCIO
 948                 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
 949                 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
 950                         ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
 951                 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
 952                         ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
 953                 } else {
 954                         printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
 955                 }
 956 #endif
 957         } else if (!is_cujo && !is_card_dino(&dev->id) &&
 958                         dev->id.hversion_rev < 3) {
 959                 printk(KERN_WARNING
 960 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
 961 "data corruption.  See Service Note Numbers: A4190A-01, A4191A-01.\n"
 962 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
 963 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
 964                         dev->id.hversion_rev);
 965 /* REVISIT: why are C200/C240 listed in the README table but not
 966 **   "Models affected"? Could be an omission in the original literature.
 967 */
 968         }
 969 
 970         dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
 971         if (!dino_dev) {
 972                 printk("dino_init_chip - couldn't alloc dino_device\n");
 973                 return 1;
 974         }
 975 
 976         dino_dev->hba.dev = dev;
 977         dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
 978         dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
 979         spin_lock_init(&dino_dev->dinosaur_pen);
 980         dino_dev->hba.iommu = ccio_get_iommu(dev);
 981 
 982         if (is_card_dino(&dev->id)) {
 983                 dino_card_init(dino_dev);
 984         } else {
 985                 dino_bridge_init(dino_dev, name);
 986         }
 987 
 988         if (dino_common_init(dev, dino_dev, name))
 989                 return 1;
 990 
 991         dev->dev.platform_data = dino_dev;
 992 
 993         pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
 994                                 HBA_PORT_BASE(dino_dev->hba.hba_num));
 995         if (dino_dev->hba.lmmio_space.flags)
 996                 pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
 997                                         dino_dev->hba.lmmio_space_offset);
 998         if (dino_dev->hba.elmmio_space.flags)
 999                 pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
1000                                         dino_dev->hba.lmmio_space_offset);
1001         if (dino_dev->hba.gmmio_space.flags)
1002                 pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
1003 
1004         dino_dev->hba.bus_num.start = dino_current_bus;
1005         dino_dev->hba.bus_num.end = 255;
1006         dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
1007         pci_add_resource(&resources, &dino_dev->hba.bus_num);
1008         /*
1009         ** It's not used to avoid chicken/egg problems
1010         ** with configuration accessor functions.
1011         */
1012         dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
1013                          dino_current_bus, &dino_cfg_ops, NULL, &resources);
1014         if (!bus) {
1015                 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
1016                        dev_name(&dev->dev), dino_current_bus);
1017                 pci_free_resource_list(&resources);
1018                 /* increment the bus number in case of duplicates */
1019                 dino_current_bus++;
1020                 return 0;
1021         }
1022 
1023         max = pci_scan_child_bus(bus);
1024         pci_bus_update_busn_res_end(bus, max);
1025 
1026         /* This code *depends* on scanning being single threaded
1027          * if it isn't, this global bus number count will fail
1028          */
1029         dino_current_bus = max + 1;
1030         pci_bus_assign_resources(bus);
1031         pci_bus_add_devices(bus);
1032         return 0;
1033 }
1034 
1035 /*
1036  * Normally, we would just test sversion.  But the Elroy PCI adapter has
1037  * the same sversion as Dino, so we have to check hversion as well.
1038  * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1039  * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1040  * For card-mode Dino, most machines report an sversion of 9D.  But 715
1041  * and 725 firmware misreport it as 0x08080 for no adequately explained
1042  * reason.
1043  */
1044 static const struct parisc_device_id dino_tbl[] __initconst = {
1045         { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1046         { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1047         { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1048         { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1049         { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1050         { 0, }
1051 };
1052 
1053 static struct parisc_driver dino_driver __refdata = {
1054         .name =         "dino",
1055         .id_table =     dino_tbl,
1056         .probe =        dino_probe,
1057 };
1058 
1059 /*
1060  * One time initialization to let the world know Dino is here.
1061  * This is the only routine which is NOT static.
1062  * Must be called exactly once before pci_init().
1063  */
1064 int __init dino_init(void)
1065 {
1066         register_parisc_driver(&dino_driver);
1067         return 0;
1068 }
1069
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/parisc/dino.c

DEFINITIONS
