This source file includes following definitions.
- qed_init
- qed_cleanup
- qed_set_coherency_mask
- qed_free_pci
- qed_init_pci
- qed_fill_dev_info
- qed_free_cdev
- qed_alloc_cdev
- qed_set_power_state
- qed_dl_param_get
- qed_dl_param_set
- qed_devlink_register
- qed_devlink_unregister
- qed_probe
- qed_remove
- qed_disable_msix
- qed_enable_msix
- qed_set_int_mode
- qed_simd_handler_config
- qed_simd_handler_clean
- qed_msix_sp_int
- qed_single_int
- qed_slowpath_irq_req
- qed_slowpath_tasklet_flush
- qed_slowpath_irq_sync
- qed_slowpath_irq_free
- qed_nic_stop
- qed_nic_setup
- qed_set_int_fp
- qed_get_int_fp
- qed_slowpath_setup_int
- qed_slowpath_vf_setup_int
- qed_unzip_data
- qed_alloc_stream_mem
- qed_free_stream_mem
- qed_update_pf_params
- qed_slowpath_delayed_work
- qed_periodic_db_rec_start
- qed_slowpath_wq_stop
- qed_slowpath_task
- qed_slowpath_wq_start
- qed_slowpath_start
- qed_slowpath_stop
- qed_set_name
- qed_sb_init
- qed_sb_release
- qed_can_link_change
- qed_set_link
- qed_get_port_type
- qed_get_link_data
- qed_fill_link_capability
- qed_fill_link
- qed_get_current_link
- qed_link_update
- qed_drain
- qed_nvm_flash_image_access_crc
- qed_nvm_flash_image_access
- qed_nvm_flash_image_file_start
- qed_nvm_flash_image_file_data
- qed_nvm_flash_image_validate
- qed_nvm_flash_cfg_write
- qed_nvm_flash_cfg_len
- qed_nvm_flash_cfg_read
- qed_nvm_flash
- qed_nvm_get_image
- qed_schedule_recovery_handler
- qed_set_coalesce
- qed_set_led
- qed_recovery_process
- qed_update_wol
- qed_update_drv_state
- qed_update_mac
- qed_update_mtu
- qed_read_module_eeprom
- qed_set_grc_config
- qed_get_affin_hwfn_idx
- qed_get_protocol_stats
- qed_mfw_tlv_req
- qed_fill_generic_tlv_data
- qed_mfw_fill_tlv_data
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33 #include <linux/stddef.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/string.h>
41 #include <linux/module.h>
42 #include <linux/interrupt.h>
43 #include <linux/workqueue.h>
44 #include <linux/ethtool.h>
45 #include <linux/etherdevice.h>
46 #include <linux/vmalloc.h>
47 #include <linux/crash_dump.h>
48 #include <linux/crc32.h>
49 #include <linux/qed/qed_if.h>
50 #include <linux/qed/qed_ll2_if.h>
51 #include <net/devlink.h>
52
53 #include "qed.h"
54 #include "qed_sriov.h"
55 #include "qed_sp.h"
56 #include "qed_dev_api.h"
57 #include "qed_ll2.h"
58 #include "qed_fcoe.h"
59 #include "qed_iscsi.h"
60
61 #include "qed_mcp.h"
62 #include "qed_reg_addr.h"
63 #include "qed_hw.h"
64 #include "qed_selftest.h"
65 #include "qed_debug.h"
66
67 #define QED_ROCE_QPS (8192)
68 #define QED_ROCE_DPIS (8)
69 #define QED_RDMA_SRQS QED_ROCE_QPS
70 #define QED_NVM_CFG_GET_FLAGS 0xA
71 #define QED_NVM_CFG_GET_PF_FLAGS 0x1A
72 #define QED_NVM_CFG_MAX_ATTRS 50
73
74 static char version[] =
75 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
76
77 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
78 MODULE_LICENSE("GPL");
79 MODULE_VERSION(DRV_MODULE_VERSION);
80
81 #define FW_FILE_VERSION \
82 __stringify(FW_MAJOR_VERSION) "." \
83 __stringify(FW_MINOR_VERSION) "." \
84 __stringify(FW_REVISION_VERSION) "." \
85 __stringify(FW_ENGINEERING_VERSION)
86
87 #define QED_FW_FILE_NAME \
88 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
89
90 MODULE_FIRMWARE(QED_FW_FILE_NAME);
91
92 static int __init qed_init(void)
93 {
94 pr_info("%s", version);
95
96 return 0;
97 }
98
99 static void __exit qed_cleanup(void)
100 {
101 pr_notice("qed_cleanup called\n");
102 }
103
104 module_init(qed_init);
105 module_exit(qed_cleanup);
106
107
108
109
110 static int qed_set_coherency_mask(struct qed_dev *cdev)
111 {
112 struct device *dev = &cdev->pdev->dev;
113
114 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
115 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
116 DP_NOTICE(cdev,
117 "Can't request 64-bit consistent allocations\n");
118 return -EIO;
119 }
120 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
121 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
122 return -EIO;
123 }
124
125 return 0;
126 }
127
128 static void qed_free_pci(struct qed_dev *cdev)
129 {
130 struct pci_dev *pdev = cdev->pdev;
131
132 if (cdev->doorbells && cdev->db_size)
133 iounmap(cdev->doorbells);
134 if (cdev->regview)
135 iounmap(cdev->regview);
136 if (atomic_read(&pdev->enable_cnt) == 1)
137 pci_release_regions(pdev);
138
139 pci_disable_device(pdev);
140 }
141
142 #define PCI_REVISION_ID_ERROR_VAL 0xff
143
144
145
146
147 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
148 {
149 u8 rev_id;
150 int rc;
151
152 cdev->pdev = pdev;
153
154 rc = pci_enable_device(pdev);
155 if (rc) {
156 DP_NOTICE(cdev, "Cannot enable PCI device\n");
157 goto err0;
158 }
159
160 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
161 DP_NOTICE(cdev, "No memory region found in bar #0\n");
162 rc = -EIO;
163 goto err1;
164 }
165
166 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
167 DP_NOTICE(cdev, "No memory region found in bar #2\n");
168 rc = -EIO;
169 goto err1;
170 }
171
172 if (atomic_read(&pdev->enable_cnt) == 1) {
173 rc = pci_request_regions(pdev, "qed");
174 if (rc) {
175 DP_NOTICE(cdev,
176 "Failed to request PCI memory resources\n");
177 goto err1;
178 }
179 pci_set_master(pdev);
180 pci_save_state(pdev);
181 }
182
183 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
184 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
185 DP_NOTICE(cdev,
186 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
187 rev_id);
188 rc = -ENODEV;
189 goto err2;
190 }
191 if (!pci_is_pcie(pdev)) {
192 DP_NOTICE(cdev, "The bus is not PCI Express\n");
193 rc = -EIO;
194 goto err2;
195 }
196
197 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
198 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
199 DP_NOTICE(cdev, "Cannot find power management capability\n");
200
201 rc = qed_set_coherency_mask(cdev);
202 if (rc)
203 goto err2;
204
205 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
206 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
207 cdev->pci_params.irq = pdev->irq;
208
209 cdev->regview = pci_ioremap_bar(pdev, 0);
210 if (!cdev->regview) {
211 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
212 rc = -ENOMEM;
213 goto err2;
214 }
215
216 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
217 cdev->db_size = pci_resource_len(cdev->pdev, 2);
218 if (!cdev->db_size) {
219 if (IS_PF(cdev)) {
220 DP_NOTICE(cdev, "No Doorbell bar available\n");
221 return -EINVAL;
222 } else {
223 return 0;
224 }
225 }
226
227 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
228
229 if (!cdev->doorbells) {
230 DP_NOTICE(cdev, "Cannot map doorbell space\n");
231 return -ENOMEM;
232 }
233
234 return 0;
235
236 err2:
237 pci_release_regions(pdev);
238 err1:
239 pci_disable_device(pdev);
240 err0:
241 return rc;
242 }
243
244 int qed_fill_dev_info(struct qed_dev *cdev,
245 struct qed_dev_info *dev_info)
246 {
247 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
248 struct qed_hw_info *hw_info = &p_hwfn->hw_info;
249 struct qed_tunnel_info *tun = &cdev->tunnel;
250 struct qed_ptt *ptt;
251
252 memset(dev_info, 0, sizeof(struct qed_dev_info));
253
254 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
255 tun->vxlan.b_mode_enabled)
256 dev_info->vxlan_enable = true;
257
258 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
259 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
260 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
261 dev_info->gre_enable = true;
262
263 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
264 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
265 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
266 dev_info->geneve_enable = true;
267
268 dev_info->num_hwfns = cdev->num_hwfns;
269 dev_info->pci_mem_start = cdev->pci_params.mem_start;
270 dev_info->pci_mem_end = cdev->pci_params.mem_end;
271 dev_info->pci_irq = cdev->pci_params.irq;
272 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
273 dev_info->dev_type = cdev->type;
274 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
275
276 if (IS_PF(cdev)) {
277 dev_info->fw_major = FW_MAJOR_VERSION;
278 dev_info->fw_minor = FW_MINOR_VERSION;
279 dev_info->fw_rev = FW_REVISION_VERSION;
280 dev_info->fw_eng = FW_ENGINEERING_VERSION;
281 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,
282 &cdev->mf_bits);
283 dev_info->tx_switching = true;
284
285 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
286 dev_info->wol_support = true;
287
288 dev_info->smart_an = qed_mcp_is_smart_an_supported(p_hwfn);
289
290 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id;
291 } else {
292 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
293 &dev_info->fw_minor, &dev_info->fw_rev,
294 &dev_info->fw_eng);
295 }
296
297 if (IS_PF(cdev)) {
298 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
299 if (ptt) {
300 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
301 &dev_info->mfw_rev, NULL);
302
303 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt,
304 &dev_info->mbi_version);
305
306 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
307 &dev_info->flash_size);
308
309 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
310 }
311 } else {
312 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
313 &dev_info->mfw_rev, NULL);
314 }
315
316 dev_info->mtu = hw_info->mtu;
317
318 return 0;
319 }
320
321 static void qed_free_cdev(struct qed_dev *cdev)
322 {
323 kfree((void *)cdev);
324 }
325
326 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
327 {
328 struct qed_dev *cdev;
329
330 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
331 if (!cdev)
332 return cdev;
333
334 qed_init_struct(cdev);
335
336 return cdev;
337 }
338
339
340 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
341 {
342 if (!cdev)
343 return -ENODEV;
344
345 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
346 return 0;
347 }
348
349 struct qed_devlink {
350 struct qed_dev *cdev;
351 };
352
353 enum qed_devlink_param_id {
354 QED_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
355 QED_DEVLINK_PARAM_ID_IWARP_CMT,
356 };
357
358 static int qed_dl_param_get(struct devlink *dl, u32 id,
359 struct devlink_param_gset_ctx *ctx)
360 {
361 struct qed_devlink *qed_dl;
362 struct qed_dev *cdev;
363
364 qed_dl = devlink_priv(dl);
365 cdev = qed_dl->cdev;
366 ctx->val.vbool = cdev->iwarp_cmt;
367
368 return 0;
369 }
370
371 static int qed_dl_param_set(struct devlink *dl, u32 id,
372 struct devlink_param_gset_ctx *ctx)
373 {
374 struct qed_devlink *qed_dl;
375 struct qed_dev *cdev;
376
377 qed_dl = devlink_priv(dl);
378 cdev = qed_dl->cdev;
379 cdev->iwarp_cmt = ctx->val.vbool;
380
381 return 0;
382 }
383
384 static const struct devlink_param qed_devlink_params[] = {
385 DEVLINK_PARAM_DRIVER(QED_DEVLINK_PARAM_ID_IWARP_CMT,
386 "iwarp_cmt", DEVLINK_PARAM_TYPE_BOOL,
387 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
388 qed_dl_param_get, qed_dl_param_set, NULL),
389 };
390
391 static const struct devlink_ops qed_dl_ops;
392
393 static int qed_devlink_register(struct qed_dev *cdev)
394 {
395 union devlink_param_value value;
396 struct qed_devlink *qed_dl;
397 struct devlink *dl;
398 int rc;
399
400 dl = devlink_alloc(&qed_dl_ops, sizeof(*qed_dl));
401 if (!dl)
402 return -ENOMEM;
403
404 qed_dl = devlink_priv(dl);
405
406 cdev->dl = dl;
407 qed_dl->cdev = cdev;
408
409 rc = devlink_register(dl, &cdev->pdev->dev);
410 if (rc)
411 goto err_free;
412
413 rc = devlink_params_register(dl, qed_devlink_params,
414 ARRAY_SIZE(qed_devlink_params));
415 if (rc)
416 goto err_unregister;
417
418 value.vbool = false;
419 devlink_param_driverinit_value_set(dl,
420 QED_DEVLINK_PARAM_ID_IWARP_CMT,
421 value);
422
423 devlink_params_publish(dl);
424 cdev->iwarp_cmt = false;
425
426 return 0;
427
428 err_unregister:
429 devlink_unregister(dl);
430
431 err_free:
432 cdev->dl = NULL;
433 devlink_free(dl);
434
435 return rc;
436 }
437
438 static void qed_devlink_unregister(struct qed_dev *cdev)
439 {
440 if (!cdev->dl)
441 return;
442
443 devlink_params_unregister(cdev->dl, qed_devlink_params,
444 ARRAY_SIZE(qed_devlink_params));
445
446 devlink_unregister(cdev->dl);
447 devlink_free(cdev->dl);
448 }
449
450
451 static struct qed_dev *qed_probe(struct pci_dev *pdev,
452 struct qed_probe_params *params)
453 {
454 struct qed_dev *cdev;
455 int rc;
456
457 cdev = qed_alloc_cdev(pdev);
458 if (!cdev)
459 goto err0;
460
461 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
462 cdev->protocol = params->protocol;
463
464 if (params->is_vf)
465 cdev->b_is_vf = true;
466
467 qed_init_dp(cdev, params->dp_module, params->dp_level);
468
469 cdev->recov_in_prog = params->recov_in_prog;
470
471 rc = qed_init_pci(cdev, pdev);
472 if (rc) {
473 DP_ERR(cdev, "init pci failed\n");
474 goto err1;
475 }
476 DP_INFO(cdev, "PCI init completed successfully\n");
477
478 rc = qed_devlink_register(cdev);
479 if (rc) {
480 DP_INFO(cdev, "Failed to register devlink.\n");
481 goto err2;
482 }
483
484 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
485 if (rc) {
486 DP_ERR(cdev, "hw prepare failed\n");
487 goto err2;
488 }
489
490 DP_INFO(cdev, "qed_probe completed successfully\n");
491
492 return cdev;
493
494 err2:
495 qed_free_pci(cdev);
496 err1:
497 qed_free_cdev(cdev);
498 err0:
499 return NULL;
500 }
501
502 static void qed_remove(struct qed_dev *cdev)
503 {
504 if (!cdev)
505 return;
506
507 qed_hw_remove(cdev);
508
509 qed_free_pci(cdev);
510
511 qed_set_power_state(cdev, PCI_D3hot);
512
513 qed_devlink_unregister(cdev);
514
515 qed_free_cdev(cdev);
516 }
517
518 static void qed_disable_msix(struct qed_dev *cdev)
519 {
520 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
521 pci_disable_msix(cdev->pdev);
522 kfree(cdev->int_params.msix_table);
523 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
524 pci_disable_msi(cdev->pdev);
525 }
526
527 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
528 }
529
530 static int qed_enable_msix(struct qed_dev *cdev,
531 struct qed_int_params *int_params)
532 {
533 int i, rc, cnt;
534
535 cnt = int_params->in.num_vectors;
536
537 for (i = 0; i < cnt; i++)
538 int_params->msix_table[i].entry = i;
539
540 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
541 int_params->in.min_msix_cnt, cnt);
542 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
543 (rc % cdev->num_hwfns)) {
544 pci_disable_msix(cdev->pdev);
545
546
547
548
549
550 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
551 DP_NOTICE(cdev,
552 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
553 cnt, int_params->in.num_vectors);
554 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
555 cnt);
556 if (!rc)
557 rc = cnt;
558 }
559
560 if (rc > 0) {
561
562 int_params->out.int_mode = QED_INT_MODE_MSIX;
563 int_params->out.num_vectors = rc;
564 rc = 0;
565 } else {
566 DP_NOTICE(cdev,
567 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
568 cnt, rc);
569 }
570
571 return rc;
572 }
573
574
575 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
576 {
577 struct qed_int_params *int_params = &cdev->int_params;
578 struct msix_entry *tbl;
579 int rc = 0, cnt;
580
581 switch (int_params->in.int_mode) {
582 case QED_INT_MODE_MSIX:
583
584 cnt = int_params->in.num_vectors;
585 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
586 if (!int_params->msix_table) {
587 rc = -ENOMEM;
588 goto out;
589 }
590
591
592 rc = qed_enable_msix(cdev, int_params);
593 if (!rc)
594 goto out;
595
596 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
597 kfree(int_params->msix_table);
598 if (force_mode)
599 goto out;
600
601
602 case QED_INT_MODE_MSI:
603 if (cdev->num_hwfns == 1) {
604 rc = pci_enable_msi(cdev->pdev);
605 if (!rc) {
606 int_params->out.int_mode = QED_INT_MODE_MSI;
607 goto out;
608 }
609
610 DP_NOTICE(cdev, "Failed to enable MSI\n");
611 if (force_mode)
612 goto out;
613 }
614
615
616 case QED_INT_MODE_INTA:
617 int_params->out.int_mode = QED_INT_MODE_INTA;
618 rc = 0;
619 goto out;
620 default:
621 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
622 int_params->in.int_mode);
623 rc = -EINVAL;
624 }
625
626 out:
627 if (!rc)
628 DP_INFO(cdev, "Using %s interrupts\n",
629 int_params->out.int_mode == QED_INT_MODE_INTA ?
630 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
631 "MSI" : "MSIX");
632 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
633
634 return rc;
635 }
636
637 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
638 int index, void(*handler)(void *))
639 {
640 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
641 int relative_idx = index / cdev->num_hwfns;
642
643 hwfn->simd_proto_handler[relative_idx].func = handler;
644 hwfn->simd_proto_handler[relative_idx].token = token;
645 }
646
647 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
648 {
649 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
650 int relative_idx = index / cdev->num_hwfns;
651
652 memset(&hwfn->simd_proto_handler[relative_idx], 0,
653 sizeof(struct qed_simd_fp_handler));
654 }
655
656 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
657 {
658 tasklet_schedule((struct tasklet_struct *)tasklet);
659 return IRQ_HANDLED;
660 }
661
662 static irqreturn_t qed_single_int(int irq, void *dev_instance)
663 {
664 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
665 struct qed_hwfn *hwfn;
666 irqreturn_t rc = IRQ_NONE;
667 u64 status;
668 int i, j;
669
670 for (i = 0; i < cdev->num_hwfns; i++) {
671 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
672
673 if (!status)
674 continue;
675
676 hwfn = &cdev->hwfns[i];
677
678
679 if (unlikely(status & 0x1)) {
680 tasklet_schedule(hwfn->sp_dpc);
681 status &= ~0x1;
682 rc = IRQ_HANDLED;
683 }
684
685
686 for (j = 0; j < 64; j++) {
687 if ((0x2ULL << j) & status) {
688 struct qed_simd_fp_handler *p_handler =
689 &hwfn->simd_proto_handler[j];
690
691 if (p_handler->func)
692 p_handler->func(p_handler->token);
693 else
694 DP_NOTICE(hwfn,
695 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
696 j, status);
697
698 status &= ~(0x2ULL << j);
699 rc = IRQ_HANDLED;
700 }
701 }
702
703 if (unlikely(status))
704 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
705 "got an unknown interrupt status 0x%llx\n",
706 status);
707 }
708
709 return rc;
710 }
711
712 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
713 {
714 struct qed_dev *cdev = hwfn->cdev;
715 u32 int_mode;
716 int rc = 0;
717 u8 id;
718
719 int_mode = cdev->int_params.out.int_mode;
720 if (int_mode == QED_INT_MODE_MSIX) {
721 id = hwfn->my_id;
722 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
723 id, cdev->pdev->bus->number,
724 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
725 rc = request_irq(cdev->int_params.msix_table[id].vector,
726 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
727 } else {
728 unsigned long flags = 0;
729
730 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
731 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
732 PCI_FUNC(cdev->pdev->devfn));
733
734 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
735 flags |= IRQF_SHARED;
736
737 rc = request_irq(cdev->pdev->irq, qed_single_int,
738 flags, cdev->name, cdev);
739 }
740
741 if (rc)
742 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
743 else
744 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
745 "Requested slowpath %s\n",
746 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
747
748 return rc;
749 }
750
751 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn)
752 {
753
754
755
756
757 if (p_hwfn->b_sp_dpc_enabled) {
758 tasklet_disable(p_hwfn->sp_dpc);
759 tasklet_enable(p_hwfn->sp_dpc);
760 }
761 }
762
763 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
764 {
765 struct qed_dev *cdev = p_hwfn->cdev;
766 u8 id = p_hwfn->my_id;
767 u32 int_mode;
768
769 int_mode = cdev->int_params.out.int_mode;
770 if (int_mode == QED_INT_MODE_MSIX)
771 synchronize_irq(cdev->int_params.msix_table[id].vector);
772 else
773 synchronize_irq(cdev->pdev->irq);
774
775 qed_slowpath_tasklet_flush(p_hwfn);
776 }
777
778 static void qed_slowpath_irq_free(struct qed_dev *cdev)
779 {
780 int i;
781
782 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
783 for_each_hwfn(cdev, i) {
784 if (!cdev->hwfns[i].b_int_requested)
785 break;
786 synchronize_irq(cdev->int_params.msix_table[i].vector);
787 free_irq(cdev->int_params.msix_table[i].vector,
788 cdev->hwfns[i].sp_dpc);
789 }
790 } else {
791 if (QED_LEADING_HWFN(cdev)->b_int_requested)
792 free_irq(cdev->pdev->irq, cdev);
793 }
794 qed_int_disable_post_isr_release(cdev);
795 }
796
797 static int qed_nic_stop(struct qed_dev *cdev)
798 {
799 int i, rc;
800
801 rc = qed_hw_stop(cdev);
802
803 for (i = 0; i < cdev->num_hwfns; i++) {
804 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
805
806 if (p_hwfn->b_sp_dpc_enabled) {
807 tasklet_disable(p_hwfn->sp_dpc);
808 p_hwfn->b_sp_dpc_enabled = false;
809 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
810 "Disabled sp tasklet [hwfn %d] at %p\n",
811 i, p_hwfn->sp_dpc);
812 }
813 }
814
815 qed_dbg_pf_exit(cdev);
816
817 return rc;
818 }
819
820 static int qed_nic_setup(struct qed_dev *cdev)
821 {
822 int rc, i;
823
824
825 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
826 for (i = 0; i < cdev->num_hwfns; i++) {
827 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
828
829 p_hwfn->using_ll2 = true;
830 }
831 }
832
833 rc = qed_resc_alloc(cdev);
834 if (rc)
835 return rc;
836
837 DP_INFO(cdev, "Allocated qed resources\n");
838
839 qed_resc_setup(cdev);
840
841 return rc;
842 }
843
844 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
845 {
846 int limit = 0;
847
848
849 cdev->int_params.fp_initialized = cnt ? true : false;
850
851 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
852 limit = cdev->num_hwfns * 63;
853 else if (cdev->int_params.fp_msix_cnt)
854 limit = cdev->int_params.fp_msix_cnt;
855
856 if (!limit)
857 return -ENOMEM;
858
859 return min_t(int, cnt, limit);
860 }
861
862 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
863 {
864 memset(info, 0, sizeof(struct qed_int_info));
865
866 if (!cdev->int_params.fp_initialized) {
867 DP_INFO(cdev,
868 "Protocol driver requested interrupt information, but its support is not yet configured\n");
869 return -EINVAL;
870 }
871
872
873
874
875 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
876 int msix_base = cdev->int_params.fp_msix_base;
877
878 info->msix_cnt = cdev->int_params.fp_msix_cnt;
879 info->msix = &cdev->int_params.msix_table[msix_base];
880 }
881
882 return 0;
883 }
884
885 static int qed_slowpath_setup_int(struct qed_dev *cdev,
886 enum qed_int_mode int_mode)
887 {
888 struct qed_sb_cnt_info sb_cnt_info;
889 int num_l2_queues = 0;
890 int rc;
891 int i;
892
893 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
894 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
895 return -EINVAL;
896 }
897
898 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
899 cdev->int_params.in.int_mode = int_mode;
900 for_each_hwfn(cdev, i) {
901 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
902 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
903 cdev->int_params.in.num_vectors += sb_cnt_info.cnt;
904 cdev->int_params.in.num_vectors++;
905 }
906
907
908 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
909
910 if (is_kdump_kernel()) {
911 DP_INFO(cdev,
912 "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
913 cdev->int_params.in.min_msix_cnt);
914 cdev->int_params.in.num_vectors =
915 cdev->int_params.in.min_msix_cnt;
916 }
917
918 rc = qed_set_int_mode(cdev, false);
919 if (rc) {
920 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
921 return rc;
922 }
923
924 cdev->int_params.fp_msix_base = cdev->num_hwfns;
925 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
926 cdev->num_hwfns;
927
928 if (!IS_ENABLED(CONFIG_QED_RDMA) ||
929 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev)))
930 return 0;
931
932 for_each_hwfn(cdev, i)
933 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
934
935 DP_VERBOSE(cdev, QED_MSG_RDMA,
936 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
937 cdev->int_params.fp_msix_cnt, num_l2_queues);
938
939 if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
940 cdev->int_params.rdma_msix_cnt =
941 (cdev->int_params.fp_msix_cnt - num_l2_queues)
942 / cdev->num_hwfns;
943 cdev->int_params.rdma_msix_base =
944 cdev->int_params.fp_msix_base + num_l2_queues;
945 cdev->int_params.fp_msix_cnt = num_l2_queues;
946 } else {
947 cdev->int_params.rdma_msix_cnt = 0;
948 }
949
950 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
951 cdev->int_params.rdma_msix_cnt,
952 cdev->int_params.rdma_msix_base);
953
954 return 0;
955 }
956
957 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
958 {
959 int rc;
960
961 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
962 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
963
964 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
965 &cdev->int_params.in.num_vectors);
966 if (cdev->num_hwfns > 1) {
967 u8 vectors = 0;
968
969 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
970 cdev->int_params.in.num_vectors += vectors;
971 }
972
973
974 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
975
976 rc = qed_set_int_mode(cdev, true);
977 if (rc)
978 return rc;
979
980 cdev->int_params.fp_msix_base = 0;
981 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
982
983 return 0;
984 }
985
986 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
987 u8 *input_buf, u32 max_size, u8 *unzip_buf)
988 {
989 int rc;
990
991 p_hwfn->stream->next_in = input_buf;
992 p_hwfn->stream->avail_in = input_len;
993 p_hwfn->stream->next_out = unzip_buf;
994 p_hwfn->stream->avail_out = max_size;
995
996 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
997
998 if (rc != Z_OK) {
999 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
1000 rc);
1001 return 0;
1002 }
1003
1004 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
1005 zlib_inflateEnd(p_hwfn->stream);
1006
1007 if (rc != Z_OK && rc != Z_STREAM_END) {
1008 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
1009 p_hwfn->stream->msg, rc);
1010 return 0;
1011 }
1012
1013 return p_hwfn->stream->total_out / 4;
1014 }
1015
1016 static int qed_alloc_stream_mem(struct qed_dev *cdev)
1017 {
1018 int i;
1019 void *workspace;
1020
1021 for_each_hwfn(cdev, i) {
1022 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1023
1024 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
1025 if (!p_hwfn->stream)
1026 return -ENOMEM;
1027
1028 workspace = vzalloc(zlib_inflate_workspacesize());
1029 if (!workspace)
1030 return -ENOMEM;
1031 p_hwfn->stream->workspace = workspace;
1032 }
1033
1034 return 0;
1035 }
1036
1037 static void qed_free_stream_mem(struct qed_dev *cdev)
1038 {
1039 int i;
1040
1041 for_each_hwfn(cdev, i) {
1042 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1043
1044 if (!p_hwfn->stream)
1045 return;
1046
1047 vfree(p_hwfn->stream->workspace);
1048 kfree(p_hwfn->stream);
1049 }
1050 }
1051
1052 static void qed_update_pf_params(struct qed_dev *cdev,
1053 struct qed_pf_params *params)
1054 {
1055 int i;
1056
1057 if (IS_ENABLED(CONFIG_QED_RDMA)) {
1058 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
1059 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
1060 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS;
1061
1062 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
1063 }
1064
1065 if (cdev->num_hwfns > 1 || IS_VF(cdev))
1066 params->eth_pf_params.num_arfs_filters = 0;
1067
1068
1069
1070
1071
1072 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) {
1073 u16 *num_cons;
1074
1075 num_cons = ¶ms->eth_pf_params.num_cons;
1076 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS);
1077 }
1078
1079 for (i = 0; i < cdev->num_hwfns; i++) {
1080 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1081
1082 p_hwfn->pf_params = *params;
1083 }
1084 }
1085
1086 #define QED_PERIODIC_DB_REC_COUNT 10
1087 #define QED_PERIODIC_DB_REC_INTERVAL_MS 100
1088 #define QED_PERIODIC_DB_REC_INTERVAL \
1089 msecs_to_jiffies(QED_PERIODIC_DB_REC_INTERVAL_MS)
1090
1091 static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn,
1092 enum qed_slowpath_wq_flag wq_flag,
1093 unsigned long delay)
1094 {
1095 if (!hwfn->slowpath_wq_active)
1096 return -EINVAL;
1097
1098
1099 smp_mb__before_atomic();
1100 set_bit(wq_flag, &hwfn->slowpath_task_flags);
1101 smp_mb__after_atomic();
1102 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, delay);
1103
1104 return 0;
1105 }
1106
1107 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn)
1108 {
1109
1110 p_hwfn->periodic_db_rec_count = QED_PERIODIC_DB_REC_COUNT;
1111
1112
1113 if (test_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1114 &p_hwfn->slowpath_task_flags))
1115 return;
1116
1117 qed_slowpath_delayed_work(p_hwfn, QED_SLOWPATH_PERIODIC_DB_REC,
1118 QED_PERIODIC_DB_REC_INTERVAL);
1119 }
1120
1121 static void qed_slowpath_wq_stop(struct qed_dev *cdev)
1122 {
1123 int i;
1124
1125 if (IS_VF(cdev))
1126 return;
1127
1128 for_each_hwfn(cdev, i) {
1129 if (!cdev->hwfns[i].slowpath_wq)
1130 continue;
1131
1132
1133 cdev->hwfns[i].slowpath_wq_active = false;
1134
1135 cancel_delayed_work(&cdev->hwfns[i].slowpath_task);
1136 destroy_workqueue(cdev->hwfns[i].slowpath_wq);
1137 }
1138 }
1139
1140 static void qed_slowpath_task(struct work_struct *work)
1141 {
1142 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1143 slowpath_task.work);
1144 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
1145
1146 if (!ptt) {
1147 if (hwfn->slowpath_wq_active)
1148 queue_delayed_work(hwfn->slowpath_wq,
1149 &hwfn->slowpath_task, 0);
1150
1151 return;
1152 }
1153
1154 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ,
1155 &hwfn->slowpath_task_flags))
1156 qed_mfw_process_tlv_req(hwfn, ptt);
1157
1158 if (test_and_clear_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1159 &hwfn->slowpath_task_flags)) {
1160 qed_db_rec_handler(hwfn, ptt);
1161 if (hwfn->periodic_db_rec_count--)
1162 qed_slowpath_delayed_work(hwfn,
1163 QED_SLOWPATH_PERIODIC_DB_REC,
1164 QED_PERIODIC_DB_REC_INTERVAL);
1165 }
1166
1167 qed_ptt_release(hwfn, ptt);
1168 }
1169
1170 static int qed_slowpath_wq_start(struct qed_dev *cdev)
1171 {
1172 struct qed_hwfn *hwfn;
1173 char name[NAME_SIZE];
1174 int i;
1175
1176 if (IS_VF(cdev))
1177 return 0;
1178
1179 for_each_hwfn(cdev, i) {
1180 hwfn = &cdev->hwfns[i];
1181
1182 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x",
1183 cdev->pdev->bus->number,
1184 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
1185
1186 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0);
1187 if (!hwfn->slowpath_wq) {
1188 DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n");
1189 return -ENOMEM;
1190 }
1191
1192 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task);
1193 hwfn->slowpath_wq_active = true;
1194 }
1195
1196 return 0;
1197 }
1198
1199 static int qed_slowpath_start(struct qed_dev *cdev,
1200 struct qed_slowpath_params *params)
1201 {
1202 struct qed_drv_load_params drv_load_params;
1203 struct qed_hw_init_params hw_init_params;
1204 struct qed_mcp_drv_version drv_version;
1205 struct qed_tunnel_info tunn_info;
1206 const u8 *data = NULL;
1207 struct qed_hwfn *hwfn;
1208 struct qed_ptt *p_ptt;
1209 int rc = -EINVAL;
1210
1211 if (qed_iov_wq_start(cdev))
1212 goto err;
1213
1214 if (qed_slowpath_wq_start(cdev))
1215 goto err;
1216
1217 if (IS_PF(cdev)) {
1218 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
1219 &cdev->pdev->dev);
1220 if (rc) {
1221 DP_NOTICE(cdev,
1222 "Failed to find fw file - /lib/firmware/%s\n",
1223 QED_FW_FILE_NAME);
1224 goto err;
1225 }
1226
1227 if (cdev->num_hwfns == 1) {
1228 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1229 if (p_ptt) {
1230 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
1231 } else {
1232 DP_NOTICE(cdev,
1233 "Failed to acquire PTT for aRFS\n");
1234 goto err;
1235 }
1236 }
1237 }
1238
1239 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
1240 rc = qed_nic_setup(cdev);
1241 if (rc)
1242 goto err;
1243
1244 if (IS_PF(cdev))
1245 rc = qed_slowpath_setup_int(cdev, params->int_mode);
1246 else
1247 rc = qed_slowpath_vf_setup_int(cdev);
1248 if (rc)
1249 goto err1;
1250
1251 if (IS_PF(cdev)) {
1252
1253 rc = qed_alloc_stream_mem(cdev);
1254 if (rc)
1255 goto err2;
1256
1257
1258 data = cdev->firmware->data + sizeof(u32);
1259
1260 qed_dbg_pf_init(cdev);
1261 }
1262
1263
1264 memset(&hw_init_params, 0, sizeof(hw_init_params));
1265 memset(&tunn_info, 0, sizeof(tunn_info));
1266 tunn_info.vxlan.b_mode_enabled = true;
1267 tunn_info.l2_gre.b_mode_enabled = true;
1268 tunn_info.ip_gre.b_mode_enabled = true;
1269 tunn_info.l2_geneve.b_mode_enabled = true;
1270 tunn_info.ip_geneve.b_mode_enabled = true;
1271 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1272 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1273 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1274 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1275 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1276 hw_init_params.p_tunn = &tunn_info;
1277 hw_init_params.b_hw_start = true;
1278 hw_init_params.int_mode = cdev->int_params.out.int_mode;
1279 hw_init_params.allow_npar_tx_switch = true;
1280 hw_init_params.bin_fw_data = data;
1281
1282 memset(&drv_load_params, 0, sizeof(drv_load_params));
1283 drv_load_params.is_crash_kernel = is_kdump_kernel();
1284 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1285 drv_load_params.avoid_eng_reset = false;
1286 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1287 hw_init_params.p_drv_load_params = &drv_load_params;
1288
1289 rc = qed_hw_init(cdev, &hw_init_params);
1290 if (rc)
1291 goto err2;
1292
1293 DP_INFO(cdev,
1294 "HW initialization and function start completed successfully\n");
1295
1296 if (IS_PF(cdev)) {
1297 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1298 BIT(QED_MODE_L2GENEVE_TUNN) |
1299 BIT(QED_MODE_IPGENEVE_TUNN) |
1300 BIT(QED_MODE_L2GRE_TUNN) |
1301 BIT(QED_MODE_IPGRE_TUNN));
1302 }
1303
1304
1305 if (QED_LEADING_HWFN(cdev)->using_ll2) {
1306 rc = qed_ll2_alloc_if(cdev);
1307 if (rc)
1308 goto err3;
1309 }
1310 if (IS_PF(cdev)) {
1311 hwfn = QED_LEADING_HWFN(cdev);
1312 drv_version.version = (params->drv_major << 24) |
1313 (params->drv_minor << 16) |
1314 (params->drv_rev << 8) |
1315 (params->drv_eng);
1316 strlcpy(drv_version.name, params->name,
1317 MCP_DRV_VER_STR_SIZE - 4);
1318 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1319 &drv_version);
1320 if (rc) {
1321 DP_NOTICE(cdev, "Failed sending drv version command\n");
1322 goto err4;
1323 }
1324 }
1325
1326 qed_reset_vport_stats(cdev);
1327
1328 return 0;
1329
1330 err4:
1331 qed_ll2_dealloc_if(cdev);
1332 err3:
1333 qed_hw_stop(cdev);
1334 err2:
1335 qed_hw_timers_stop_all(cdev);
1336 if (IS_PF(cdev))
1337 qed_slowpath_irq_free(cdev);
1338 qed_free_stream_mem(cdev);
1339 qed_disable_msix(cdev);
1340 err1:
1341 qed_resc_free(cdev);
1342 err:
1343 if (IS_PF(cdev))
1344 release_firmware(cdev->firmware);
1345
1346 if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1347 QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1348 qed_ptt_release(QED_LEADING_HWFN(cdev),
1349 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1350
1351 qed_iov_wq_stop(cdev, false);
1352
1353 qed_slowpath_wq_stop(cdev);
1354
1355 return rc;
1356 }
1357
1358 static int qed_slowpath_stop(struct qed_dev *cdev)
1359 {
1360 if (!cdev)
1361 return -ENODEV;
1362
1363 qed_slowpath_wq_stop(cdev);
1364
1365 qed_ll2_dealloc_if(cdev);
1366
1367 if (IS_PF(cdev)) {
1368 if (cdev->num_hwfns == 1)
1369 qed_ptt_release(QED_LEADING_HWFN(cdev),
1370 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1371 qed_free_stream_mem(cdev);
1372 if (IS_QED_ETH_IF(cdev))
1373 qed_sriov_disable(cdev, true);
1374 }
1375
1376 qed_nic_stop(cdev);
1377
1378 if (IS_PF(cdev))
1379 qed_slowpath_irq_free(cdev);
1380
1381 qed_disable_msix(cdev);
1382
1383 qed_resc_free(cdev);
1384
1385 qed_iov_wq_stop(cdev, true);
1386
1387 if (IS_PF(cdev))
1388 release_firmware(cdev->firmware);
1389
1390 return 0;
1391 }
1392
1393 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE])
1394 {
1395 int i;
1396
1397 memcpy(cdev->name, name, NAME_SIZE);
1398 for_each_hwfn(cdev, i)
1399 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1400 }
1401
1402 static u32 qed_sb_init(struct qed_dev *cdev,
1403 struct qed_sb_info *sb_info,
1404 void *sb_virt_addr,
1405 dma_addr_t sb_phy_addr, u16 sb_id,
1406 enum qed_sb_type type)
1407 {
1408 struct qed_hwfn *p_hwfn;
1409 struct qed_ptt *p_ptt;
1410 u16 rel_sb_id;
1411 u32 rc;
1412
1413
1414 if (type == QED_SB_TYPE_L2_QUEUE) {
1415 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns];
1416 rel_sb_id = sb_id / cdev->num_hwfns;
1417 } else {
1418 p_hwfn = QED_AFFIN_HWFN(cdev);
1419 rel_sb_id = sb_id;
1420 }
1421
1422 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1423 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1424 IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id);
1425
1426 if (IS_PF(p_hwfn->cdev)) {
1427 p_ptt = qed_ptt_acquire(p_hwfn);
1428 if (!p_ptt)
1429 return -EBUSY;
1430
1431 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1432 sb_phy_addr, rel_sb_id);
1433 qed_ptt_release(p_hwfn, p_ptt);
1434 } else {
1435 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1436 sb_phy_addr, rel_sb_id);
1437 }
1438
1439 return rc;
1440 }
1441
1442 static u32 qed_sb_release(struct qed_dev *cdev,
1443 struct qed_sb_info *sb_info,
1444 u16 sb_id,
1445 enum qed_sb_type type)
1446 {
1447 struct qed_hwfn *p_hwfn;
1448 u16 rel_sb_id;
1449 u32 rc;
1450
1451
1452 if (type == QED_SB_TYPE_L2_QUEUE) {
1453 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns];
1454 rel_sb_id = sb_id / cdev->num_hwfns;
1455 } else {
1456 p_hwfn = QED_AFFIN_HWFN(cdev);
1457 rel_sb_id = sb_id;
1458 }
1459
1460 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1461 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1462 IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id);
1463
1464 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1465
1466 return rc;
1467 }
1468
1469 static bool qed_can_link_change(struct qed_dev *cdev)
1470 {
1471 return true;
1472 }
1473
1474 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1475 {
1476 struct qed_hwfn *hwfn;
1477 struct qed_mcp_link_params *link_params;
1478 struct qed_ptt *ptt;
1479 u32 sup_caps;
1480 int rc;
1481
1482 if (!cdev)
1483 return -ENODEV;
1484
1485
1486 hwfn = &cdev->hwfns[0];
1487
1488
1489
1490
1491
1492 if (IS_VF(cdev)) {
1493 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1494 return 0;
1495 }
1496
1497 ptt = qed_ptt_acquire(hwfn);
1498 if (!ptt)
1499 return -EBUSY;
1500
1501 link_params = qed_mcp_get_link_params(hwfn);
1502 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1503 link_params->speed.autoneg = params->autoneg;
1504 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1505 link_params->speed.advertised_speeds = 0;
1506 sup_caps = QED_LM_1000baseT_Full_BIT |
1507 QED_LM_1000baseKX_Full_BIT |
1508 QED_LM_1000baseX_Full_BIT;
1509 if (params->adv_speeds & sup_caps)
1510 link_params->speed.advertised_speeds |=
1511 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1512 sup_caps = QED_LM_10000baseT_Full_BIT |
1513 QED_LM_10000baseKR_Full_BIT |
1514 QED_LM_10000baseKX4_Full_BIT |
1515 QED_LM_10000baseR_FEC_BIT |
1516 QED_LM_10000baseCR_Full_BIT |
1517 QED_LM_10000baseSR_Full_BIT |
1518 QED_LM_10000baseLR_Full_BIT |
1519 QED_LM_10000baseLRM_Full_BIT;
1520 if (params->adv_speeds & sup_caps)
1521 link_params->speed.advertised_speeds |=
1522 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1523 if (params->adv_speeds & QED_LM_20000baseKR2_Full_BIT)
1524 link_params->speed.advertised_speeds |=
1525 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
1526 sup_caps = QED_LM_25000baseKR_Full_BIT |
1527 QED_LM_25000baseCR_Full_BIT |
1528 QED_LM_25000baseSR_Full_BIT;
1529 if (params->adv_speeds & sup_caps)
1530 link_params->speed.advertised_speeds |=
1531 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1532 sup_caps = QED_LM_40000baseLR4_Full_BIT |
1533 QED_LM_40000baseKR4_Full_BIT |
1534 QED_LM_40000baseCR4_Full_BIT |
1535 QED_LM_40000baseSR4_Full_BIT;
1536 if (params->adv_speeds & sup_caps)
1537 link_params->speed.advertised_speeds |=
1538 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1539 sup_caps = QED_LM_50000baseKR2_Full_BIT |
1540 QED_LM_50000baseCR2_Full_BIT |
1541 QED_LM_50000baseSR2_Full_BIT;
1542 if (params->adv_speeds & sup_caps)
1543 link_params->speed.advertised_speeds |=
1544 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1545 sup_caps = QED_LM_100000baseKR4_Full_BIT |
1546 QED_LM_100000baseSR4_Full_BIT |
1547 QED_LM_100000baseCR4_Full_BIT |
1548 QED_LM_100000baseLR4_ER4_Full_BIT;
1549 if (params->adv_speeds & sup_caps)
1550 link_params->speed.advertised_speeds |=
1551 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1552 }
1553 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1554 link_params->speed.forced_speed = params->forced_speed;
1555 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1556 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1557 link_params->pause.autoneg = true;
1558 else
1559 link_params->pause.autoneg = false;
1560 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1561 link_params->pause.forced_rx = true;
1562 else
1563 link_params->pause.forced_rx = false;
1564 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1565 link_params->pause.forced_tx = true;
1566 else
1567 link_params->pause.forced_tx = false;
1568 }
1569 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1570 switch (params->loopback_mode) {
1571 case QED_LINK_LOOPBACK_INT_PHY:
1572 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1573 break;
1574 case QED_LINK_LOOPBACK_EXT_PHY:
1575 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1576 break;
1577 case QED_LINK_LOOPBACK_EXT:
1578 link_params->loopback_mode = ETH_LOOPBACK_EXT;
1579 break;
1580 case QED_LINK_LOOPBACK_MAC:
1581 link_params->loopback_mode = ETH_LOOPBACK_MAC;
1582 break;
1583 default:
1584 link_params->loopback_mode = ETH_LOOPBACK_NONE;
1585 break;
1586 }
1587 }
1588
1589 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
1590 memcpy(&link_params->eee, ¶ms->eee,
1591 sizeof(link_params->eee));
1592
1593 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1594
1595 qed_ptt_release(hwfn, ptt);
1596
1597 return rc;
1598 }
1599
1600 static int qed_get_port_type(u32 media_type)
1601 {
1602 int port_type;
1603
1604 switch (media_type) {
1605 case MEDIA_SFPP_10G_FIBER:
1606 case MEDIA_SFP_1G_FIBER:
1607 case MEDIA_XFP_FIBER:
1608 case MEDIA_MODULE_FIBER:
1609 case MEDIA_KR:
1610 port_type = PORT_FIBRE;
1611 break;
1612 case MEDIA_DA_TWINAX:
1613 port_type = PORT_DA;
1614 break;
1615 case MEDIA_BASE_T:
1616 port_type = PORT_TP;
1617 break;
1618 case MEDIA_NOT_PRESENT:
1619 port_type = PORT_NONE;
1620 break;
1621 case MEDIA_UNSPECIFIED:
1622 default:
1623 port_type = PORT_OTHER;
1624 break;
1625 }
1626 return port_type;
1627 }
1628
1629 static int qed_get_link_data(struct qed_hwfn *hwfn,
1630 struct qed_mcp_link_params *params,
1631 struct qed_mcp_link_state *link,
1632 struct qed_mcp_link_capabilities *link_caps)
1633 {
1634 void *p;
1635
1636 if (!IS_PF(hwfn->cdev)) {
1637 qed_vf_get_link_params(hwfn, params);
1638 qed_vf_get_link_state(hwfn, link);
1639 qed_vf_get_link_caps(hwfn, link_caps);
1640
1641 return 0;
1642 }
1643
1644 p = qed_mcp_get_link_params(hwfn);
1645 if (!p)
1646 return -ENXIO;
1647 memcpy(params, p, sizeof(*params));
1648
1649 p = qed_mcp_get_link_state(hwfn);
1650 if (!p)
1651 return -ENXIO;
1652 memcpy(link, p, sizeof(*link));
1653
1654 p = qed_mcp_get_link_capabilities(hwfn);
1655 if (!p)
1656 return -ENXIO;
1657 memcpy(link_caps, p, sizeof(*link_caps));
1658
1659 return 0;
1660 }
1661
1662 static void qed_fill_link_capability(struct qed_hwfn *hwfn,
1663 struct qed_ptt *ptt, u32 capability,
1664 u32 *if_capability)
1665 {
1666 u32 media_type, tcvr_state, tcvr_type;
1667 u32 speed_mask, board_cfg;
1668
1669 if (qed_mcp_get_media_type(hwfn, ptt, &media_type))
1670 media_type = MEDIA_UNSPECIFIED;
1671
1672 if (qed_mcp_get_transceiver_data(hwfn, ptt, &tcvr_state, &tcvr_type))
1673 tcvr_type = ETH_TRANSCEIVER_STATE_UNPLUGGED;
1674
1675 if (qed_mcp_trans_speed_mask(hwfn, ptt, &speed_mask))
1676 speed_mask = 0xFFFFFFFF;
1677
1678 if (qed_mcp_get_board_config(hwfn, ptt, &board_cfg))
1679 board_cfg = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
1680
1681 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
1682 "Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n",
1683 media_type, tcvr_state, tcvr_type, speed_mask, board_cfg);
1684
1685 switch (media_type) {
1686 case MEDIA_DA_TWINAX:
1687 *if_capability |= QED_LM_FIBRE_BIT;
1688 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1689 *if_capability |= QED_LM_20000baseKR2_Full_BIT;
1690
1691 capability = capability & speed_mask;
1692 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1693 *if_capability |= QED_LM_1000baseKX_Full_BIT;
1694 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1695 *if_capability |= QED_LM_10000baseCR_Full_BIT;
1696 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1697 *if_capability |= QED_LM_40000baseCR4_Full_BIT;
1698 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1699 *if_capability |= QED_LM_25000baseCR_Full_BIT;
1700 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1701 *if_capability |= QED_LM_50000baseCR2_Full_BIT;
1702 if (capability &
1703 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1704 *if_capability |= QED_LM_100000baseCR4_Full_BIT;
1705 break;
1706 case MEDIA_BASE_T:
1707 *if_capability |= QED_LM_TP_BIT;
1708 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
1709 if (capability &
1710 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
1711 *if_capability |= QED_LM_1000baseT_Full_BIT;
1712 }
1713 if (capability &
1714 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
1715 *if_capability |= QED_LM_10000baseT_Full_BIT;
1716 }
1717 }
1718 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
1719 *if_capability |= QED_LM_FIBRE_BIT;
1720 if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET)
1721 *if_capability |= QED_LM_1000baseT_Full_BIT;
1722 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET)
1723 *if_capability |= QED_LM_10000baseT_Full_BIT;
1724 }
1725 break;
1726 case MEDIA_SFP_1G_FIBER:
1727 case MEDIA_SFPP_10G_FIBER:
1728 case MEDIA_XFP_FIBER:
1729 case MEDIA_MODULE_FIBER:
1730 *if_capability |= QED_LM_FIBRE_BIT;
1731 if (capability &
1732 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
1733 if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) ||
1734 (tcvr_type == ETH_TRANSCEIVER_TYPE_1G_SX))
1735 *if_capability |= QED_LM_1000baseKX_Full_BIT;
1736 }
1737 if (capability &
1738 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
1739 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_SR)
1740 *if_capability |= QED_LM_10000baseSR_Full_BIT;
1741 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LR)
1742 *if_capability |= QED_LM_10000baseLR_Full_BIT;
1743 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LRM)
1744 *if_capability |= QED_LM_10000baseLRM_Full_BIT;
1745 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_ER)
1746 *if_capability |= QED_LM_10000baseR_FEC_BIT;
1747 }
1748 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1749 *if_capability |= QED_LM_20000baseKR2_Full_BIT;
1750 if (capability &
1751 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) {
1752 if (tcvr_type == ETH_TRANSCEIVER_TYPE_25G_SR)
1753 *if_capability |= QED_LM_25000baseSR_Full_BIT;
1754 }
1755 if (capability &
1756 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) {
1757 if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_LR4)
1758 *if_capability |= QED_LM_40000baseLR4_Full_BIT;
1759 if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_SR4)
1760 *if_capability |= QED_LM_40000baseSR4_Full_BIT;
1761 }
1762 if (capability &
1763 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1764 *if_capability |= QED_LM_50000baseKR2_Full_BIT;
1765 if (capability &
1766 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) {
1767 if (tcvr_type == ETH_TRANSCEIVER_TYPE_100G_SR4)
1768 *if_capability |= QED_LM_100000baseSR4_Full_BIT;
1769 }
1770
1771 break;
1772 case MEDIA_KR:
1773 *if_capability |= QED_LM_Backplane_BIT;
1774 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1775 *if_capability |= QED_LM_20000baseKR2_Full_BIT;
1776 if (capability &
1777 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1778 *if_capability |= QED_LM_1000baseKX_Full_BIT;
1779 if (capability &
1780 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1781 *if_capability |= QED_LM_10000baseKR_Full_BIT;
1782 if (capability &
1783 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1784 *if_capability |= QED_LM_25000baseKR_Full_BIT;
1785 if (capability &
1786 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1787 *if_capability |= QED_LM_40000baseKR4_Full_BIT;
1788 if (capability &
1789 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1790 *if_capability |= QED_LM_50000baseKR2_Full_BIT;
1791 if (capability &
1792 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1793 *if_capability |= QED_LM_100000baseKR4_Full_BIT;
1794 break;
1795 case MEDIA_UNSPECIFIED:
1796 case MEDIA_NOT_PRESENT:
1797 DP_VERBOSE(hwfn->cdev, QED_MSG_DEBUG,
1798 "Unknown media and transceiver type;\n");
1799 break;
1800 }
1801 }
1802
1803 static void qed_fill_link(struct qed_hwfn *hwfn,
1804 struct qed_ptt *ptt,
1805 struct qed_link_output *if_link)
1806 {
1807 struct qed_mcp_link_capabilities link_caps;
1808 struct qed_mcp_link_params params;
1809 struct qed_mcp_link_state link;
1810 u32 media_type;
1811
1812 memset(if_link, 0, sizeof(*if_link));
1813
1814
1815 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) {
1816 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1817 return;
1818 }
1819
1820
1821 if (link.link_up)
1822 if_link->link_up = true;
1823
1824
1825 if (link_caps.default_speed_autoneg)
1826 if_link->supported_caps |= QED_LM_Autoneg_BIT;
1827 if (params.pause.autoneg ||
1828 (params.pause.forced_rx && params.pause.forced_tx))
1829 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
1830 if (params.pause.autoneg || params.pause.forced_rx ||
1831 params.pause.forced_tx)
1832 if_link->supported_caps |= QED_LM_Pause_BIT;
1833
1834 if_link->advertised_caps = if_link->supported_caps;
1835 if (params.speed.autoneg)
1836 if_link->advertised_caps |= QED_LM_Autoneg_BIT;
1837 else
1838 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT;
1839
1840
1841 qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds,
1842 &if_link->advertised_caps);
1843
1844 qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities,
1845 &if_link->supported_caps);
1846
1847 if (link.link_up)
1848 if_link->speed = link.speed;
1849
1850
1851 if_link->duplex = DUPLEX_FULL;
1852 qed_mcp_get_media_type(hwfn, ptt, &media_type);
1853 if_link->port = qed_get_port_type(media_type);
1854
1855 if_link->autoneg = params.speed.autoneg;
1856
1857 if (params.pause.autoneg)
1858 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1859 if (params.pause.forced_rx)
1860 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1861 if (params.pause.forced_tx)
1862 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1863
1864
1865 if (link.partner_adv_speed &
1866 QED_LINK_PARTNER_SPEED_1G_FD)
1867 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1868 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1869 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1870 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G)
1871 if_link->lp_caps |= QED_LM_20000baseKR2_Full_BIT;
1872 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1873 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1874 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1875 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1876 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1877 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1878 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1879 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
1880
1881 if (link.an_complete)
1882 if_link->lp_caps |= QED_LM_Autoneg_BIT;
1883
1884 if (link.partner_adv_pause)
1885 if_link->lp_caps |= QED_LM_Pause_BIT;
1886 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1887 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1888 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
1889
1890 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
1891 if_link->eee_supported = false;
1892 } else {
1893 if_link->eee_supported = true;
1894 if_link->eee_active = link.eee_active;
1895 if_link->sup_caps = link_caps.eee_speed_caps;
1896
1897 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
1898 params.eee.adv_caps;
1899 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
1900 if_link->eee.enable = params.eee.enable;
1901 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
1902 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
1903 }
1904 }
1905
1906 static void qed_get_current_link(struct qed_dev *cdev,
1907 struct qed_link_output *if_link)
1908 {
1909 struct qed_hwfn *hwfn;
1910 struct qed_ptt *ptt;
1911 int i;
1912
1913 hwfn = &cdev->hwfns[0];
1914 if (IS_PF(cdev)) {
1915 ptt = qed_ptt_acquire(hwfn);
1916 if (ptt) {
1917 qed_fill_link(hwfn, ptt, if_link);
1918 qed_ptt_release(hwfn, ptt);
1919 } else {
1920 DP_NOTICE(hwfn, "Failed to fill link; No PTT\n");
1921 }
1922 } else {
1923 qed_fill_link(hwfn, NULL, if_link);
1924 }
1925
1926 for_each_hwfn(cdev, i)
1927 qed_inform_vf_link_state(&cdev->hwfns[i]);
1928 }
1929
1930 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
1931 {
1932 void *cookie = hwfn->cdev->ops_cookie;
1933 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1934 struct qed_link_output if_link;
1935
1936 qed_fill_link(hwfn, ptt, &if_link);
1937 qed_inform_vf_link_state(hwfn);
1938
1939 if (IS_LEAD_HWFN(hwfn) && cookie)
1940 op->link_update(cookie, &if_link);
1941 }
1942
1943 static int qed_drain(struct qed_dev *cdev)
1944 {
1945 struct qed_hwfn *hwfn;
1946 struct qed_ptt *ptt;
1947 int i, rc;
1948
1949 if (IS_VF(cdev))
1950 return 0;
1951
1952 for_each_hwfn(cdev, i) {
1953 hwfn = &cdev->hwfns[i];
1954 ptt = qed_ptt_acquire(hwfn);
1955 if (!ptt) {
1956 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1957 return -EBUSY;
1958 }
1959 rc = qed_mcp_drain(hwfn, ptt);
1960 qed_ptt_release(hwfn, ptt);
1961 if (rc)
1962 return rc;
1963 }
1964
1965 return 0;
1966 }
1967
1968 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev,
1969 struct qed_nvm_image_att *nvm_image,
1970 u32 *crc)
1971 {
1972 u8 *buf = NULL;
1973 int rc, j;
1974 u32 val;
1975
1976
1977 buf = kzalloc(nvm_image->length, GFP_KERNEL);
1978 if (!buf)
1979 return -ENOMEM;
1980
1981
1982 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr,
1983 buf, nvm_image->length);
1984 if (rc) {
1985 DP_ERR(cdev, "Failed reading image from nvm\n");
1986 goto out;
1987 }
1988
1989
1990
1991
1992 for (j = 0; j < nvm_image->length - 4; j += 4) {
1993 val = cpu_to_be32(*(u32 *)&buf[j]);
1994 *(u32 *)&buf[j] = val;
1995 }
1996
1997
1998
1999
2000 *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4)));
2001
2002 out:
2003 kfree(buf);
2004
2005 return rc;
2006 }
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data,
2020 bool *check_resp)
2021 {
2022 struct qed_nvm_image_att nvm_image;
2023 struct qed_hwfn *p_hwfn;
2024 bool is_crc = false;
2025 u32 image_type;
2026 int rc = 0, i;
2027 u16 len;
2028
2029 *data += 4;
2030 image_type = **data;
2031 p_hwfn = QED_LEADING_HWFN(cdev);
2032 for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2033 if (image_type == p_hwfn->nvm_info.image_att[i].image_type)
2034 break;
2035 if (i == p_hwfn->nvm_info.num_images) {
2036 DP_ERR(cdev, "Failed to find nvram image of type %08x\n",
2037 image_type);
2038 return -ENOENT;
2039 }
2040
2041 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2042 nvm_image.length = p_hwfn->nvm_info.image_att[i].len;
2043
2044 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2045 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n",
2046 **data, image_type, nvm_image.start_addr,
2047 nvm_image.start_addr + nvm_image.length - 1);
2048 (*data)++;
2049 is_crc = !!(**data & BIT(0));
2050 (*data)++;
2051 len = *((u16 *)*data);
2052 *data += 2;
2053 if (is_crc) {
2054 u32 crc = 0;
2055
2056 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc);
2057 if (rc) {
2058 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc);
2059 goto exit;
2060 }
2061
2062 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
2063 (nvm_image.start_addr +
2064 nvm_image.length - 4), (u8 *)&crc, 4);
2065 if (rc)
2066 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n",
2067 nvm_image.start_addr + nvm_image.length - 4, rc);
2068 goto exit;
2069 }
2070
2071
2072 while (len) {
2073 u32 offset, mask, value, cur_value;
2074 u8 buf[4];
2075
2076 value = *((u32 *)*data);
2077 *data += 4;
2078 mask = *((u32 *)*data);
2079 *data += 4;
2080 offset = *((u32 *)*data);
2081 *data += 4;
2082
2083 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf,
2084 4);
2085 if (rc) {
2086 DP_ERR(cdev, "Failed reading from %08x\n",
2087 nvm_image.start_addr + offset);
2088 goto exit;
2089 }
2090
2091 cur_value = le32_to_cpu(*((__le32 *)buf));
2092 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2093 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n",
2094 nvm_image.start_addr + offset, cur_value,
2095 (cur_value & ~mask) | (value & mask), value, mask);
2096 value = (value & mask) | (cur_value & ~mask);
2097 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
2098 nvm_image.start_addr + offset,
2099 (u8 *)&value, 4);
2100 if (rc) {
2101 DP_ERR(cdev, "Failed writing to %08x\n",
2102 nvm_image.start_addr + offset);
2103 goto exit;
2104 }
2105
2106 len--;
2107 }
2108 exit:
2109 return rc;
2110 }
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev,
2122 const u8 **data, bool *check_resp)
2123 {
2124 u32 file_type, file_size = 0;
2125 int rc;
2126
2127 *data += 4;
2128 *check_resp = !!(**data & BIT(0));
2129 *data += 4;
2130 file_type = **data;
2131
2132 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2133 "About to start a new file of type %02x\n", file_type);
2134 if (file_type == DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI) {
2135 *data += 4;
2136 file_size = *((u32 *)(*data));
2137 }
2138
2139 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_BEGIN, file_type,
2140 (u8 *)(&file_size), 4);
2141 *data += 4;
2142
2143 return rc;
2144 }
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev,
2158 const u8 **data, bool *check_resp)
2159 {
2160 u32 offset, len;
2161 int rc;
2162
2163 *data += 4;
2164 len = *((u32 *)(*data));
2165 *data += 4;
2166 *check_resp = !!(**data & BIT(0));
2167 *data += 4;
2168 offset = *((u32 *)(*data));
2169 *data += 4;
2170
2171 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2172 "About to write File-data: %08x bytes to offset %08x\n",
2173 len, offset);
2174
2175 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset,
2176 (char *)(*data), len);
2177 *data += len;
2178
2179 return rc;
2180 }
2181
2182
2183
2184
2185
2186
2187
2188
2189 static int qed_nvm_flash_image_validate(struct qed_dev *cdev,
2190 const struct firmware *image,
2191 const u8 **data)
2192 {
2193 u32 signature, len;
2194
2195
2196 if (image->size < 12) {
2197 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size);
2198 return -EINVAL;
2199 }
2200
2201
2202 signature = *((u32 *)(*data));
2203 if (signature != QED_NVM_SIGNATURE) {
2204 DP_ERR(cdev, "Wrong signature '%08x'\n", signature);
2205 return -EINVAL;
2206 }
2207
2208 *data += 4;
2209
2210 len = *((u32 *)(*data));
2211 if (len != image->size) {
2212 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n",
2213 len, (u32)image->size);
2214 return -EINVAL;
2215 }
2216
2217 *data += 4;
2218
2219 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) {
2220 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n",
2221 *((u16 *)(*data)));
2222 return -EINVAL;
2223 }
2224
2225 *data += 4;
2226
2227 return 0;
2228 }
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244 static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data)
2245 {
2246 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2247 u8 entity_id, len, buf[32];
2248 bool need_nvm_init = true;
2249 struct qed_ptt *ptt;
2250 u16 cfg_id, count;
2251 int rc = 0, i;
2252 u32 flags;
2253
2254 ptt = qed_ptt_acquire(hwfn);
2255 if (!ptt)
2256 return -EAGAIN;
2257
2258
2259 *data += 4;
2260 count = *((u16 *)*data);
2261 *data += 4;
2262
2263 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2264 "Read config ids: num_attrs = %0d\n", count);
2265
2266
2267
2268 for (i = 1; i <= count; i++) {
2269 cfg_id = *((u16 *)*data);
2270 *data += 2;
2271 entity_id = **data;
2272 (*data)++;
2273 len = **data;
2274 (*data)++;
2275 memcpy(buf, *data, len);
2276 *data += len;
2277
2278 flags = 0;
2279 if (need_nvm_init) {
2280 flags |= QED_NVM_CFG_OPTION_INIT;
2281 need_nvm_init = false;
2282 }
2283
2284
2285 if (!(i % QED_NVM_CFG_MAX_ATTRS) || i == count) {
2286 flags |= QED_NVM_CFG_OPTION_COMMIT |
2287 QED_NVM_CFG_OPTION_FREE;
2288 need_nvm_init = true;
2289 }
2290
2291 if (entity_id)
2292 flags |= QED_NVM_CFG_OPTION_ENTITY_SEL;
2293
2294 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2295 "cfg_id = %d entity = %d len = %d\n", cfg_id,
2296 entity_id, len);
2297 rc = qed_mcp_nvm_set_cfg(hwfn, ptt, cfg_id, entity_id, flags,
2298 buf, len);
2299 if (rc) {
2300 DP_ERR(cdev, "Error %d configuring %d\n", rc, cfg_id);
2301 break;
2302 }
2303 }
2304
2305 qed_ptt_release(hwfn, ptt);
2306
2307 return rc;
2308 }
2309
2310 #define QED_MAX_NVM_BUF_LEN 32
2311 static int qed_nvm_flash_cfg_len(struct qed_dev *cdev, u32 cmd)
2312 {
2313 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2314 u8 buf[QED_MAX_NVM_BUF_LEN];
2315 struct qed_ptt *ptt;
2316 u32 len;
2317 int rc;
2318
2319 ptt = qed_ptt_acquire(hwfn);
2320 if (!ptt)
2321 return QED_MAX_NVM_BUF_LEN;
2322
2323 rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, 0, QED_NVM_CFG_GET_FLAGS, buf,
2324 &len);
2325 if (rc || !len) {
2326 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
2327 len = QED_MAX_NVM_BUF_LEN;
2328 }
2329
2330 qed_ptt_release(hwfn, ptt);
2331
2332 return len;
2333 }
2334
2335 static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data,
2336 u32 cmd, u32 entity_id)
2337 {
2338 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2339 struct qed_ptt *ptt;
2340 u32 flags, len;
2341 int rc = 0;
2342
2343 ptt = qed_ptt_acquire(hwfn);
2344 if (!ptt)
2345 return -EAGAIN;
2346
2347 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2348 "Read config cmd = %d entity id %d\n", cmd, entity_id);
2349 flags = entity_id ? QED_NVM_CFG_GET_PF_FLAGS : QED_NVM_CFG_GET_FLAGS;
2350 rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, entity_id, flags, *data, &len);
2351 if (rc)
2352 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
2353
2354 qed_ptt_release(hwfn, ptt);
2355
2356 return rc;
2357 }
2358
2359 static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
2360 {
2361 const struct firmware *image;
2362 const u8 *data, *data_end;
2363 u32 cmd_type;
2364 int rc;
2365
2366 rc = request_firmware(&image, name, &cdev->pdev->dev);
2367 if (rc) {
2368 DP_ERR(cdev, "Failed to find '%s'\n", name);
2369 return rc;
2370 }
2371
2372 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2373 "Flashing '%s' - firmware's data at %p, size is %08x\n",
2374 name, image->data, (u32)image->size);
2375 data = image->data;
2376 data_end = data + image->size;
2377
2378 rc = qed_nvm_flash_image_validate(cdev, image, &data);
2379 if (rc)
2380 goto exit;
2381
2382 while (data < data_end) {
2383 bool check_resp = false;
2384
2385
2386 cmd_type = *((u32 *)data);
2387 switch (cmd_type) {
2388 case QED_NVM_FLASH_CMD_FILE_DATA:
2389 rc = qed_nvm_flash_image_file_data(cdev, &data,
2390 &check_resp);
2391 break;
2392 case QED_NVM_FLASH_CMD_FILE_START:
2393 rc = qed_nvm_flash_image_file_start(cdev, &data,
2394 &check_resp);
2395 break;
2396 case QED_NVM_FLASH_CMD_NVM_CHANGE:
2397 rc = qed_nvm_flash_image_access(cdev, &data,
2398 &check_resp);
2399 break;
2400 case QED_NVM_FLASH_CMD_NVM_CFG_ID:
2401 rc = qed_nvm_flash_cfg_write(cdev, &data);
2402 break;
2403 default:
2404 DP_ERR(cdev, "Unknown command %08x\n", cmd_type);
2405 rc = -EINVAL;
2406 goto exit;
2407 }
2408
2409 if (rc) {
2410 DP_ERR(cdev, "Command %08x failed\n", cmd_type);
2411 goto exit;
2412 }
2413
2414
2415 if (check_resp) {
2416 u32 mcp_response = 0;
2417
2418 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) {
2419 DP_ERR(cdev, "Failed getting MCP response\n");
2420 rc = -EINVAL;
2421 goto exit;
2422 }
2423
2424 switch (mcp_response & FW_MSG_CODE_MASK) {
2425 case FW_MSG_CODE_OK:
2426 case FW_MSG_CODE_NVM_OK:
2427 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK:
2428 case FW_MSG_CODE_PHY_OK:
2429 break;
2430 default:
2431 DP_ERR(cdev, "MFW returns error: %08x\n",
2432 mcp_response);
2433 rc = -EINVAL;
2434 goto exit;
2435 }
2436 }
2437 }
2438
2439 exit:
2440 release_firmware(image);
2441
2442 return rc;
2443 }
2444
2445 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type,
2446 u8 *buf, u16 len)
2447 {
2448 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2449
2450 return qed_mcp_get_nvm_image(hwfn, type, buf, len);
2451 }
2452
2453 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn)
2454 {
2455 struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common;
2456 void *cookie = p_hwfn->cdev->ops_cookie;
2457
2458 if (ops && ops->schedule_recovery_handler)
2459 ops->schedule_recovery_handler(cookie);
2460 }
2461
2462 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
2463 void *handle)
2464 {
2465 return qed_set_queue_coalesce(rx_coal, tx_coal, handle);
2466 }
2467
2468 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
2469 {
2470 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2471 struct qed_ptt *ptt;
2472 int status = 0;
2473
2474 ptt = qed_ptt_acquire(hwfn);
2475 if (!ptt)
2476 return -EAGAIN;
2477
2478 status = qed_mcp_set_led(hwfn, ptt, mode);
2479
2480 qed_ptt_release(hwfn, ptt);
2481
2482 return status;
2483 }
2484
2485 static int qed_recovery_process(struct qed_dev *cdev)
2486 {
2487 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2488 struct qed_ptt *p_ptt;
2489 int rc = 0;
2490
2491 p_ptt = qed_ptt_acquire(p_hwfn);
2492 if (!p_ptt)
2493 return -EAGAIN;
2494
2495 rc = qed_start_recovery_process(p_hwfn, p_ptt);
2496
2497 qed_ptt_release(p_hwfn, p_ptt);
2498
2499 return rc;
2500 }
2501
2502 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
2503 {
2504 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2505 struct qed_ptt *ptt;
2506 int rc = 0;
2507
2508 if (IS_VF(cdev))
2509 return 0;
2510
2511 ptt = qed_ptt_acquire(hwfn);
2512 if (!ptt)
2513 return -EAGAIN;
2514
2515 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
2516 : QED_OV_WOL_DISABLED);
2517 if (rc)
2518 goto out;
2519 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2520
2521 out:
2522 qed_ptt_release(hwfn, ptt);
2523 return rc;
2524 }
2525
2526 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
2527 {
2528 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2529 struct qed_ptt *ptt;
2530 int status = 0;
2531
2532 if (IS_VF(cdev))
2533 return 0;
2534
2535 ptt = qed_ptt_acquire(hwfn);
2536 if (!ptt)
2537 return -EAGAIN;
2538
2539 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
2540 QED_OV_DRIVER_STATE_ACTIVE :
2541 QED_OV_DRIVER_STATE_DISABLED);
2542
2543 qed_ptt_release(hwfn, ptt);
2544
2545 return status;
2546 }
2547
2548 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
2549 {
2550 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2551 struct qed_ptt *ptt;
2552 int status = 0;
2553
2554 if (IS_VF(cdev))
2555 return 0;
2556
2557 ptt = qed_ptt_acquire(hwfn);
2558 if (!ptt)
2559 return -EAGAIN;
2560
2561 status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
2562 if (status)
2563 goto out;
2564
2565 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2566
2567 out:
2568 qed_ptt_release(hwfn, ptt);
2569 return status;
2570 }
2571
2572 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
2573 {
2574 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2575 struct qed_ptt *ptt;
2576 int status = 0;
2577
2578 if (IS_VF(cdev))
2579 return 0;
2580
2581 ptt = qed_ptt_acquire(hwfn);
2582 if (!ptt)
2583 return -EAGAIN;
2584
2585 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
2586 if (status)
2587 goto out;
2588
2589 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2590
2591 out:
2592 qed_ptt_release(hwfn, ptt);
2593 return status;
2594 }
2595
2596 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
2597 u8 dev_addr, u32 offset, u32 len)
2598 {
2599 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2600 struct qed_ptt *ptt;
2601 int rc = 0;
2602
2603 if (IS_VF(cdev))
2604 return 0;
2605
2606 ptt = qed_ptt_acquire(hwfn);
2607 if (!ptt)
2608 return -EAGAIN;
2609
2610 rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr,
2611 offset, len, buf);
2612
2613 qed_ptt_release(hwfn, ptt);
2614
2615 return rc;
2616 }
2617
2618 static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val)
2619 {
2620 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2621 struct qed_ptt *ptt;
2622 int rc = 0;
2623
2624 if (IS_VF(cdev))
2625 return 0;
2626
2627 ptt = qed_ptt_acquire(hwfn);
2628 if (!ptt)
2629 return -EAGAIN;
2630
2631 rc = qed_dbg_grc_config(hwfn, ptt, cfg_id, val);
2632
2633 qed_ptt_release(hwfn, ptt);
2634
2635 return rc;
2636 }
2637
2638 static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev)
2639 {
2640 return QED_AFFIN_HWFN_IDX(cdev);
2641 }
2642
2643 static struct qed_selftest_ops qed_selftest_ops_pass = {
2644 .selftest_memory = &qed_selftest_memory,
2645 .selftest_interrupt = &qed_selftest_interrupt,
2646 .selftest_register = &qed_selftest_register,
2647 .selftest_clock = &qed_selftest_clock,
2648 .selftest_nvram = &qed_selftest_nvram,
2649 };
2650
2651 const struct qed_common_ops qed_common_ops_pass = {
2652 .selftest = &qed_selftest_ops_pass,
2653 .probe = &qed_probe,
2654 .remove = &qed_remove,
2655 .set_power_state = &qed_set_power_state,
2656 .set_name = &qed_set_name,
2657 .update_pf_params = &qed_update_pf_params,
2658 .slowpath_start = &qed_slowpath_start,
2659 .slowpath_stop = &qed_slowpath_stop,
2660 .set_fp_int = &qed_set_int_fp,
2661 .get_fp_int = &qed_get_int_fp,
2662 .sb_init = &qed_sb_init,
2663 .sb_release = &qed_sb_release,
2664 .simd_handler_config = &qed_simd_handler_config,
2665 .simd_handler_clean = &qed_simd_handler_clean,
2666 .dbg_grc = &qed_dbg_grc,
2667 .dbg_grc_size = &qed_dbg_grc_size,
2668 .can_link_change = &qed_can_link_change,
2669 .set_link = &qed_set_link,
2670 .get_link = &qed_get_current_link,
2671 .drain = &qed_drain,
2672 .update_msglvl = &qed_init_dp,
2673 .dbg_all_data = &qed_dbg_all_data,
2674 .dbg_all_data_size = &qed_dbg_all_data_size,
2675 .chain_alloc = &qed_chain_alloc,
2676 .chain_free = &qed_chain_free,
2677 .nvm_flash = &qed_nvm_flash,
2678 .nvm_get_image = &qed_nvm_get_image,
2679 .set_coalesce = &qed_set_coalesce,
2680 .set_led = &qed_set_led,
2681 .recovery_process = &qed_recovery_process,
2682 .recovery_prolog = &qed_recovery_prolog,
2683 .update_drv_state = &qed_update_drv_state,
2684 .update_mac = &qed_update_mac,
2685 .update_mtu = &qed_update_mtu,
2686 .update_wol = &qed_update_wol,
2687 .db_recovery_add = &qed_db_recovery_add,
2688 .db_recovery_del = &qed_db_recovery_del,
2689 .read_module_eeprom = &qed_read_module_eeprom,
2690 .get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
2691 .read_nvm_cfg = &qed_nvm_flash_cfg_read,
2692 .read_nvm_cfg_len = &qed_nvm_flash_cfg_len,
2693 .set_grc_config = &qed_set_grc_config,
2694 };
2695
2696 void qed_get_protocol_stats(struct qed_dev *cdev,
2697 enum qed_mcp_protocol_type type,
2698 union qed_mcp_protocol_stats *stats)
2699 {
2700 struct qed_eth_stats eth_stats;
2701
2702 memset(stats, 0, sizeof(*stats));
2703
2704 switch (type) {
2705 case QED_MCP_LAN_STATS:
2706 qed_get_vport_stats(cdev, ð_stats);
2707 stats->lan_stats.ucast_rx_pkts =
2708 eth_stats.common.rx_ucast_pkts;
2709 stats->lan_stats.ucast_tx_pkts =
2710 eth_stats.common.tx_ucast_pkts;
2711 stats->lan_stats.fcs_err = -1;
2712 break;
2713 case QED_MCP_FCOE_STATS:
2714 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
2715 break;
2716 case QED_MCP_ISCSI_STATS:
2717 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
2718 break;
2719 default:
2720 DP_VERBOSE(cdev, QED_MSG_SP,
2721 "Invalid protocol type = %d\n", type);
2722 return;
2723 }
2724 }
2725
2726 int qed_mfw_tlv_req(struct qed_hwfn *hwfn)
2727 {
2728 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
2729 "Scheduling slowpath task [Flag: %d]\n",
2730 QED_SLOWPATH_MFW_TLV_REQ);
2731 smp_mb__before_atomic();
2732 set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags);
2733 smp_mb__after_atomic();
2734 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
2735
2736 return 0;
2737 }
2738
2739 static void
2740 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv)
2741 {
2742 struct qed_common_cb_ops *op = cdev->protocol_ops.common;
2743 struct qed_eth_stats_common *p_common;
2744 struct qed_generic_tlvs gen_tlvs;
2745 struct qed_eth_stats stats;
2746 int i;
2747
2748 memset(&gen_tlvs, 0, sizeof(gen_tlvs));
2749 op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs);
2750
2751 if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM)
2752 tlv->flags.ipv4_csum_offload = true;
2753 if (gen_tlvs.feat_flags & QED_TLV_LSO)
2754 tlv->flags.lso_supported = true;
2755 tlv->flags.b_set = true;
2756
2757 for (i = 0; i < QED_TLV_MAC_COUNT; i++) {
2758 if (is_valid_ether_addr(gen_tlvs.mac[i])) {
2759 ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]);
2760 tlv->mac_set[i] = true;
2761 }
2762 }
2763
2764 qed_get_vport_stats(cdev, &stats);
2765 p_common = &stats.common;
2766 tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
2767 p_common->rx_bcast_pkts;
2768 tlv->rx_frames_set = true;
2769 tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
2770 p_common->rx_bcast_bytes;
2771 tlv->rx_bytes_set = true;
2772 tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
2773 p_common->tx_bcast_pkts;
2774 tlv->tx_frames_set = true;
2775 tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
2776 p_common->tx_bcast_bytes;
2777 tlv->rx_bytes_set = true;
2778 }
2779
2780 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type,
2781 union qed_mfw_tlv_data *tlv_buf)
2782 {
2783 struct qed_dev *cdev = hwfn->cdev;
2784 struct qed_common_cb_ops *ops;
2785
2786 ops = cdev->protocol_ops.common;
2787 if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) {
2788 DP_NOTICE(hwfn, "Can't collect TLV management info\n");
2789 return -EINVAL;
2790 }
2791
2792 switch (type) {
2793 case QED_MFW_TLV_GENERIC:
2794 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic);
2795 break;
2796 case QED_MFW_TLV_ETH:
2797 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth);
2798 break;
2799 case QED_MFW_TLV_FCOE:
2800 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe);
2801 break;
2802 case QED_MFW_TLV_ISCSI:
2803 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi);
2804 break;
2805 default:
2806 break;
2807 }
2808
2809 return 0;
2810 }