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8 #ifndef __QLCNIC_HW_H
9 #define __QLCNIC_HW_H
10
11
12 enum qlcnic_regs {
13 QLCNIC_PEG_HALT_STATUS1 = 0,
14 QLCNIC_PEG_HALT_STATUS2,
15 QLCNIC_PEG_ALIVE_COUNTER,
16 QLCNIC_FLASH_LOCK_OWNER,
17 QLCNIC_FW_CAPABILITIES,
18 QLCNIC_CRB_DRV_ACTIVE,
19 QLCNIC_CRB_DEV_STATE,
20 QLCNIC_CRB_DRV_STATE,
21 QLCNIC_CRB_DRV_SCRATCH,
22 QLCNIC_CRB_DEV_PARTITION_INFO,
23 QLCNIC_CRB_DRV_IDC_VER,
24 QLCNIC_FW_VERSION_MAJOR,
25 QLCNIC_FW_VERSION_MINOR,
26 QLCNIC_FW_VERSION_SUB,
27 QLCNIC_CRB_DEV_NPAR_STATE,
28 QLCNIC_FW_IMG_VALID,
29 QLCNIC_CMDPEG_STATE,
30 QLCNIC_RCVPEG_STATE,
31 QLCNIC_ASIC_TEMP,
32 QLCNIC_FW_API,
33 QLCNIC_DRV_OP_MODE,
34 QLCNIC_FLASH_LOCK,
35 QLCNIC_FLASH_UNLOCK,
36 };
37
38
39 #define QLC_SHARED_REG_RD32(a, addr) \
40 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
41
42
43 #define QLC_SHARED_REG_WR32(a, addr, value) \
44 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
45
46
47 #define QLCRDX(ahw, addr) \
48 readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))
49
50
51 #define QLCWRX(ahw, addr, value) \
52 writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))
53
54 #define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1
55 #define QLCNIC_CMD_CONFIG_INTRPT 0x2
56 #define QLCNIC_CMD_CREATE_RX_CTX 0x7
57 #define QLCNIC_CMD_DESTROY_RX_CTX 0x8
58 #define QLCNIC_CMD_CREATE_TX_CTX 0x9
59 #define QLCNIC_CMD_DESTROY_TX_CTX 0xa
60 #define QLCNIC_CMD_CONFIGURE_LRO 0xC
61 #define QLCNIC_CMD_CONFIGURE_MAC_LEARNING 0xD
62 #define QLCNIC_CMD_GET_STATISTICS 0xF
63 #define QLCNIC_CMD_INTRPT_TEST 0x11
64 #define QLCNIC_CMD_SET_MTU 0x12
65 #define QLCNIC_CMD_READ_PHY 0x13
66 #define QLCNIC_CMD_WRITE_PHY 0x14
67 #define QLCNIC_CMD_READ_HW_REG 0x15
68 #define QLCNIC_CMD_GET_FLOW_CTL 0x16
69 #define QLCNIC_CMD_SET_FLOW_CTL 0x17
70 #define QLCNIC_CMD_READ_MAX_MTU 0x18
71 #define QLCNIC_CMD_READ_MAX_LRO 0x19
72 #define QLCNIC_CMD_MAC_ADDRESS 0x1f
73 #define QLCNIC_CMD_GET_PCI_INFO 0x20
74 #define QLCNIC_CMD_GET_NIC_INFO 0x21
75 #define QLCNIC_CMD_SET_NIC_INFO 0x22
76 #define QLCNIC_CMD_GET_ESWITCH_CAPABILITY 0x24
77 #define QLCNIC_CMD_TOGGLE_ESWITCH 0x25
78 #define QLCNIC_CMD_GET_ESWITCH_STATUS 0x26
79 #define QLCNIC_CMD_SET_PORTMIRRORING 0x27
80 #define QLCNIC_CMD_CONFIGURE_ESWITCH 0x28
81 #define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG 0x29
82 #define QLCNIC_CMD_GET_ESWITCH_STATS 0x2a
83 #define QLCNIC_CMD_CONFIG_PORT 0x2e
84 #define QLCNIC_CMD_TEMP_SIZE 0x2f
85 #define QLCNIC_CMD_GET_TEMP_HDR 0x30
86 #define QLCNIC_CMD_BC_EVENT_SETUP 0x31
87 #define QLCNIC_CMD_CONFIG_VPORT 0x32
88 #define QLCNIC_CMD_DCB_QUERY_CAP 0x34
89 #define QLCNIC_CMD_DCB_QUERY_PARAM 0x35
90 #define QLCNIC_CMD_GET_MAC_STATS 0x37
91 #define QLCNIC_CMD_82XX_SET_DRV_VER 0x38
92 #define QLCNIC_CMD_MQ_TX_CONFIG_INTR 0x39
93 #define QLCNIC_CMD_GET_LED_STATUS 0x3C
94 #define QLCNIC_CMD_CONFIGURE_RSS 0x41
95 #define QLCNIC_CMD_CONFIG_INTR_COAL 0x43
96 #define QLCNIC_CMD_CONFIGURE_LED 0x44
97 #define QLCNIC_CMD_CONFIG_MAC_VLAN 0x45
98 #define QLCNIC_CMD_GET_LINK_EVENT 0x48
99 #define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE 0x49
100 #define QLCNIC_CMD_CONFIGURE_HW_LRO 0x4A
101 #define QLCNIC_CMD_SET_INGRESS_ENCAP 0x4E
102 #define QLCNIC_CMD_INIT_NIC_FUNC 0x60
103 #define QLCNIC_CMD_STOP_NIC_FUNC 0x61
104 #define QLCNIC_CMD_IDC_ACK 0x63
105 #define QLCNIC_CMD_SET_PORT_CONFIG 0x66
106 #define QLCNIC_CMD_GET_PORT_CONFIG 0x67
107 #define QLCNIC_CMD_GET_LINK_STATUS 0x68
108 #define QLCNIC_CMD_SET_LED_CONFIG 0x69
109 #define QLCNIC_CMD_GET_LED_CONFIG 0x6A
110 #define QLCNIC_CMD_83XX_SET_DRV_VER 0x6F
111 #define QLCNIC_CMD_ADD_RCV_RINGS 0x0B
112 #define QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP 0x37
113
114 #define QLCNIC_INTRPT_INTX 1
115 #define QLCNIC_INTRPT_MSIX 3
116 #define QLCNIC_INTRPT_ADD 1
117 #define QLCNIC_INTRPT_DEL 2
118
119 #define QLCNIC_GET_CURRENT_MAC 1
120 #define QLCNIC_SET_STATION_MAC 2
121 #define QLCNIC_GET_DEFAULT_MAC 3
122 #define QLCNIC_GET_FAC_DEF_MAC 4
123 #define QLCNIC_SET_FAC_DEF_MAC 5
124
125 #define QLCNIC_MBX_LINK_EVENT 0x8001
126 #define QLCNIC_MBX_BC_EVENT 0x8002
127 #define QLCNIC_MBX_COMP_EVENT 0x8100
128 #define QLCNIC_MBX_REQUEST_EVENT 0x8101
129 #define QLCNIC_MBX_TIME_EXTEND_EVENT 0x8102
130 #define QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT 0x8110
131 #define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130
132 #define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131
133
134 struct qlcnic_mailbox_metadata {
135 u32 cmd;
136 u32 in_args;
137 u32 out_args;
138 };
139
140
141 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
142
143 #define QLCNIC_SET_OWNER 1
144 #define QLCNIC_CLR_OWNER 0
145 #define QLCNIC_MBX_TIMEOUT 5000
146
147 #define QLCNIC_MBX_RSP_OK 1
148 #define QLCNIC_MBX_PORT_RSP_OK 0x1a
149 #define QLCNIC_MBX_ASYNC_EVENT BIT_15
150
151
152 #define QLCNIC_MAX_HW_TX_RINGS 8
153 #define QLCNIC_MAX_HW_VNIC_TX_RINGS 4
154 #define QLCNIC_MAX_TX_RINGS 8
155 #define QLCNIC_MAX_SDS_RINGS 8
156
157 struct qlcnic_pci_info;
158 struct qlcnic_info;
159 struct qlcnic_cmd_args;
160 struct ethtool_stats;
161 struct pci_device_id;
162 struct qlcnic_host_sds_ring;
163 struct qlcnic_host_tx_ring;
164 struct qlcnic_hardware_context;
165 struct qlcnic_adapter;
166 struct qlcnic_fw_dump;
167
168 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong, int *);
169 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
170 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int);
171 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
172 int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter,
173 struct net_device *netdev);
174 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *);
175 void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter,
176 u64 *uaddr, u16 vlan_id,
177 struct qlcnic_host_tx_ring *tx_ring);
178 int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *,
179 struct ethtool_coalesce *);
180 int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *);
181 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int);
182 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
183 __be32, int);
184 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int);
185 void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
186 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8);
187 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8);
188 void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
189 void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
190 int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
191 struct qlcnic_cmd_args *);
192 int qlcnic_82xx_mq_intrpt(struct qlcnic_adapter *, int);
193 int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *, u8);
194 int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *);
195 int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *,
196 struct qlcnic_host_tx_ring *tx_ring, int);
197 void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *);
198 void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *,
199 struct qlcnic_host_tx_ring *);
200 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
201 int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*, u8);
202 int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
203 int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
204 int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
205 int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *,
206 struct qlcnic_adapter *, u32);
207 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
208 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *);
209 int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32);
210 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *);
211 int qlcnic_82xx_api_lock(struct qlcnic_adapter *);
212 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *);
213 void qlcnic_82xx_napi_enable(struct qlcnic_adapter *);
214 void qlcnic_82xx_napi_disable(struct qlcnic_adapter *);
215 void qlcnic_82xx_napi_del(struct qlcnic_adapter *);
216 int qlcnic_82xx_shutdown(struct pci_dev *);
217 int qlcnic_82xx_resume(struct qlcnic_adapter *);
218 void qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8 failed);
219 void qlcnic_fw_poll_work(struct work_struct *work);
220
221 u32 qlcnic_82xx_get_saved_state(void *, u32);
222 void qlcnic_82xx_set_saved_state(void *, u32, u32);
223 void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
224 u32 qlcnic_82xx_get_cap_size(void *, int);
225 void qlcnic_82xx_set_sys_info(void *, int, u32);
226 void qlcnic_82xx_store_cap_mask(void *, u32);
227 #endif