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13 #ifndef _REGS_H
14 #define _REGS_H
15
16 #define TBD 0
17
18 struct XENA_dev_config {
19
20
21
22 u64 general_int_status;
23 #define GEN_INTR_TXPIC s2BIT(0)
24 #define GEN_INTR_TXDMA s2BIT(1)
25 #define GEN_INTR_TXMAC s2BIT(2)
26 #define GEN_INTR_TXXGXS s2BIT(3)
27 #define GEN_INTR_TXTRAFFIC s2BIT(8)
28 #define GEN_INTR_RXPIC s2BIT(32)
29 #define GEN_INTR_RXDMA s2BIT(33)
30 #define GEN_INTR_RXMAC s2BIT(34)
31 #define GEN_INTR_MC s2BIT(35)
32 #define GEN_INTR_RXXGXS s2BIT(36)
33 #define GEN_INTR_RXTRAFFIC s2BIT(40)
34 #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
38 GEN_INTR_MC
39
40 u64 general_int_mask;
41
42 u8 unused0[0x100 - 0x10];
43
44 u64 sw_reset;
45
46 #define SW_RESET_XENA vBIT(0xA5,0,8)
47 #define SW_RESET_FLASH vBIT(0xA5,8,8)
48 #define SW_RESET_EOI vBIT(0xA5,16,8)
49 #define SW_RESET_ALL (SW_RESET_XENA | \
50 SW_RESET_FLASH | \
51 SW_RESET_EOI)
52
53 #define SW_RESET_RAW_VAL 0xA5000000
54
55
56 u64 adapter_status;
57 #define ADAPTER_STATUS_TDMA_READY s2BIT(0)
58 #define ADAPTER_STATUS_RDMA_READY s2BIT(1)
59 #define ADAPTER_STATUS_PFC_READY s2BIT(2)
60 #define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3)
61 #define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5)
62 #define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6)
63 #define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)
64 #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65 #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
66 #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
67 #define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24)
68 #define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25)
69 #define ADAPTER_STATUS_RIC_RUNNING s2BIT(26)
70 #define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30)
71 #define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31)
72
73 u64 adapter_control;
74 #define ADAPTER_CNTL_EN s2BIT(7)
75 #define ADAPTER_EOI_TX_ON s2BIT(15)
76 #define ADAPTER_LED_ON s2BIT(23)
77 #define ADAPTER_UDPI(val) vBIT(val,36,4)
78 #define ADAPTER_WAIT_INT s2BIT(48)
79 #define ADAPTER_ECC_EN s2BIT(55)
80
81 u64 serr_source;
82 #define SERR_SOURCE_PIC s2BIT(0)
83 #define SERR_SOURCE_TXDMA s2BIT(1)
84 #define SERR_SOURCE_RXDMA s2BIT(2)
85 #define SERR_SOURCE_MAC s2BIT(3)
86 #define SERR_SOURCE_MC s2BIT(4)
87 #define SERR_SOURCE_XGXS s2BIT(5)
88 #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
89 SERR_SOURCE_TXDMA | \
90 SERR_SOURCE_RXDMA | \
91 SERR_SOURCE_MAC | \
92 SERR_SOURCE_MC | \
93 SERR_SOURCE_XGXS)
94
95 u64 pci_mode;
96 #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
97 #define PCI_MODE_PCI_33 0
98 #define PCI_MODE_PCI_66 0x1
99 #define PCI_MODE_PCIX_M1_66 0x2
100 #define PCI_MODE_PCIX_M1_100 0x3
101 #define PCI_MODE_PCIX_M1_133 0x4
102 #define PCI_MODE_PCIX_M2_66 0x5
103 #define PCI_MODE_PCIX_M2_100 0x6
104 #define PCI_MODE_PCIX_M2_133 0x7
105 #define PCI_MODE_UNSUPPORTED s2BIT(0)
106 #define PCI_MODE_32_BITS s2BIT(8)
107 #define PCI_MODE_UNKNOWN_MODE s2BIT(9)
108
109 u8 unused_0[0x800 - 0x128];
110
111
112 u64 pic_int_status;
113 u64 pic_int_mask;
114 #define PIC_INT_TX s2BIT(0)
115 #define PIC_INT_FLSH s2BIT(1)
116 #define PIC_INT_MDIO s2BIT(2)
117 #define PIC_INT_IIC s2BIT(3)
118 #define PIC_INT_GPIO s2BIT(4)
119 #define PIC_INT_RX s2BIT(32)
120
121 u64 txpic_int_reg;
122 u64 txpic_int_mask;
123 #define PCIX_INT_REG_ECC_SG_ERR s2BIT(0)
124 #define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)
125 #define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)
126 #define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9)
127 #define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10)
128 #define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11)
129 #define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13)
130 #define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14)
131 #define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15)
132 #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21)
133 #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23)
134 #define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48)
135 #define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50)
136
137
138
139
140
141 u64 txpic_alarms;
142 u64 rxpic_int_reg;
143 u64 rxpic_int_mask;
144 u64 rxpic_alarms;
145
146 u64 flsh_int_reg;
147 u64 flsh_int_mask;
148 #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63)
149 #define PIC_FLSH_INT_REG_ERR s2BIT(62)
150 u64 flash_alarms;
151
152 u64 mdio_int_reg;
153 u64 mdio_int_mask;
154 #define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0)
155 #define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)
156 #define MDIO_INT_REG_LASI s2BIT(39)
157 u64 mdio_alarms;
158
159 u64 iic_int_reg;
160 u64 iic_int_mask;
161 #define IIC_INT_REG_BUS_FSM_ERR s2BIT(4)
162 #define IIC_INT_REG_BIT_FSM_ERR s2BIT(5)
163 #define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6)
164 #define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)
165 #define IIC_INT_REG_ACK_ERR s2BIT(8)
166 u64 iic_alarms;
167
168 u8 unused4[0x08];
169
170 u64 gpio_int_reg;
171 #define GPIO_INT_REG_DP_ERR_INT s2BIT(0)
172 #define GPIO_INT_REG_LINK_DOWN s2BIT(1)
173 #define GPIO_INT_REG_LINK_UP s2BIT(2)
174 u64 gpio_int_mask;
175 #define GPIO_INT_MASK_LINK_DOWN s2BIT(1)
176 #define GPIO_INT_MASK_LINK_UP s2BIT(2)
177 u64 gpio_alarms;
178
179 u8 unused5[0x38];
180
181 u64 tx_traffic_int;
182 #define TX_TRAFFIC_INT_n(n) s2BIT(n)
183 u64 tx_traffic_mask;
184
185 u64 rx_traffic_int;
186 #define RX_TRAFFIC_INT_n(n) s2BIT(n)
187 u64 rx_traffic_mask;
188
189
190 u64 pic_control;
191 #define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0)
192 #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
193
194 u64 swapper_ctrl;
195 #define SWAPPER_CTRL_PIF_R_FE s2BIT(0)
196 #define SWAPPER_CTRL_PIF_R_SE s2BIT(1)
197 #define SWAPPER_CTRL_PIF_W_FE s2BIT(8)
198 #define SWAPPER_CTRL_PIF_W_SE s2BIT(9)
199 #define SWAPPER_CTRL_TXP_FE s2BIT(16)
200 #define SWAPPER_CTRL_TXP_SE s2BIT(17)
201 #define SWAPPER_CTRL_TXD_R_FE s2BIT(18)
202 #define SWAPPER_CTRL_TXD_R_SE s2BIT(19)
203 #define SWAPPER_CTRL_TXD_W_FE s2BIT(20)
204 #define SWAPPER_CTRL_TXD_W_SE s2BIT(21)
205 #define SWAPPER_CTRL_TXF_R_FE s2BIT(22)
206 #define SWAPPER_CTRL_TXF_R_SE s2BIT(23)
207 #define SWAPPER_CTRL_RXD_R_FE s2BIT(32)
208 #define SWAPPER_CTRL_RXD_R_SE s2BIT(33)
209 #define SWAPPER_CTRL_RXD_W_FE s2BIT(34)
210 #define SWAPPER_CTRL_RXD_W_SE s2BIT(35)
211 #define SWAPPER_CTRL_RXF_W_FE s2BIT(36)
212 #define SWAPPER_CTRL_RXF_W_SE s2BIT(37)
213 #define SWAPPER_CTRL_XMSI_FE s2BIT(40)
214 #define SWAPPER_CTRL_XMSI_SE s2BIT(41)
215 #define SWAPPER_CTRL_STATS_FE s2BIT(48)
216 #define SWAPPER_CTRL_STATS_SE s2BIT(49)
217
218 u64 pif_rd_swapper_fb;
219 #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
220
221 u64 scheduled_int_ctrl;
222 #define SCHED_INT_CTRL_TIMER_EN s2BIT(0)
223 #define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)
224 #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
225 #define SCHED_INT_PERIOD TBD
226
227 u64 txreqtimeout;
228 #define TXREQTO_VAL(val) vBIT(val,0,32)
229 #define TXREQTO_EN s2BIT(63)
230
231 u64 statsreqtimeout;
232 #define STATREQTO_VAL(n) TBD
233 #define STATREQTO_EN s2BIT(63)
234
235 u64 read_retry_delay;
236 u64 read_retry_acceleration;
237 u64 write_retry_delay;
238 u64 write_retry_acceleration;
239
240 u64 xmsi_control;
241 u64 xmsi_access;
242 u64 xmsi_address;
243 u64 xmsi_data;
244
245 u64 rx_mat;
246 #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
247
248 u8 unused6[0x8];
249
250 u64 tx_mat0_n[0x8];
251 #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
252
253 u64 xmsi_mask_reg;
254 u64 stat_byte_cnt;
255 #define STAT_BC(n) vBIT(n,4,12)
256
257
258 u64 stat_cfg;
259 #define STAT_CFG_STAT_EN s2BIT(0)
260 #define STAT_CFG_ONE_SHOT_EN s2BIT(1)
261 #define STAT_CFG_STAT_NS_EN s2BIT(8)
262 #define STAT_CFG_STAT_RO s2BIT(9)
263 #define STAT_TRSF_PER(n) TBD
264 #define PER_SEC 0x208d5
265 #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
266 #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
267
268 u64 stat_addr;
269
270
271 u64 mdio_control;
272 #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
273 #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
274 #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
275 #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
276 #define MDIO_OP(val) vBIT(val, 60, 2)
277 #define MDIO_OP_ADDR_TRANS 0x0
278 #define MDIO_OP_WRITE_TRANS 0x1
279 #define MDIO_OP_READ_POST_INC_TRANS 0x2
280 #define MDIO_OP_READ_TRANS 0x3
281 #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
282
283 u64 dtx_control;
284
285 u64 i2c_control;
286 #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
287 #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
288 #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
289 #define I2C_CONTROL_READ s2BIT(24)
290 #define I2C_CONTROL_NACK s2BIT(25)
291 #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
292 #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
293 #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
294 #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
295
296 u64 gpio_control;
297 #define GPIO_CTRL_GPIO_0 s2BIT(8)
298 u64 misc_control;
299 #define FAULT_BEHAVIOUR s2BIT(0)
300 #define EXT_REQ_EN s2BIT(1)
301 #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
302
303 u8 unused7_1[0x230 - 0x208];
304
305 u64 pic_control2;
306 u64 ini_dperr_ctrl;
307
308 u64 wreq_split_mask;
309 #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
310
311 u8 unused7_2[0x800 - 0x248];
312
313
314 u64 txdma_int_status;
315 u64 txdma_int_mask;
316 #define TXDMA_PFC_INT s2BIT(0)
317 #define TXDMA_TDA_INT s2BIT(1)
318 #define TXDMA_PCC_INT s2BIT(2)
319 #define TXDMA_TTI_INT s2BIT(3)
320 #define TXDMA_LSO_INT s2BIT(4)
321 #define TXDMA_TPA_INT s2BIT(5)
322 #define TXDMA_SM_INT s2BIT(6)
323 u64 pfc_err_reg;
324 #define PFC_ECC_SG_ERR s2BIT(7)
325 #define PFC_ECC_DB_ERR s2BIT(15)
326 #define PFC_SM_ERR_ALARM s2BIT(23)
327 #define PFC_MISC_0_ERR s2BIT(31)
328 #define PFC_MISC_1_ERR s2BIT(32)
329 #define PFC_PCIX_ERR s2BIT(39)
330 u64 pfc_err_mask;
331 u64 pfc_err_alarm;
332
333 u64 tda_err_reg;
334 #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
335 #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
336 #define TDA_SM0_ERR_ALARM s2BIT(22)
337 #define TDA_SM1_ERR_ALARM s2BIT(23)
338 #define TDA_PCIX_ERR s2BIT(39)
339 u64 tda_err_mask;
340 u64 tda_err_alarm;
341
342 u64 pcc_err_reg;
343 #define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
344 #define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
345 #define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
346 #define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
347 #define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
348 #define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
349 #define PCC_N_SERR vBIT(0xff,48,8)
350 #define PCC_6_COF_OV_ERR s2BIT(56)
351 #define PCC_7_COF_OV_ERR s2BIT(57)
352 #define PCC_6_LSO_OV_ERR s2BIT(58)
353 #define PCC_7_LSO_OV_ERR s2BIT(59)
354 #define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
355 u64 pcc_err_mask;
356 u64 pcc_err_alarm;
357
358 u64 tti_err_reg;
359 #define TTI_ECC_SG_ERR s2BIT(7)
360 #define TTI_ECC_DB_ERR s2BIT(15)
361 #define TTI_SM_ERR_ALARM s2BIT(23)
362 u64 tti_err_mask;
363 u64 tti_err_alarm;
364
365 u64 lso_err_reg;
366 #define LSO6_SEND_OFLOW s2BIT(12)
367 #define LSO7_SEND_OFLOW s2BIT(13)
368 #define LSO6_ABORT s2BIT(14)
369 #define LSO7_ABORT s2BIT(15)
370 #define LSO6_SM_ERR_ALARM s2BIT(22)
371 #define LSO7_SM_ERR_ALARM s2BIT(23)
372 u64 lso_err_mask;
373 u64 lso_err_alarm;
374
375 u64 tpa_err_reg;
376 #define TPA_TX_FRM_DROP s2BIT(7)
377 #define TPA_SM_ERR_ALARM s2BIT(23)
378
379 u64 tpa_err_mask;
380 u64 tpa_err_alarm;
381
382 u64 sm_err_reg;
383 #define SM_SM_ERR_ALARM s2BIT(15)
384 u64 sm_err_mask;
385 u64 sm_err_alarm;
386
387 u8 unused8[0x100 - 0xB8];
388
389
390 u64 tx_dma_wrap_stat;
391
392
393 #define X_MAX_FIFOS 8
394 #define X_FIFO_MAX_LEN 0x1FFF
395 u64 tx_fifo_partition_0;
396 #define TX_FIFO_PARTITION_EN s2BIT(0)
397 #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
398 #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
399 #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
400 #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
401
402 u64 tx_fifo_partition_1;
403 #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
404 #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
405 #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
406 #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
407
408 u64 tx_fifo_partition_2;
409 #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
410 #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
411 #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
412 #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
413
414 u64 tx_fifo_partition_3;
415 #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
416 #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
417 #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
418 #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
419
420 #define TX_FIFO_PARTITION_PRI_0 0
421 #define TX_FIFO_PARTITION_PRI_1 1
422 #define TX_FIFO_PARTITION_PRI_2 2
423 #define TX_FIFO_PARTITION_PRI_3 3
424 #define TX_FIFO_PARTITION_PRI_4 4
425 #define TX_FIFO_PARTITION_PRI_5 5
426 #define TX_FIFO_PARTITION_PRI_6 6
427 #define TX_FIFO_PARTITION_PRI_7 7
428
429 u64 tx_w_round_robin_0;
430 u64 tx_w_round_robin_1;
431 u64 tx_w_round_robin_2;
432 u64 tx_w_round_robin_3;
433 u64 tx_w_round_robin_4;
434
435 u64 tti_command_mem;
436 #define TTI_CMD_MEM_WE s2BIT(7)
437 #define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
438 #define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15)
439 #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
440
441 u64 tti_data1_mem;
442 #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
443 #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
444 #define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38)
445 #define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39)
446 #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
447 #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
448 #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
449
450 u64 tti_data2_mem;
451 #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
452 #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
453 #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
454 #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
455
456
457 u64 tx_pa_cfg;
458 #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
459 #define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
460 #define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
461 #define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
462 #define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15)
463
464
465 u64 pcc_enable;
466
467 u8 unused9[0x700 - 0x178];
468
469 u64 txdma_debug_ctrl;
470
471 u8 unused10[0x1800 - 0x1708];
472
473
474 u64 rxdma_int_status;
475 u64 rxdma_int_mask;
476 #define RXDMA_INT_RC_INT_M s2BIT(0)
477 #define RXDMA_INT_RPA_INT_M s2BIT(1)
478 #define RXDMA_INT_RDA_INT_M s2BIT(2)
479 #define RXDMA_INT_RTI_INT_M s2BIT(3)
480
481 u64 rda_err_reg;
482 #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
483 #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
484 #define RDA_FRM_ECC_SG_ERR s2BIT(23)
485 #define RDA_FRM_ECC_DB_N_AERR s2BIT(31)
486 #define RDA_SM1_ERR_ALARM s2BIT(38)
487 #define RDA_SM0_ERR_ALARM s2BIT(39)
488 #define RDA_MISC_ERR s2BIT(47)
489 #define RDA_PCIX_ERR s2BIT(55)
490 #define RDA_RXD_ECC_DB_SERR s2BIT(63)
491 u64 rda_err_mask;
492 u64 rda_err_alarm;
493
494 u64 rc_err_reg;
495 #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
496 #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
497 #define RC_FTC_ECC_SG_ERR s2BIT(23)
498 #define RC_FTC_ECC_DB_ERR s2BIT(31)
499 #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
500 #define RC_FTC_SM_ERR_ALARM s2BIT(47)
501 #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
502 u64 rc_err_mask;
503 u64 rc_err_alarm;
504
505 u64 prc_pcix_err_reg;
506 #define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
507 #define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
508 #define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
509 #define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
510 #define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
511 #define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
512 u64 prc_pcix_err_mask;
513 u64 prc_pcix_err_alarm;
514
515 u64 rpa_err_reg;
516 #define RPA_ECC_SG_ERR s2BIT(7)
517 #define RPA_ECC_DB_ERR s2BIT(15)
518 #define RPA_FLUSH_REQUEST s2BIT(22)
519 #define RPA_SM_ERR_ALARM s2BIT(23)
520 #define RPA_CREDIT_ERR s2BIT(31)
521 u64 rpa_err_mask;
522 u64 rpa_err_alarm;
523
524 u64 rti_err_reg;
525 #define RTI_ECC_SG_ERR s2BIT(7)
526 #define RTI_ECC_DB_ERR s2BIT(15)
527 #define RTI_SM_ERR_ALARM s2BIT(23)
528 u64 rti_err_mask;
529 u64 rti_err_alarm;
530
531 u8 unused11[0x100 - 0x88];
532
533
534 u64 rx_queue_priority;
535 #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
536 #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
537 #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
538 #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
539 #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
540 #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
541 #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
542 #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
543
544 #define RX_QUEUE_PRI_0 0
545 #define RX_QUEUE_PRI_1 1
546 #define RX_QUEUE_PRI_2 2
547 #define RX_QUEUE_PRI_3 3
548 #define RX_QUEUE_PRI_4 4
549 #define RX_QUEUE_PRI_5 5
550 #define RX_QUEUE_PRI_6 6
551 #define RX_QUEUE_PRI_7 7
552
553 u64 rx_w_round_robin_0;
554 u64 rx_w_round_robin_1;
555 u64 rx_w_round_robin_2;
556 u64 rx_w_round_robin_3;
557 u64 rx_w_round_robin_4;
558
559
560 #define RX_MAX_RINGS 8
561 #if 0
562 #define RX_MAX_RINGS_SZ 0xFFFF
563 #define RX_MIN_RINGS_SZ 0x3F
564 #endif
565 u64 prc_rxd0_n[RX_MAX_RINGS];
566 u64 prc_ctrl_n[RX_MAX_RINGS];
567 #define PRC_CTRL_RC_ENABLED s2BIT(7)
568 #define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15))
569 #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
570 #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
571 #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
572 #define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
573 #define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23))
574 #define PRC_CTRL_NO_SNOOP_DESC s2BIT(22)
575 #define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23)
576 #define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37)
577 #define PRC_CTRL_GROUP_READS s2BIT(38)
578 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
579
580 u64 prc_alarm_action;
581 #define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3)
582 #define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7)
583 #define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11)
584 #define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15)
585 #define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19)
586 #define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23)
587 #define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27)
588 #define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31)
589 #define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35)
590 #define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39)
591 #define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43)
592 #define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47)
593 #define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51)
594 #define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55)
595 #define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59)
596 #define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63)
597
598
599 u64 rti_command_mem;
600 #define RTI_CMD_MEM_WE s2BIT(7)
601 #define RTI_CMD_MEM_STROBE s2BIT(15)
602 #define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
603 #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15)
604 #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
605
606 u64 rti_data1_mem;
607 #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
608 #define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38)
609 #define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39)
610 #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
611 #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
612 #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
613
614 u64 rti_data2_mem;
615 #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
616 #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
617 #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
618 #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
619
620 u64 rx_pa_cfg;
621 #define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
622 #define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
623 #define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
624 #define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
625
626 u64 unused_11_1;
627
628 u64 ring_bump_counter1;
629 u64 ring_bump_counter2;
630
631 u8 unused12[0x700 - 0x1F0];
632
633 u64 rxdma_debug_ctrl;
634
635 u8 unused13[0x2000 - 0x1f08];
636
637
638 u64 mac_int_status;
639 u64 mac_int_mask;
640 #define MAC_INT_STATUS_TMAC_INT s2BIT(0)
641 #define MAC_INT_STATUS_RMAC_INT s2BIT(1)
642
643 u64 mac_tmac_err_reg;
644 #define TMAC_ECC_SG_ERR s2BIT(7)
645 #define TMAC_ECC_DB_ERR s2BIT(15)
646 #define TMAC_TX_BUF_OVRN s2BIT(23)
647 #define TMAC_TX_CRI_ERR s2BIT(31)
648 #define TMAC_TX_SM_ERR s2BIT(39)
649 #define TMAC_DESC_ECC_SG_ERR s2BIT(47)
650 #define TMAC_DESC_ECC_DB_ERR s2BIT(55)
651
652 u64 mac_tmac_err_mask;
653 u64 mac_tmac_err_alarm;
654
655 u64 mac_rmac_err_reg;
656 #define RMAC_RX_BUFF_OVRN s2BIT(0)
657 #define RMAC_FRM_RCVD_INT s2BIT(1)
658 #define RMAC_UNUSED_INT s2BIT(2)
659 #define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5)
660 #define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6)
661 #define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7)
662 #define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)
663 #define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9)
664 #define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10)
665 #define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11)
666 #define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13)
667 #define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14)
668 #define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15)
669 #define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16)
670 #define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17)
671 #define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18)
672 #define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19)
673 #define RMAC_LINK_STATE_CHANGE_INT s2BIT(31)
674 #define RMAC_RX_SM_ERR s2BIT(39)
675 #define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\
676 s2BIT(8) | s2BIT(9) | s2BIT(10)|\
677 s2BIT(11))
678 #define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\
679 s2BIT(16) | s2BIT(17) | s2BIT(18)|\
680 s2BIT(19))
681 u64 mac_rmac_err_mask;
682 u64 mac_rmac_err_alarm;
683
684 u8 unused14[0x100 - 0x40];
685
686 u64 mac_cfg;
687 #define MAC_CFG_TMAC_ENABLE s2BIT(0)
688 #define MAC_CFG_RMAC_ENABLE s2BIT(1)
689 #define MAC_CFG_LAN_NOT_WAN s2BIT(2)
690 #define MAC_CFG_TMAC_LOOPBACK s2BIT(3)
691 #define MAC_CFG_TMAC_APPEND_PAD s2BIT(4)
692 #define MAC_CFG_RMAC_STRIP_FCS s2BIT(5)
693 #define MAC_CFG_RMAC_STRIP_PAD s2BIT(6)
694 #define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7)
695 #define MAC_RMAC_DISCARD_PFRM s2BIT(8)
696 #define MAC_RMAC_BCAST_ENABLE s2BIT(9)
697 #define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10)
698 #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
699
700 u64 tmac_avg_ipg;
701 #define TMAC_AVG_IPG(val) vBIT(val,0,8)
702
703 u64 rmac_max_pyld_len;
704 #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
705 #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
706 #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
707
708 u64 rmac_err_cfg;
709 #define RMAC_ERR_FCS s2BIT(0)
710 #define RMAC_ERR_FCS_ACCEPT s2BIT(1)
711 #define RMAC_ERR_TOO_LONG s2BIT(1)
712 #define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)
713 #define RMAC_ERR_RUNT s2BIT(2)
714 #define RMAC_ERR_RUNT_ACCEPT s2BIT(2)
715 #define RMAC_ERR_LEN_MISMATCH s2BIT(3)
716 #define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3)
717
718 u64 rmac_cfg_key;
719 #define RMAC_CFG_KEY(val) vBIT(val,0,16)
720
721 #define S2IO_MAC_ADDR_START_OFFSET 0
722
723 #define S2IO_XENA_MAX_MC_ADDRESSES 64
724 #define S2IO_HERC_MAX_MC_ADDRESSES 256
725
726 #define S2IO_XENA_MAX_MAC_ADDRESSES 16
727 #define S2IO_HERC_MAX_MAC_ADDRESSES 64
728
729 #define S2IO_XENA_MC_ADDR_START_OFFSET 16
730 #define S2IO_HERC_MC_ADDR_START_OFFSET 64
731
732 u64 rmac_addr_cmd_mem;
733 #define RMAC_ADDR_CMD_MEM_WE s2BIT(7)
734 #define RMAC_ADDR_CMD_MEM_RD 0
735 #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
736 #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15)
737 #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
738
739 u64 rmac_addr_data0_mem;
740 #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
741 #define RMAC_ADDR_DATA0_MEM_USER s2BIT(48)
742
743 u64 rmac_addr_data1_mem;
744 #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
745
746 u8 unused15[0x8];
747
748
749
750
751
752
753
754
755 u64 tmac_ipg_cfg;
756
757 u64 rmac_pause_cfg;
758 #define RMAC_PAUSE_GEN s2BIT(0)
759 #define RMAC_PAUSE_GEN_ENABLE s2BIT(0)
760 #define RMAC_PAUSE_RX s2BIT(1)
761 #define RMAC_PAUSE_RX_ENABLE s2BIT(1)
762 #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
763 #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
764
765 u64 rmac_red_cfg;
766
767 u64 rmac_red_rate_q0q3;
768 u64 rmac_red_rate_q4q7;
769
770 u64 mac_link_util;
771 #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
772 #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
773 #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
774 #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
775 #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
776 #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
777
778 #define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
779 MAC_RX_LINK_UTIL_DISABLE
780
781 u64 rmac_invalid_ipg;
782
783
784 #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
785 u64 rts_frm_len_n[8];
786
787 u64 rts_qos_steering;
788
789 #define MAX_DIX_MAP 4
790 u64 rts_dix_map_n[MAX_DIX_MAP];
791 #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
792 #define RTS_DIX_MAP_SCW(val) s2BIT(val,21)
793
794 u64 rts_q_alternates;
795 u64 rts_default_q;
796
797 u64 rts_ctrl;
798 #define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2)
799 #define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3)
800
801 u64 rts_pn_cam_ctrl;
802 #define RTS_PN_CAM_CTRL_WE s2BIT(7)
803 #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15)
804 #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15)
805 #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
806 u64 rts_pn_cam_data;
807 #define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7)
808 #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
809 #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
810
811 u64 rts_ds_mem_ctrl;
812 #define RTS_DS_MEM_CTRL_WE s2BIT(7)
813 #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15)
814 #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15)
815 #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
816 u64 rts_ds_mem_data;
817 #define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
818
819 u8 unused16[0x700 - 0x220];
820
821 u64 mac_debug_ctrl;
822 #define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
823
824 u8 unused17[0x2800 - 0x2708];
825
826
827 u64 mc_int_status;
828 #define MC_INT_STATUS_MC_INT s2BIT(0)
829 u64 mc_int_mask;
830 #define MC_INT_MASK_MC_INT s2BIT(0)
831
832 u64 mc_err_reg;
833 #define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14)
834 #define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15)
835 #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18)
836 #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20)
837 #define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22)
838 #define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23)
839 #define MC_ERR_REG_SM_ERR s2BIT(31)
840 #define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\
841 s2BIT(17) | s2BIT(19))
842 #define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\
843 s2BIT(13) | s2BIT(18) | s2BIT(20))
844 #define PLL_LOCK_N s2BIT(39)
845 u64 mc_err_mask;
846 u64 mc_err_alarm;
847
848 u8 unused18[0x100 - 0x28];
849
850
851 u64 rx_queue_cfg;
852 #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
853 #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
854 #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
855 #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
856 #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
857 #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
858 #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
859 #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
860
861 u64 mc_rldram_mrs;
862 #define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39)
863 #define MC_RLDRAM_MRS_ENABLE s2BIT(47)
864
865 u64 mc_rldram_interleave;
866
867 u64 mc_pause_thresh_q0q3;
868 u64 mc_pause_thresh_q4q7;
869
870 u64 mc_red_thresh_q[8];
871
872 u8 unused19[0x200 - 0x168];
873 u64 mc_rldram_ref_per;
874 u8 unused20[0x220 - 0x208];
875 u64 mc_rldram_test_ctrl;
876 #define MC_RLDRAM_TEST_MODE s2BIT(47)
877 #define MC_RLDRAM_TEST_WRITE s2BIT(7)
878 #define MC_RLDRAM_TEST_GO s2BIT(15)
879 #define MC_RLDRAM_TEST_DONE s2BIT(23)
880 #define MC_RLDRAM_TEST_PASS s2BIT(31)
881
882 u8 unused21[0x240 - 0x228];
883 u64 mc_rldram_test_add;
884 u8 unused22[0x260 - 0x248];
885 u64 mc_rldram_test_d0;
886 u8 unused23[0x280 - 0x268];
887 u64 mc_rldram_test_d1;
888 u8 unused24[0x300 - 0x288];
889 u64 mc_rldram_test_d2;
890
891 u8 unused24_1[0x360 - 0x308];
892 u64 mc_rldram_ctrl;
893 #define MC_RLDRAM_ENABLE_ODT s2BIT(7)
894
895 u8 unused24_2[0x640 - 0x368];
896 u64 mc_rldram_ref_per_herc;
897 #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
898
899 u8 unused24_3[0x660 - 0x648];
900 u64 mc_rldram_mrs_herc;
901
902 u8 unused25[0x700 - 0x668];
903 u64 mc_debug_ctrl;
904
905 u8 unused26[0x3000 - 0x2f08];
906
907
908
909
910 u64 xgxs_int_status;
911 #define XGXS_INT_STATUS_TXGXS s2BIT(0)
912 #define XGXS_INT_STATUS_RXGXS s2BIT(1)
913 u64 xgxs_int_mask;
914 #define XGXS_INT_MASK_TXGXS s2BIT(0)
915 #define XGXS_INT_MASK_RXGXS s2BIT(1)
916
917 u64 xgxs_txgxs_err_reg;
918 #define TXGXS_ECC_SG_ERR s2BIT(7)
919 #define TXGXS_ECC_DB_ERR s2BIT(15)
920 #define TXGXS_ESTORE_UFLOW s2BIT(31)
921 #define TXGXS_TX_SM_ERR s2BIT(39)
922
923 u64 xgxs_txgxs_err_mask;
924 u64 xgxs_txgxs_err_alarm;
925
926 u64 xgxs_rxgxs_err_reg;
927 #define RXGXS_ESTORE_OFLOW s2BIT(7)
928 #define RXGXS_RX_SM_ERR s2BIT(39)
929 u64 xgxs_rxgxs_err_mask;
930 u64 xgxs_rxgxs_err_alarm;
931
932 u8 unused27[0x100 - 0x40];
933
934 u64 xgxs_cfg;
935 u64 xgxs_status;
936
937 u64 xgxs_cfg_key;
938 u64 xgxs_efifo_cfg;
939 u64 rxgxs_ber_0;
940 u64 rxgxs_ber_1;
941
942 u64 spi_control;
943 #define SPI_CONTROL_KEY(key) vBIT(key,0,4)
944 #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
945 #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
946 #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
947 #define SPI_CONTROL_SEL1 s2BIT(4)
948 #define SPI_CONTROL_REQ s2BIT(7)
949 #define SPI_CONTROL_NACK s2BIT(5)
950 #define SPI_CONTROL_DONE s2BIT(6)
951 u64 spi_data;
952 #define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
953 };
954
955 #define XENA_REG_SPACE sizeof(struct XENA_dev_config)
956 #define XENA_EEPROM_SPACE (0x01 << 11)
957
958 #endif